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  • Handwritten Notes On SVA 1690023225

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    Purna satya srinivas Vempala
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    12 views17 pages

    Handwritten Notes On SVA 1690023225

    Uploaded by

    Purna satya srinivas Vempala

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 17
    KOTHA VANI oad (a es ae) SYSTEM VERILOG ASSERTIONS Trcbroduction . Syster> Verilog adds features to specify assertions of o syster. Av assertion specifies a behavior of the systers. * Assertions are primarily used to validate the behavior of o design. They can be used to provide functional covero.ge and generate input stimulos -for validation . = An ossertion is a statement that a certain property must be true gi assert property Co I-r x) else derror ("Assertion failed!) ace ote the. piece of verification code that Monitors a design implementation fer compliance with the Speetficattons + Gives ‘whitebor” visibility to a black box design, So,it can find more bugs + Source of the bugs foster: S pase. chepke throughout life-cycle , strength Yegression testing - + Lrrpreves Observability of the design +t vsing assertions one can create unlimited number of observations points any where in the design ee Rees Se Kethe Vani : Tnproves debugging of the design + Assertion help copture the improper functionality of the PUT at or near the sovrce of the See here by neducing the debug time. Who writes Assertions » ————— © White- Bex Verification — luserted by design engineers —+ Bbck Interfaces —+ Internal signals * Black -Bex Verification -¥ Inserted by IP Providers , Vevifrcatron Engineers. —e External uterfacas eyes V2? ‘eovereg See ee Assertion bated Sie Verification « Soving time ' * Low cost Traditional Veriftcation + Small to see Y i time 1 time + Gompasingr with Tradition Verification “here we need hot ees specify in RTL code. tenth of the code Medvees . display is not necessary. ‘Arquoneis (ewe US kotha Vant SV Event Sheduting De ed las Revrous —Preponed} — ——faett 2} “Time Slot Somple stable valuas evaluate assertions» Obseve | execute poss| fail, Statements Reactive Next Time Slo& TTypes ' of Assertions SS Clocked Dnclocked Greoecent Immediate Deferred Final 2009 2o0j2-- 14. Leomediote Assertions- —t Tests an expression when the statement ts executed in the procedoral code. Tt test for a condition at +the corrent +time- + An Immediate vasertion is the same os an if...else Stutement but with assertion contre ls, - ee Kotha Voni low simulation event semantics -for their execution Intended to be used with > Fol the TA oe prirorily sireulation- —t Syotox + vssert (exp [else -foil- statement] ression> Pass statement ye always ©C fonehot) else 4 fatal; assert (oa == generate 0 otal error “0° variable is net a onehet value- as = ‘ 4 Insbontoneeus Bialian Chuck 2. Ft requires more time to debug. 3 Poor readability: 2 ed Immediate A ssertions + fre a type of lmmediate ousertions di (of the keyword final’ ote fssertions evaluate tremediately without variables in ts combinotinal efined with roe Kotha Vane 3. Concvrrent Assertions . at By: using lwmedinte 4 beferred assertions we cart write temporary checks .e Lf Séroulation is hopper ing that whenever * or multiple times 4 protocol say clock cycler B Should be high. is high after 2 + Srmulation is heing- cauvedout by more Mo: of gyclas: multiple Test for 0 Sequence of events spread over Clock cycles: + Asertions occer in precedora | hick, module, initial blocke or Stand -alene- assert property C@cpaedge clk) ##1 COE); mecde Assertion Placement + Instde initial Precedore execute only onee a inttial Once * pssert property (rst); rst is high ot t=0 + Outside of initiol procedure execute Continvously. & assert propertiy (er), en & aluays hag te Ls er Clock -bick Kotho Vani Sequence Property 4+ Sequence —> Peclaves a seguence expression that canbe used in property declavations. local Vatiabler au. pereitted + Build on 4ep of boolean exprenion layer, 4 descrcbe Sequence made of series of events 4 other Sequences — Gn be instantiated in any f o medule , énterface blck, pregram blecks cbckeng Bleck, . - + Liveor Seg i absolute timing relation ts known Non-linear Sey? multiple events trigger a seg + not time ent ss Syntoee! sequence identifier Cformal_argement. list): Z test expressions » : end sequence. os x: sequence ergt veg Htt2 ock; end sequence - 2 Property — Declares during simulation. local vordables ave permitted. — No. of Seguences om combined logically feeg ventrally. Buits won the foendation of seguences 4 Bookan exp. 0 condition [seguence +o be verified Ketho Vani > Roperty declaration can occpr in ao module, interface, program, cloc king- bleckpackape ... Ht Sypstose: property identifier Larger ent lst] 5 5 erdproperty Pataca @Cpaedge clk) alt bs Assertion Statements + & [t+ Assentions : —7 Insure design correctness. “assert property cps —t the dd wssert indicates that o peperty acks as & Checker dovingy Verification Arouoneas joweg US In. Assurnptions : —+ Medel design envivooment. / ousume property gpd: I+the assume keyword indicates preperty behaviour ds assumed 4 shold be treated so gy the verification tool be property holds dering veriftcarblon |3- Cover_Stotements : It To monitor coverage evaluation. “cover property Gp); _t the stutenent 's executed when the peperty Succeeds’ Ketho Vani ye Expeot Sodewent : Vo until the property soccends > Blocks the current process or foils = oceers withina prcedvral block Yeepect Gory-Pyop- ty) pass. stotiments: ese, fosl- stotiments 5 5 Restrictions : — Te verity specify verification constraint. aie ee? Clocking —? Beolases on event to we for sanapil pesesfions values: Multiple Bkceks ¢ cheks inferred from 2 containing only assertions are ¢ : gee ie texpy ) : kotha Vani + Specifies the clock or evert that controls properly evaluation » Tt applies to every assertion in the Some Scope withest o specific clock. rt squree: default clocking. cdentifier Pctke-ex presscony ; Its erdelocking: Hr &e:- defautt cleckeng. de @Cposedge che) 5 endoleckirg . Eire penitence + A property expoenion may be o simple seg expression. “tH property apres may be an invere L ancther property expression « Tt is done scraper operator. Gr preperar not-ex 5 not sts end propery . Property type digjunction - Tt is dene using 2° operator: Sr popes or-ex;, seg! ov seg 2: Kotha Vani ‘ Property type conjunction « expreued ae ond operator: a pope ond-e%; seguex and note; i endproperty. + ‘if nele? type at if foe iy : else = end property: . Over lopped Nwapltcation operator + Alon overlapped Io. Pn inpbetion property, dueribes that occurs when & preceding eee takes place- “the puopely xp must be tive in the lot cop tue - Quran = Ketha Von Arouoneis jowed US the property exp mut be true in the first qyeck aftr the 509 ep is taue - Alon oves lysing’ - indie Sa operator: © (pacdge clk) 79 laryet 5 Sequenre _Spuators * Sequenee opumbors am ied to combine fle too ov move. hoof Sequences, - ond + Both Sequences murt Ocovr, bub the end tirnes of the operands can be different” S1 ond $8 5 - Onterseot Lt Both the sequences must ocowr, and the start and end times of the sSeguence exp must be Same si intersect sa: kB. or L> stout one of the sequence mut ocour sl er 4a; 4 First-motec +t evaluation of one or more Seguencet stops vohen ist match is -foond- ; . sequent® I; Kotha Vani firstemateh (o Ht b Ee? 2) HH dd; end Sequence & roughout + A condition must bold true for the lurection fe fepuemce- a atit c througheut seg; basthio = sequence expaestion + nub wath of same poe within the timeframe Ff Sequence expression 3 of HH we wHha Jeg: 4 deo the yuethed: are ued Ketho bow? Repetition roctors |: Consecutive Repetition Gperator: [¥0]} —t Indicates that the sequence yepeats itself o. peeified no. of Himes Ce Coe Te Peuphy sequence [*o] Fata ae with a range [min mex] la. Alon Conse ctive Repetition _ Opera era ia y+ Jt is similar to ge tr sxepetition gperator except thot ft does mot require thet the [ort match on the signal yepetition hoppers im the cleck gycle before the end of the entire seg insets, It Non consectve repecti tin with oa vange Emin sari] G- Of=i] * the boolsan cb 0 hos been true toice, butt necenatls on succerive clocks 4 thew be additteralcbck cycles after the [ost A hefore the sequence couplets 3 -Gote tion rotor _[- >] + st ends ot tru wl? ec cary —+ If a booltan tor been true for Specified no. of times but not necewayi 4 2m Cencecutive cli cycles! sthe sequence starts with the frst occurance of the : : Ketha Von? boolean c#p qende vith the lor one Cre teu & no gop before the first one and oftir the fart one). Hts wed to specifiy That 0 signal wilt match the no of dimer specified not reces sarily om tour oes che cyelu + —trowge [A mie 5 moa]. Sh cath b (27 ud 3 hisoble Claure Specifies a neret expression checking of the prspety & terminotid sayochronautly. when the expression is tiue- -t diable iff Cexprsion) ~edefiut daotle iff (Lalean.exp) E ee _ @Cporeiye ltd desable iff Crst) Cod it gs pepaty Kotha Vani 3 Feountones + count no of bils in 0 Vecder with Value high + auton type is bik Ds Jolooexx =h 2 “rignesed: le gisunbyeion — check whedter a vector har a bit with value x or Zz B= 100 COCe +o a= eo 10lk +1 Sampled Value Functions b Georepled +> Returns sompled value of expruision pe 4 post + Return pat value of expression . dyose 2 check pohethe exprumdr value ts charged bi ee cleck cyele + Tae le dfell —-F Retuin tine if the Somiplad value of exprenion changed to 0 cusing the coment Clek cycl- E changed + taue, if the value af the cxprenion changed} ¢- dstable + aus, if the value af the expresion did vet Chonge 5 fale, othesise. levels firfo > Simple info 3: fenos + tonlime ‘ ronnie + untime Da & ffatal + guit zimulal Ketha Vani Gatrol Sherr Tasks + Control usiertion cheoking- dosing Aimuulain Ib fossertaff to tum off the assertions gassertaff [Clevels, list of ound); 2 doserter

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