DAY 38 VERIFICATION CHALLENGE - Parameters

1. What are the three kinds of parameters?

Module parameter (keyword : parameter)
Overriding parameter (keyword : defparam)

2. How can I override a modules parameters values during instantiation?

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3. What are the rules governing parameter assignments?

Unique parameter names
Constant values
Data types
Scope of parameters
Parameter overrides

4. How do I prevent selected parameter of a module from being overridden during instantiation?
A particular parameter within a module should be prevented from being overridden, then it should be
declared using the localparam construct, rather than the parameter construct.
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5. What are the differences between using `define and using either parameter or defparam for
specifying the values ?
`define Parameter defparam
`define is used for text `parameter is part of the Verilog `defparam is used for dynamic
substitution during standard and is used to declare assignment of parameter values
preprocessing. It is not a part of constant values within a after module instantiation
the standard Verilog language module. during simulation.
but is commonly supported by
Verilog preprocessors.
`define macros are global and Parameters are local to the `defparam is used at the
can be used anywhere in the module where they are instance level and applies to a
code, including module declared. They can be used in specific module instance.
declarations, tasks, functions, module ports, as well as in the
and procedural blocks. module's internal logic.
There is no type checking for Parameters have explicit data While `defparam provides
`define macros; they are simply types, and the values are type- flexibility, it is generally
replaced wherever they are checked during compilation. considered less preferable than
used. using parameters directly in the
module declaration due to
readability and maintainability
concerns.
Values defined with `define are Parameters can be overridden Values cannot override at
substituted at compile-time. at the instance level during specific time
module instantiation.
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6. What are the pros and cons of specifying the parameters using the defparam construct vs.
Specifying during instantiation?
Defparam Instantiation
Pros Flexibility and centralized Explicitness, readability,compile
configuration time checks
Cons Readability and maintainability, Code repetition and
debugging challenges, limited maintenance
compile time checking
7. What is differnece between the specparam and parameter constructs?
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8. What are derived parameters?when are derived parameters useful, and what are their limitation?
Derived parameters in Verilog are parameters that are computed based on the values of other
parameters. They are calculated during elaboration time, which is the time during compilation before
simulation begins. Derived parameters provide a way to express complex relationships or
computations between different parameters in a concise and readable manner.
Limitation :
They cannot contain dynamic or runtime-dependent constructs.
No Dependency Tracking
Compiler-Specific Behavior

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9. Explain the overriding parameters using defparam with an example?

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10. Explain the meaning of following code snippets :

i) Specify
Specparam t_rise=200, t_fall=150;
endspecify
Explanation :
Specify block should declare inside the module not any procedural blocks, specparam is used to
declare the special parameter inside that block t_rise and t_fall mentioning the rise and fall time of
the clock.
ii) Parameter BUS_WIDTH = 32,DATA_WIDTH = 64;
Explanation :
Parameter keyword is used to declare the constant values inside module it is local scope to thath
module alone. In above statement the bus widht and data width is declared as parameter so we can
use it anywhere inside the module using the same keyword. We can override the values using
defparam keyword.