VLSI DESIGN

18EC72

SET OF POSSIBLE QUESTIONS FOR VTU EXAMINATION

MODULE: 2

1. With the help of neat diagrams, explain the steps involved in NMOS fabrication.
2. With the help of neat diagrams, explain the steps involved in PMOS fabrication.
3. With the help of neat diagrams, explain PWELL fabrication process.
4. With the help of neat diagrams, explain NWELL fabrication process.
5. With the help of neat diagrams, explain Twin Tub fabrication process.
6. In detail explain λ based design rules for different layers used in CMOS.
7. Draw the schematic, stick diagram, using λ based design rules draw layout diagram
for the following
I. CMOS inverter.
II. Two input NAND gate
III. Two input NOR gate
IV. Y = A+BC
V. Y = A+B+C.D
VI. Y = A.(D+E)+B.C
VII. Y = (A+B+C).D
VIII. Y = A.B+C.D
IX. Y = (A+B).C
X. Y = (A.B)+C
8. Describe the steps to be followed to design VLSI chip.
9. What is Scaling? Outline full scaling with the help of neat diagram.
10. Illustrate constant voltage scaling with the help of neat diagram.
11. Explain Drain Induced Barrier Lowering.
12. Describe Surface Scattering with the help of a neat diagram.
13. Describe Hot Carrier Injection with the help of a neat diagram.

14. What is MOSFET capacitance? With expressions, explain Cgb, Cgs, Cgd. Also

draw a DC model of MOSFET capacitances.

Advaith P R, Assistant Professor, Dept. of ECE, SVIT