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LMT86
LMT86
LMT86
SNIS169E – MARCH 2013 – REVISED OCTOBER 2017
90%
80% VDD
FINAL TEMPERATURE
70%
60% LMT86
CBP OUT
50%
40%
30%
GND
20%
10% LMT8xLPG
Thermistor
0
Copyright © 2016, Texas Instruments Incorporated
0 20 40 60 80 100
TIME (s) D003
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMT86
SNIS169E – MARCH 2013 – REVISED OCTOBER 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................... 9
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 11
3 Description ............................................................. 1 9 Application and Implementation ........................ 13
4 Revision History..................................................... 2 9.1 Application Information............................................ 13
9.2 Typical Applications ............................................... 13
5 Device Comparison Tables................................... 3
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 14
7 Specifications......................................................... 5 11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
7.1 Absolute Maximum Ratings ..................................... 5
11.2 Layout Example .................................................... 15
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 16
7.4 Thermal Information .................................................. 5 12.1 Receiving Notification of Documentation Updates 16
7.5 Accuracy Characteristics ......................................... 6 12.2 Community Resources.......................................... 16
7.6 Electrical Characteristics ......................................... 6 12.3 Trademarks ........................................................... 16
7.7 Typical Characteristics .............................................. 7 12.4 Electrostatic Discharge Caution ............................ 16
12.5 Glossary ................................................................ 16
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ......................................... 9
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Updated data sheet text to the latest documentation and translations standards ................................................................. 1
• Added AEC-Q100 automotive qualification bullets to Features ............................................................................................. 1
• Added Time Constant graph................................................................................................................................................... 1
• Removed disk drivers, games, wireless transceivers, and cell phones from Applications..................................................... 1
• Added LPG (TO-92S) package .............................................................................................................................................. 4
• Added Figure 10 to Typical Characteristics............................................................................................................................ 7
• Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application
and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, Mechanical,
Packaging, and Orderable Information .................................................................................................................................. 1
• Added TO92 and TO126 package information....................................................................................................................... 1
• Changed from 450°C/W to 275 °C/W. New specification is derived using TI ' s latest methodology. .................................. 5
• Changed Temperature Accuracy VDD condition from 2.4V to 2.2V for range of 40°C to 150°C. .......................................... 6
• Deleted Note: The input current is leakage only and is highest at high temperature. It is typically only 0.001 µA. The
1 µA limit is solely based on a testing limitation and does not reflect the actual performance of the part............................. 6
(1) For all available packages and complete order numbers, see the Package Option addendum at the end of the data sheet.
(2) AKA = Also Known As
1 5
GND VDD
2
GND LMT86
3 4
OUT VDD
1
VD
LPG Package
D
3-Pin TO-92S
(Top View)
2 T
3 D
O
G
U
N
Scale: 4:1
1
2
3
LPM Package
3-Pin TO-92
(Top View)
1 T
O
U
2 D
3
G
VD
N
Scale: 4:1
1
VD
D
2 T
O
U
3 D
G
N
Scale: 4:1
Pin Functions
PIN DESCRIPTION
TYPE
NAME SOT (SC70) TO-92 TO-92S EQUIVALENT CIRCUIT FUNCTION
GND 1, 2 (1) 3 2 Ground N/A Power Supply Ground
VDD
GND
7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
See
MIN MAX UNIT
Supply voltage –0.3 6 V
Voltage at output pin –0.3 (VDD + 0.5) V
Output current –7 7 mA
(3)
Input current at any pin –5 5 mA
Maximum junction temperature (TJMAX) 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
(2) Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. Reflow temperature
profiles are different for lead-free and non-lead-free packages.
(3) When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > V), the current at that pin should be limited to 5 mA.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For information on self-heating and thermal response time, see section Mounting and Thermal Conductivity.
(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(3) The junction to ambient thermal resistance (RθJA) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
(4) Changes in output due to self-heating can be computed by multiplying the internal dissipation by the thermal resistance.
(1) Limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(3) Accuracy is defined as the error between the measured and reference output voltages, tabulated in the Transfer Table at the specified
conditions of supply gain setting, voltage, and temperature (expressed in °C). Accuracy limits include line regulation within the specified
conditions. Accuracy limits do not include load regulation; they assume no dc load.
(1) Limits are specific to TI's AOQL (Average Outgoing Quality Level).
(2) Typicals are at TJ = TA = 25°C and represent most likely parametric norm.
(3) Source currents are flowing out of the LMT86. Sink currents are flowing into the LMT86.
(4) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest
supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Output Voltage Shift.
(5) Specified by design and characterization.
3
TEMPERATURE ERROR (ºC)
-1
-2
-3
-4
-50 -25 0 25 50 75 100 125 150
TEMPERATURE (ºC)
Figure 1. Temperature Error vs Temperature Figure 2. Minimum Operating Temperature vs
Supply Voltage
Figure 5. Load Regulation, Sourcing Current Figure 6. Load Regulation, Sinking Current
FINAL TEMPERATURE
70%
60%
50%
40%
30%
20%
10% LMT8xLPG
Thermistor
0
0 20 40 60 80 100
TIME (s) D003
Figure 9. Output Voltage vs Supply Voltage Figure 10. LMT86LPG Thermal Response vs Common
Leaded Thermistor With 1.2-m/s Airflow
8 Detailed Description
8.1 Overview
The LMT86 is an analog output temperature sensor. The temperature-sensing element is comprised of a simple
base emitter junction that is forward biased by a current source. The temperature-sensing element is then
buffered by an amplifier and provided to the OUT pin. The amplifier has a simple push-pull output stage thus
providing a low impedance output source.
VDD
OUT
Thermal Diodes
GND
Although the LMT86 is very linear, its response does have a slight umbrella parabolic shape. This shape is very
accurately reflected in Table 3. The Transfer Table can be calculated by using the parabolic equation
(Equation 1).
ª mV º ª mV 2º
VTEMP mV = 1777.3mV - «10.888 T - 30°C » - «0.00347 2 T - 30°C »
¬ °C ¼ ¬ °C ¼ (1)
The parabolic equation is an approximation of the transfer table and the accuracy of the equation degrades
slightly at the temperature range extremes. Equation 1 can be solved for T resulting in:
2
10 .888 10 .888 4 u 0.00347 u 1777 .3 VTEMP mV
T 30
2 u ( 0.00347 ) (2)
For an even less accurate linear approximation, a line can easily be calculated over the desired temperature
range from the table using the two-point equation (Equation 3):
¹
V - V1 = · V2 - V1 · u (T - T1)
T2 - T1 ¹
where
• V is in mV,
• T is in °C,
• T1 and V1 are the coordinates of the lowest temperature,
• and T2 and V2 are the coordinates of the highest temperature. (3)
For example, if the user wanted to resolve this equation, over a temperature range of 20°C to 50°C, they would
proceed as follows:
¹
1558 mV - 1885 mV·
V - 1885 mV = · u (T - 20oC)
50oC - 20oC ¹ (4)
o o
V - 1885 mV = (-10.9 mV / C) u (T - 20 C) (5)
o
V = (-10.9 mV / C) u T + 2103 mV (6)
Using this method of linear approximation, the transfer function can be approximated for one or more
temperature ranges of interest.
where
• TA is the ambient temperature,
• IS is the supply current,
• ILis the load current on the output,
• and VO is the output voltage. (7)
For example, in an application where TA = 30°C, VDD = 5 V, IS = 5.4 µA, VO = 1777 mV junction temp 30.014°C
self-heating error of 0.014°C. Because the junction temperature of the LMT86 is the actual temperature being
measured, take care to minimize the load current that the LMT86 is required to drive. Thermal Information (1)
shows the thermal resistance of the LMT86.
(1) For information on self-heating and thermal response time, see section Mounting and Thermal Conductivity.
Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMT86
LMT86
SNIS169E – MARCH 2013 – REVISED OCTOBER 2017 www.ti.com
LMT86
OUT
OPTIONAL
BYPASS GND CLOAD ” 1100 pF
CAPACITANCE
Figure 11. LMT86 No Decoupling Required for Capacitive Loads Less Than 1100 pF
VDD
RS
LMT86
OUT
OPTIONAL
BYPASS GND
CAPACITANCE CLOAD > 1100 pF
Figure 12. LMT86 With Series Resistor for Capacitive Loading Greater Than 1100 pF
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Input
LMT86 RMUX RSS Sample
Pin
VDD OUT
CBP GND CMUX
CFILTER CSAMPLE
2.5
OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
0.0
±50 0 50 100 150
TEMPERATURE (ƒC)
C001
Time: 500 µs/div; Top Trace: VDD 1 V/div; Time: 500 µs/div; Top Trace: VDD 1 V/div;
Bottom Trace: OUT 1 V/div Bottom Trace: OUT 1 V/div
Figure 16. Output Turnon Response Time Without a Figure 17. Output Turnon Response Time With a 1.1-nF
Capacitive Load and VDD = 3.3 V Capacitive Load and VDD = 3.3 V
Time: 500 µs/div; Top Trace: VDD 2 V/div; Time: 500 µs/div; Top Trace: VDD 2 V/div;
Bottom Trace: OUT 1 V/div Bottom Trace: OUT 1 V/div
Figure 18. Output Turnon Response Time Without a Figure 19. Output Turnon Response Time With 1.1-nF
Capacitive Load and VDD = 5 V Capacitive Load and VDD = 5 V
11 Layout
GND VDD
GND 0.01µ F
OUT VDD
OUT
GND
OUT
GND
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 13-Nov-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LMT86DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-1-260C-UNLIM -50 to 150 BSA Samples
LMT86DCKT LIFEBUY SC70 DCK 5 250 RoHS & Green SN Level-1-260C-UNLIM -50 to 150 BSA
LMT86LP ACTIVE TO-92 LP 3 1800 RoHS & Green SN N / A for Pkg Type -50 to 150 LMT86 Samples
LMT86LPG ACTIVE TO-92 LPG 3 1000 RoHS & Green SN N / A for Pkg Type -50 to 150 LMT86 Samples
LMT86LPGM ACTIVE TO-92 LPG 3 3000 RoHS & Green SN N / A for Pkg Type -50 to 150 LMT86 Samples
LMT86LPM ACTIVE TO-92 LP 3 2000 RoHS & Green SN N / A for Pkg Type -50 to 150 LMT86 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 13-Nov-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive : LMT86-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Oct-2021
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Oct-2021
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA
1 5
2X 0.65 NOTE 4
2.15
1.3 (0.15) 1.3
2 1.85
(0.1)
4
0.33 3
5X
0.23
0.1
0.1 C A B (0.9) TYP
0.0
0.15
GAGE PLANE 0.22
TYP
0.08
8 0.46
TYP TYP
0 0.26
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X (0.65)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214834/C 03/2023
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X(0.65)
3 4
(R0.05) TYP
(2.2)
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
LPG0003A SCALE 1.300
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
4.1
3.9
3.25
3.05 0.55
3X
0.40 5.05
MAX
1 3
3X (0.8)
3X
15.5
15.1
0.48 0.51
3X 3X
0.35 0.36
2X 1.27 0.05
2.64
2.44
2.68
2.28
1.62
2X (45 ) 1.42
1 2 3
(0.5425) 0.86
0.66
4221343/C 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
LPG0003A TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
FULL R
0.05 MAX (1.07) TYP
METAL
ALL AROUND TYP 3X ( 0.75) VIA
TYP
2X
METAL
(1.7) 2X (1.7)
2X
SOLDER MASK
OPENING
1 2 3
(R0.05) TYP 2X (1.07)
(1.27)
SOLDER MASK
OPENING (2.54)
4221343/C 01/2018
www.ti.com
TAPE SPECIFICATIONS
LPG0003A TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
0 1
13.0 0 1
12.4
1 MAX
21
18
2.5 MIN
6.5
5.5
9.5
8.5 0.25
0.15
19.0
17.5
4221343/C 01/2018
www.ti.com
PACKAGE OUTLINE
LP0003A SCALE 1.200 SCALE 1.200
TO-92 - 5.34 mm max height
TO-92
5.21
4.44
EJECTOR PIN
OPTIONAL
5.34
4.32
(1.5) TYP
(2.54) SEATING
2X NOTE 3 PLANE
4 MAX
(0.51) TYP
6X
0.076 MAX
SEATING
PLANE
3X
12.7 MIN
0.43
2X 0.55 3X
3X 0.35
2.6 0.2 0.38
2X 1.27 0.13
FORMED LEAD OPTION
OTHER DIMENSIONS IDENTICAL STRAIGHT LEAD OPTION
TO STRAIGHT LEAD OPTION
2.67
3X
2.03 4.19
3.17
3 2 1
3.43 MIN
4215214/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within this area.
4. Reference JEDEC TO-226, variation AA.
5. Shipping method:
a. Straight lead option available in bulk pack only.
b. Formed lead option available in tape and reel or ammo pack.
c. Specific products can be offered in limited combinations of shipping medium and lead options.
d. Consult product folder for more information on available options.
www.ti.com
EXAMPLE BOARD LAYOUT
LP0003A TO-92 - 5.34 mm max height
TO-92
FULL R
0.05 MAX (1.07) TYP
ALL AROUND METAL 3X ( 0.85) HOLE
TYP TYP
2X
METAL
(1.5) 2X (1.5)
2X
SOLDER MASK
OPENING
1 2 3
(R0.05) TYP 2X (1.07)
(1.27)
SOLDER MASK
(2.54)
OPENING
METAL
2X
1 2 3 SOLDER MASK
(R0.05) TYP
(2.6) OPENING
SOLDER MASK
OPENING (5.2)
4215214/B 04/2017
www.ti.com
TAPE SPECIFICATIONS
LP0003A TO-92 - 5.34 mm max height
TO-92
13.7
11.7
32
23
16.5
15.5
11.0 9.75
8.5 8.50
19.0
17.5
4215214/B 04/2017
www.ti.com
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