CHAMP-XD3
3U VPX Intel Ice Lake Xeon D-1700 HPEC and Cognitive
DSP Module Aligned with The SOSA ™ Technical Standard
Key Features
• Intel Ice Lake Xeon D-1746TER 10
Core with 48 GB SDRAM in 3 channels
(contact factory for 4 or 8 cores)
• Dual 10 GbE-KR ports
• 40 GbE Data Plane
• AMD Zynq UltraScale+ MPSoC FPGA
with independent DDR4 memory for
enhanced security or co-processor
functionality
• IPMI (Vita 46.11) with Host 3.0
support
• One or two channels of NVMe SSD
supporting up to 160 GB SLC/480 GB
TLC secure storage per channel
• TrustedCOTS TM
protections
• Variants aligned with the Payload
Plug-In Card Profile from the SOSATM
Technical Standard
Applications
• Multi-mode Radar
• Synthetic Aperture Radar (SAR)
• Signal Intelligence (SIGINT)
• Electro-Optical/Infrared (EO/IR)
• Electronic warfare (EW)
• Virtualized and mission computing
• Industrial server applications
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The CHAMP-XD3 is available in both SOSA and IO enhanced options.
Overview
The 3U OpenVPX ™ CHAMP-XD3 (VPX3-484) security-enhanced,
cognitive, rugged digital signal processor (DSP) engine module is
designed for use in very compute-intensive industrial, aerospace,
and defense applications, enabling developers of High Performance
Embedded Computing (HPEC) systems to take full advantage of
the unmatched performance of today’s latest Intel ® Ice Lake Xeon ®
D-1700 architecture.
The CHAMP-XD3 combines the high core count and floating-point
performance of the Intel “Ice Lake D” processor with the substantial
bandwidth and system-enabling features of the VITA 3U OpenVPX
form-factor. Providing an extended temperature Xeon D-1700 LCC
processor with 10 hyper-threading cores, the CHAMP-XD3 brings
Intel’s new AVX512 floating-point capability to the rugged embedded
marketplace. Processor performance is enhanced with 48 GB of
high capacity DDR4-2400 in three independent memory channels,
providing over 50% more memory bandwidth than prior generation
modules ensuring memory accesses are not a bottleneck.
The Ice Lake D processor provides new Intel Deep Learning Boost
with optimized commands for AI applications which are ideal for
cognitive EW and other smart sensor processing applications.
Aligned with the SOSA Technical Standard, the CHAMP-XD3
supports a 40GbE Data Plane, dual 10 GbE interfaces, and up to 16
lanes of Gen3 PCI Express ® (PCIe) on the Expansion Plane, with a
pinout aligned to the Payload PIC profile of the SOSA standard
The CHAMP-XD3 includes a AMD ® Zynq ® UltraScale+™ MPSoC
field programmable gate array (FPGA) with additional security
features, embedded quad-core Arm ® A53 processor and dual-core
R5 processor used for enhanced TrustedCOTS security, as a co-
processor or for general purpose I/O. System monitoring and health
is supported with IPMI (VITA 46.11) with HOST extensions as required
for SOSA conformance.
Available in a conduction-cooled 3U VPX form factor with two level
maintenance covers, the CHAMP-XD3 provides the processing
performance, I/O and memory bandwidth, and ruggedization needed
to address the most challenging sensor processing applications.
 CHAMP-XD3

DDR4 16 GB 2400 MT/s

DDR4 16 GB 2400 MT/s Intel® Xeon D
DDR4 16 GB 2400 MT/s 10‐core
D‐1746TER
SSD Flash PCIe
“Ice Lake D”
SSD Flash PCIe

SPI x4 PCIe x2 PCIe x1 PCIe

NVRAM LPC
Gen2 Gen2 Gen2
TPM 2.0
PABS PS
10G
MAC
BIOS SPI
AMD
Jumpers ZYNQ x4
Ultrascale+

10GBASE‐KR or
1000BASE‐KX
MPSOC Flash 40GbE‐KR4

10GBASE‐KR
2Gb PABS & QSPI
2Gb BootFlash FPGA GigE Power

USB 3.0
USB 2.0
SATA 2
NIC Supplies
4 GB DDR4 2133 MHz
x8 PCIe Clock
Generation

3.3V_AUX
IPMI

VS1 (12V)
1x RS‐422 4x MAG Gen3
or

VBAT
DIO x8 PCIe
FPGA 2x
2x RS‐232
1000Base‐T REFCLK
1x HSS Gen3
Maint Ports 1PPS
LVCMOS/RS‐232 3x LVDS

IPMB Maint COM P2 P1

Expansion UTP P1 FP Clocks Power
A/B Ctl
Ports Port Plane Data Data
Plane
Not Available on SOSA Profile Plane Plane

CHAMP-XD3 block diagram

Leveraging Curtiss-Wright’s extensive 3U OpenVPX • Intel AI Acceleration with Deep Learning Boost (VNNI)
ecosystem, the CHAMP-XD3 forms the centerpiece of • Intel Total Memory Encryption (TME)
new small form factor HPEC system architectures that
need to be aligned to the SOSA Technical standard. • 67W TDP package supported
Other Curtiss-Wright 3U OpenVPX modules available for
HPEC configurations include Single Board Computers, Processor SDRAM Memory
Ethernet Switches, Graphics/GPGPU Processors, and • 3 x channels DDR4 SDRAM operating at, 2400 MT/s
FPGA-based processing modules. • 16 GB per channel with ECC
• Supports total memory encryption (TME) with processor
Specifications FPGA Memory
Processor • 1 channel DDR4 SDRAM 2133 MT/S
• Intel Ice Lake Xeon D-1746TER Processor with integrated • 4 GB with ECC
Platform Controller Hub (PCH) • 4 Gb QSPI Flash for MPSoC boot Flash
• 10-core (20-thread) processor operating at 2.0 GHz base
clock Non-Volatile Memory
+ Supports all-core turbo operation to 2.5 GHz • Single or dual channel NVMe SSD Flash
+ Also supports non-turbo SST-BP profile with 6-core @ + 80 or 160 GB (SLC) or 480 GB (TLC) per channel
2.5GHz + 4-core @ 1.0 GHz + Supports write protection and sanitization with path to
• Intel Advanced Vector Extensions (AVX, AVX2, AVX512) encryption
floating-point • 2 x 16 MB SPI Flash for UEFI BIOS
• Intel Virtualization Technology (VT-x, VT-d) • 512 KB NVRAM

© 2023 Curtiss-Wright. All rights reserved. Specifications are subject to change

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This document was reviewed on 11August2023, and does not contain technical data.

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 CHAMP-XD3

Backplane Fabrics • Multiple interfaces to processor including LPC and PCIe

• PCIe Expansion Plane
+ Up to 16 lanes of PCIe Gen3 to backplane
+ Supports bifurcation down to 4x4
• 40G Ethernet Data Plane
+ 4-lane 40GBase-KR4 or 4 x 10GBase-KR operation
+ RoCE and high-performance DMA support
• 10 GbE or 1 GbE Control and Data Plane
+ 2 x 10GBASE-KR / 1000BASE-KX (backplane)
+ Includes Stratum 3 TCXO for enhanced accuracy for PTP
with capability to lock to 1 PPS Aux CLK
• GbE BASE-T
+ 1 x 10/100/1000BASE-T
+ Includes Stratum 3 TCXO for enhanced accuracy for PTP
for Ice Lake Xeon D-1700, with capability to lock to 1
PPS Aux CLK
I/O Interfaces
• Digital I/O (DIO)
+ 1 x 3.3V tolerant DIO
• Serial Ports
+ 2 x LVCMOS Maintenance Ports (contact factory for
RS232 options)
I/O Interfaces (non-SOSA variants)
• SATA 3.0
• 1 x watchdog timer
• 5 x general-purpose timers
• PCIe to 10GbE Ethernet MAC
FPGA Memory
• 1 channel DDR4 SDRAM operating at 2,133 MT/s
• 4 GB with ECC
• Dual 2 Gbit QSPI Flash for MPSoC boot Flash
FPGA Security Features
• 256bit entropy PUF option
• Contact factory for security IP options
IPMC FPGA
• Microsemi SmartFusion 2 device
• Supports VITA 46.11 (IPMI) Tier 1, Tier 2, including HOST
extensions per SOSA requirements
Security Features (Contact Factory for Availability)
• Intel Bootguard, SGX, UEFI Secure Boot, and TME
support
• DPA-resistant Core FPGA, with embedded processor and
optional physically unclonable function (PUF)
• DPA-resistant IPMC FPGA
• Enables secure and authenticated boot infrastructure with
independent hardware PUF Root-of-Trust

+ Backplane • Memory module with embedded termination resistors for

MPSOC SDRAM
• USB 2.0
• Control plane link to FPGA
+ 1 x USB 2.0
• TPM 2.0 (FIPS and Common Criteria certified)
• USB 3.0
• SSD with encryption and write protection capability
+ 1 x USB 3.0 to backplane
• Zeroization capability
• Digital I/O (DIO)
• FPGA toolkit provides a framework for security
+ 3 x additional 3.3V tolerant DIO customization
+ 3 x differential DIO
Mechanical
+ 1 x HSS link from FPGA
• Conduction-cooled VITA 48.2 with covers
• Serial Ports
+ 2 x RS-232 ports (or one RS-422) Power
Power consumption will vary based on operational loading.
Core and Security FPGA Values below are guidelines when operating with 10 cores
Provides logical hardware services and security capabilities @ 2.0 GHz at room temperature (25°C) – contact Curtiss-
to CHAMP-XD3. Wright for more details on power consumption.
• AMD ZU4EG/ZU5EG MPSoC • Idle power consumption: 42 watts
+ Quad-core A53 processor with NEON FPU • Typical power consumption: 85 watts
+ Dual-core R5 processor • Maximum power consumption: 125 watts

CURTISSWRIGHTDS.COM

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 CHAMP-XD3
Backplane I/O Variants
• Supports SOSA-Aligned OpenVPX profiles:
+ MOD3-PAY-1F1U1S1S1U1U2F1H-16.6.11-11 SOSA
Payload Profile with 8-lane PCIe Expansion Plane
+ AMPS: MODA3-16.6.11-11-1-F2C-(E8-E7)(P3F-P3F)(E7)
(N)
› This module profile is intended for backplanes
that support the following slot profile: SLT3-PAY-
1F1U1S1S1U1U2F1H-14.6.11-x
+ MOD3-PAY-1F1U1S1S1U1U4F1J-16.6.13-1 SOSA
Payload Profile with 16-lane PCIe Expansion Plane)
+ AMPS: MODA3-16.6.13-11-1-F2C-(E8-E7)(2P3F-2P3F)
(E7)(N)
› This module profile is intended for backplanes
that support the following slot profile: SLT3-PAY-
1F1U1S1S1U1U4F1J-14.6.13-x
• Additional non-SOSA variants available for support of USB/
SATA/1GBASE-T/RS-232/DIO on lower half of P2. Contact
factory for details.
See Ordering Information for more details.
Weight
• 1115g (including covers)
Software
• AlmaLinux pre-loaded from the factory
• BSP available for AlmaLinux and Red Hat Enterprise Linux
(RHEL)
Security Toolkit
• Reference design for MPSoC FPGA
• Includes IP for base MPSoC design
• Additional security module add-ons options include:
+ Full secure boot including authentication of MPSoC and
Intel Bootcode with hardware MPSoC PUF
+ Memory encryption
+ JTAG protection
+ Additional features
Contact factory for security details.
CURTISSWRIGHTDS.COM
Intel Ice Lake Xeon D-1700
Processor
The CHAMP-XD3 features the 10-core extended temperature
Intel Ice Lake Xeon D-1700 LCC processor. Lower power
applications can also be supported with the 8-core and
4-core processor SKUs. The Ice Lake Xeon D-1700 brings
a number of key enhancements over the prior generation
Xeon D (Broadwell DE) processor including:
• AVX vector math engine doubling from 256 to 512 bits
• A third memory channel for over 50% more memory
bandwidth
• Architectural enhancements and VNNI instruction set for
an order of magnitude performance improvement for AI/
ML functions
• Intel Bootguard, SGX and Total Memory Encryption for
enhanced security
• Resource Director Technology for enhanced determinism
AMD Zynq UltraScale+
MPSoC FPGA
The AMD Zynq UltraScale+ MPSoC FPGA is the heart of
the security center for the CHAMP-XD3. When configured
for optimal security, it becomes a DPA-resistant, encrypted,
and authenticated guardian to ensure the integrity of its
own image and the Intel processor boot image, as well
as monitoring for unexpected behavior. An internal PUF
can be used as an independent hardware root-of-trust for
the authentication of the firmware and software entities
resident on the module. Featuring a quad-core Arm A53
processor, the FPGA can provide independent software
monitoring or co-processor functionality in addition to the
Xeon processor. The FPGA can be independently controlled
via one of the serial ports, and has high-speed connections
to the Intel processor via a 4-lane PCIe Gen2 link. External
I/O is provided to the backplane via HSS or LVDS signals.
It is also connected to the IPMC FPGA device for additional
monitoring capability and cross-authentication.
With a combination of the quad-core Arm A53 processor
and two R5 processors, hardened crypto functions, and a
large array of programmable logic, as well as hooks into
much of the logic on the module, the FPGA provides a
robust platform for monitoring and responding to an array
of security threats.
Curtiss-Wright offers an FPGA toolkit which implements a
fully instantiated reference design suitable for custom IP
development. A number of 3rd party FPGA security packages
will also be available for the CHAMP-XD3. Contact Curtiss-
Wright for more details.
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 CHAMP-XD3
In addition to security, the FPGA can be used for other co-
processing functions, or, in conjunction with some of the
backplane I/O, the FPGA can be used as a configurable I/O
controller.
SDRAM
The Xeon D processor has three independent 16 GB banks
of 72-bit DDR4 SDRAM (64-bit plus ECC). Processor DRAM
operates at 2,400 MT/s for a total memory throughput of
57.6 GB/s. For enhanced security, the processor DRAM
memory can be protected utilizing the Xeon processor’s
Total Memory Encryption (TME) capability, ensuring all data
written to the memory is encrypted.
The MPSoC FPGA has an additional 4 GB of DDR4 SDRAM,
which can be utilized by the Arm processors within the FPGA.
The FPGA DRAM interface runs at 2,133 MT/s providing 17
GB/s of memory bandwidth. The Intel processor also has
access to this memory over the PCIe link.
NVMe SSD
The CHAMP-XD3 supports one or two channels of high-
performance Non-Volatile Memory Express (NVMe) local
SSD storage, maximizing performance and eliminating
traditional performance bottlenecks associated with SATA
connected storage. SSD capacity options include 80 GB or
160 GB devices operating in SLC mode for the highest level
of reliability and endurance, or 480 GB devices operating in
TLC mode for applications requiring higher capacity.
The SSDs also include unique features to enhance reliability,
as well as support for write protection and quick erase
capability for optimal handling of sensitive data.
Trusted Platform Module
(TPM)
The CHAMP-XD3 includes a Trusted Platform Module (TPM)
2.0 hardware security device. The TPM can be used to create
a secure computing environment, ensuring only trusted and
signed UEFI BIOS and software can execute on the board.
The TPM device is certified to FIPS-140-2 and Common
Criteria security standards, and is available to the operating
system for application security functions.
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IPMI Health Management
The CHAMP-XD3 features an independent SmartFusion2
FPGA to support IPMC health and management functions
and is compliant to VITA 46.11 (Tier 1 and Tier 2) and SOSA
(with HOST extensions) requirements.
The SmartFusion2 has its own security features, and can
also be encrypted to strengthen board level security. Both
the Intel processor and AMD MPSoC FPGA have access to
this resource.
Data Plane
The CHAMP-XD3 has a high-performance, low-latency 40
GbE data plane as defined by the SOSA Technical standard.
This 40GBase-KR4 interface is connected directly to the
Intel processor. The Intel Ethernet core supports RoCE
V2. The 4-lane Data Plane can also be configured as four
independent 10GBase-KR Ethernet ports.
Please contact Curtiss-Wright for 100GbE Data Plane
product options.
Expansion Plane
The CHAMP-XD3 support 8-lanes or 16-lanes of Gen3 PCIe
on the Expansion Plane. These are intended to connect
point-to-point to an FPGA or GPGPU or similar module.
Bifurcation down to x4 links is supported.
Please contact Curtiss-Wright for PCIe Gen4 product
options.
Ethernet Ports
In addition to the 40 GbE Data Plane interface, there are two
10 GbE interfaces which align with the control plane interface
and the non-real-time data plane as defined by the SOSA
Technical Standard. The non-real-time data plane interface
is connected to the MPSOC FPGA and can be controlled
by the Intel processor through a dedicated PCIe interface.
Alternatively, with a different FPGA load, this interface could
be controlled by the Arm cores within the MPSOC FPGA. The
other 10 GbE interface is the control plane interface directly
connected to the Intel processor. The 10 GbE interfaces
when utilized with switch cards that support precision-
time-protocol (PTP), such as the Curtiss-Wright VPX3-687,
can provide system level timing accuracy within 10s of ns,
even with variable traffic. Stratum 3 clock sources for the
Ethernet interfaces also provide a high level of stability for
optimal handling of situations where the reference clock is
lost. The clocks for the Ethernet connections can optionally
be synchronized to the 1PPS Aux CLK.
5
 CHAMP-XD3
In addition to the dual 10 Gbe interfaces, the CHAMP-XD3
offers an additional 1000BASE-T port connected to the
backplane for external connectivity. The 1000BASE-T link is
only available on non-SOSA variants.
Additional I/O Interfaces
The CHAMP-XD3 supports additional I/O interfaces on the
bottom half of P2, which are only available with a full P2
connector populated. Applications that do not require full
SOSA conformance can use these additional interfaces for
enhanced functionality.
The following additional interfaces are available:
• 1 x 1000Base-T Ethernet port
• 2 x RS-232 or 1 x RS-422 serial port
• 1 x SATA 2.0 port
• 1 x USB 3.0 port
• 3 x additional 3.3V tolerant DIO
• 1 x High Speed Serial (HSS) interface to the MPSoC
FPGA
• 3 x LVDS interfaces to the MPSoC FPGA
FPGA Toolkit Support
An FPGA toolkit is available for the MPSOC FPGA. This
toolkit includes all the IP used in the base (reference)
design, along with a simulation environment, build scripts,
and documentation. The toolkit allows customization of the
MPSoC FPGA to support additional security, processing, or
monitoring functionality.
Please contact Curtiss-Wright for additional information on
advanced security features and additional orderable security
FPGA capabilities.
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Operating System Software
The CHAMP-XD3 is supported with an extensive array of
software items, which cover all facets of developing and
running application code for the board. The following 64-bit
operating systems are supported for the CHAMP-XD3
• Alma Linux 8.6 (pre-installed from the factory)
• Red Hat Enterprise Linux (RHEL) 8.6
For information regarding additional OS support, please
contact Curtiss-Wright.
Rear Transition Module
For building systems in the lab environment, Curtiss-Wright
offers a Rear Transition Module (RTM) and breakout cable
that plugs into the backside of the CHAMP-XD3’s backplane
and provides access to most of the board connections on
industry standard connectors.
Ruggedization Levels
The CHAMP-XD3 is offered in a conduction-cooled form
factor with 2-level maintenance (2LM) covers.
The CHAMP-XD3 supports the full L100 -40 to +71°C card
edge temperature with near full utilization of all processor
cores, memory interfaces, and peripherals. Operation is also
supported at higher temperatures with reduced processor
loading.
Please contact Curtiss-Wright for full thermal details and
operational characterization.
6
 CHAMP-XD3

Ordering Information
TABLE 1 CHAMP-XD3 Ordering Information
PART NUMBER AVAILABLE OPTIONS
CHAMP-XD3 3U VPX high-performance DSP engine featuring
Intel Ice Lake Xeon D-1700 10-core processor
› System memory: 48 GB of DDR4-2400
› AMD MPSoC FPGA with 4 GB of DDR4-2133 SDRAM
› CC-L100 ruggedization (max utilization): conduction-cooled with covers 1.0” pitch
X: Backplane Profile
0 = SOSA Payload, no P2
1 = SOSA Payload, 1/2 P2
2 = Full Backplane with optional I/O
Y: Processor SKU and FPGA SKU
VPX3-484-C15xyzo
0 = 10-core Ice Lake Xeon D-1746TER - ZU4EG AMD Ultrascale+ Zynq FPGA
(contact factory
4 = 10-core Ice Lake Xeon D-1746TER - ZU4EG FPGA with 256b PUF
to confirm valid
7 = 10-core Ice Lake Xeon D-1746TER - ZU5EG FPGA with 256b PUF
combinations)
Z: Memory Configuration
0 = 48 GB SDRAM, 80 GB SLC SSD
1 = 48 GB SDRAM, dual 80 GB SLC SSD
2 = 48 GB SDRAM, dual 160 GB SLC SSD
3 = 48 GB SDRAM, dual 480 GB TLC SSD
4 = 48 GB SDRAM, no SSD
O: Options
“-E” appended to part number for early access units (EAU). EAUs may vary slightly and are not fully
qualified and may have other limitations.
Contact factory for additional permutations
Rear Transition Module (RTM) for the SOSA aligned variant of the CHAMP-XD3 with x8 PCIe to the
RTM3-SBC-1001
backplane. Includes breakout cable.
Rear Transition Module (RTM) for the non-SOSA aligned variant of the CHAMP-XD3 that has the full P2.
RTM3-484-0000
Includes breakout cable.
RHEL and AlmaLinux board support package (BSP) and driver suite for the Curtiss-Wright CHAMP-XD3
DSW-484-6850-RHL6
(VPX3-484). Includes driver source code.
Annual Software Upgrade/Maintenance Program (SUP) for the CHAMP-XD3 BSP. First year mandatory
MNT-484-6800-RHL6
with DSW-484 BSP purchase.
DSW-484-FPGA-000 Base AMD MPSoC FPGA Toolkit for CHAMP-XD3 Module
Annual Software Upgrade/Maintenance Program (SUP) for the CHAMP-XD3 FPGA toolkit. First year
MNT-484-FPGA-000
mandatory with DSW-484-FPGA purchase.
DPK-484-SI-000 S-Parameters file for CHAMP-XD3 high speed backplane interfaces
Contact Curtiss-Wright for additional product configurations.

© 2023 Curtiss-Wright. All rights reserved. Specifications are subject to change

CURTISSWRIGHTDS.COM without notice. All trademarks are property of their respective owners I D437.120222
This document was reviewed on 11August2023, and does not contain technical data.