EC8552 - COMPUTER ARCHITECTURE AND ORGANIZATION

UNIT I
COMPUTER ORGANIZATION & INSTRUCTIONS
Basics of a computer system: Evolution, Ideas, Technology, Performance, Power wall,
Uniprocessors to Multiprocessors. Addressing and addressing modes. Instructions: Operations
and Operands, Representing instructions, Logical operations, control operations.

1 How many bytes required to form a kilo byte

a. 1000
b. 1024
c. 1042
d. 1240
2 Identify the 16 bit microprocessor
a. 8080
b. 8085
c. 8086
d. 8087
3 Role of assembler is
a. HLL to ALP
b. ALP to HLL
c. ALP to machine
d. All of the above
4 The 8-bit encoding format used to store data in a computer is
a. ASCII
b. EBCDIC
c. ANCI
d. USCII
5 Modern computers are designed using ___
a. SSI
b. MSI
c. LSI
d. VLSI
6 In CPU increasing clock frequency which will
a. Increase static power dissipation
b. Decrease static power dissipation
 c. Increase dynamic power dissipation
d. Decrease static power dissipation
7 Current trend in processor design is
a. NMOS
b. PMOS
c. CMOS
d. BJT
8 MIPS stands for
a. Multi Input Processing System
b. Million Instructions Per Second
c. Memory Information Processing System
d. None of the above
9 Which data is program memory?
a. RAM
b. ROM
c. EPROM
d. All of the above
10 The interface of hardware and software is
a. Operating system
b. Input System
c. Output System
d. All of the above

11  A source program is usually in

a. Assembly language
b. Machine level language
c. High-level language
d. Natural language
12 Pipelining is a
a. Serial Process
b. Parallel Process
c. Both
d. All of the above
13 The instruction used to cause unconditional jump is ________
a. UJG
b. JG
 c. JMP
d. GOTO
14  Add #45, when this instruction is executed the following happen/s _______
a. The processor raises an error and requests for one more operand
b. The value stored in memory location 45 is retrieved and one more operand is requested
c. The value 45 gets added to the value on the stack and is pushed onto the stack
d. None of the mentioned
15 The condition flag Z is set to 1 to indicate
a. The operation has resulted in an error
b. The operation requires an interrupt call
c. The result is zero
d. There is no empty register available
16 The two phases of executing an instruction are
a. Instruction decoding and storage
b. Instruction fetch and instruction execution
c. Instruction execution and storage
d. Instruction fetch and Instruction processing
17 The addressing mode, where you directly specify the operand value is
a. Immediate
b. Direct
c. Definite
d. Relative
18 The bus used to connect the monitor to the CPU
a. PCI bus
b. SCSI bus
c. Memory bus
d. Ram bus
19 The main advantage of multiple bus organisation over a single bus is
a. Reduction in the number of cycles for execution
b. Increase in size of the registers
c. Better Connectivity
d. All of the above
20 The time delay between two successive initiations of memory operation
a. Memory access time
b. Memory search time
c. Memory cycle time
 d. Instruction delay
21 The decoded instruction is stored in ___
a. IR
b. PC
c. Registers
d. MDR
22 Find the flip flop used to store data in registers.
a. D flip flop
b. JK flip flop
c. RS flip flop
d. All of the above
23 A processor performing fetch or decoding of different instruction during the execution of another
instruction is called
a. Super-scaling
b. Pipe-lining
c. Parallel Computation
d. All of the above
24 The clock rate of the processor can be improved by ______
a. Improving the IC technology of the logic circuits
b. Reducing the amount of processing done in one step
c. By using the over clocking method
d. All of the mentioned
25 CISC stands for
a. Complete Instruction Sequential Compilation
b. Computer Integrated Sequential Compiler
c. Complex Instruction Set Computer
d. Complex Instruction Sequential Compilation
26 To indicate negative sign which symbol is used
a) 0
b) 1
c) 00
d) 11
27 To indicate positive sign which symbol is used
a) 0
b) 1
c) 00
 d) 11
28 Uniprocessor system used for
a. Small systems
b. Low cost systems
c. Small size systems
d. All of the above
29 Nature of multi-processor system is
a. Shared and individual memory
b. Common bus connectivity
c. Common I/O devices
d. All of the above
30 A computer system should be
a. Small in size
b. Low power required
c. High speed
d. All of the above

UNIT II
ARITHMETIC
Fixed point Addition, Subtraction, Multiplication and Division. Floating Point
arithmetic, High performance arithmetic, Subword parallelism.

1 Find the instruction used for addition with carry

a. ADD
b. ADC
c. SUB
d. SBB
2 In computer how subtraction carried out
a. Addition
b. Subtraction
c. Complement addition
d. Complement subtraction
3 Which instruction used for subtraction with borrow
a. ADD
b. ADC
 c. SUB
d. SBB
4 Which method/s of representation of numbers occupies a large amount of memory than others?
a. Sign-magnitude
b. 1’s complement
c. 2’s complement
d. 1’s & 2’s compliment
5 When we perform subtraction on -7 and 1 the answer in 2’s complement form is __
a. 1010
b. 1110
c. 0110
d. 1000
6 When we perform subtraction on -7 and -5 the answer in 2’s complement form is
a. 11110
b. 1110
c. 1010
d. 0010
7 The processor keeps track of the results of its operations using flags called as
a. Conditional code flags
b. Test output flags
c. Type flags
d. Zero flag
8 The register used to store the flags is called as
a. Flag register
b. Status register
c. Test register
d. Log register
9 The most efficient method followed by computers to multiply two unsigned numbers is
a. Booth algorithm
b. Bit pair recording of multipliers
c. Restoring algorithm
d. Non restoring algorithm
10  For the addition of large integers, most of the systems make use of ______
a. Fast adders
b. Full adders
c. Carry look-ahead adders
 d. Half adder
11 When 1101 is used to divide 100010010 the remainder is ______
a. 101
b. 11
c. 0
d. 1
12  In the implementation of a Multiplier circuit in the system we make use of
a. Counter
b. Flip flop
c. Shift register
d. Push down stack
13 Multiplication is the process of
a. Repetitive addition
b. Repetitive subtraction
c. Complement addition
d. All of the above
14 Division is the process of
a. Repetitive addition
b. Repetitive subtraction
c. Complement addition
d. All of the above
15 Find the Equation for division is
a. Dividend = Quotient X Divisor + Remainder
b. Dividend = Quotient X Divisor - Remainder
c. Dividend = Quotient + Divisor X Remainder
d. Dividend = Quotient - Divisor X Remainder
16 For two n bit multiplication output size is
a. n bit
b. 2n bit
c. n+1 bit
d. 2n+1 bit
17 The functional unit which performs arithmetic operation is
a. Bus
b. ALU
c. IO Device
d. Memory
18 What are the terms used in multiplication process?
a. Multiplicand
b. Multiplier
c. Product
d. All the above

19 Terms used in division process is

a. Dividend
b. Quotient
c. Divisor
d. Remainder
e. All the above
20 Find the logical symbol equivalent to addition
a. AND
b. OR
c. NOT
d. EXOR
21 Identify the ogical symbol equivalent to multiplication
a. AND
b. OR
c. NOT
d. EXOR
22 For 16 bit microprocessor if A=FFFFH then accumulator value after one bit increment
a. FFFF
b. FFFE
c. 0000
d. 0001
23 Number system preferred for fractional value computation is ____
a. Fixed point system
b. Floating point system
c. Decimal system
d. Binary system
24 What are the components of floating point number
a. Whole number
b. Fractional number
c. Decimal point
 d. All of the above

25 Data type used in fixed point system

a. Whole number
b. Fractional number
c. Binary
d. Hexa Decimal
26 Which one is used for higher end computation systems
a. Fixed point system
b. Floating point system
c. Decimal System
d. All of the above
27 Reason for using parallelism
a. Increase execution speed
b. Improve efficiency
c. Efficient utilization
d. All of the above
28 Step(s) involved in execution of a instruction is
a. Fetching
b. Decoding
c. Executing
d. Storing
e. All the above
29 The instruction which makes addition of value one with register value
a. Add
b. Sub
c. Inc
d. Dec
30 The instruction which makes subtraction of value one from register value
a. Add
b. Sub
c. Inc
d. Dec
 UNIT III
THE PROCESSOR
Introduction, Logic Design Conventions, Building a Datapath - A Simple Implementation
scheme - An Overview of Pipelining - Pipelined Datapath and Control. Data Hazards:
Forwarding versus Stalling, Control Hazards, Exceptions, Parallelism via Instructions.

1. Any data or instruction entered into the memory of a computer is considered as

a) Storage
b) Output
c) Input
d) Information
2. Time during which a job is processed by the computer is:
a) Execution Time
b) Delay Time
c) Real Time
d) Waiting Time
3. A control character is sent at the beginning as well as at the end of each block in the
synchronous-transmission in order to
a) Synchronize the clock of transmitter and
b) Supply information needed to separate the incoming bits into individual character.
c) Detect the error in transmission and received
d) Both (A) and (C).
4. Which activity does not take place during execution cycle?
a) ALU performs the arithmetic & logical
b) Effective address is
c) Next instruction is
d) Branch address is calculated & Branching conditions are checked.
5. Negative numbers cannot be represented in
a) Signed magnitude form
b) 1’s complement form
c) 2’s complement form
d) 8-4-2-1 code
6. Where the result of an arithmetic and logical operation are stored?
a) In Accumulator
b) In Cache Memory
c) In ROM
d) In Instruction Registry  
7. Memory interleaving technique is used to address the memory modules in order to have
a) higher average utilization
b) faster access to a of data
c) reduced complexity in mapping hardware
d) Both (1) & (2)
8. The decoded instruction is stored in
a) IR
b) PC
c) Registers
d) MDR
9. Which registers can interact with the secondary storage?
a) MAR
b) PC
c) IR
d) R0
10. During the execution of a program which gets initialized first?
a) MDR
b) IR
c) PC
d) MAR
11. Which of the register/s of the processor is/are connected to Memory Bus ?
a) PC
b) MAR
c) IR
d) Both PC and MAR
12. ISP stands for _________
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
 d) Interrupt Service Procedure
13. Pipeline overhead arises from combination of pipeline register delay and
a) Hit rate
b) Clock cycle
c) Clock rate
d) Clock Skew
14. In pipelined instruction time between instructions, assuming ideal conditions, is equal to
a) Time between instructions pipelined= time between instruction / no of piped stages
b) Time between instructions pipelined= no of piped stages
c) Time between instructions pipelined= time between instruction
d) Time between instructions pipelined= time between instruction × no of piped stages
15. The registers, ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
16. PC Program Counter is also called as
a) instruction pointer
b) memory pointer
c) data counter
d) file pointer
17. Data hazards occur when________
a) Greater performance loss
b) Pipeline changes the order of read/write access to operands
c) Some functional unit is not fully pipelined
d) Machine size is limited
18. Predicting branches at runtime by using run-time information, is known as
a) Static branch prediction
b) Dynamic branch prediction
c) Branch prediction
d) Stall prediction
19. The instruction in different stages of the pipeline do not interfere with one another, the
separation is done by
a) Pipe stage
 b) Pipeline stacks
c) Pipeline registers
d) Processor cycle
20. How is a privilege exception dealt with?
a) The program is halted and the system switches into supervisor mode and restarts the
program execution
b) The Program is stopped and removed from the queue
c) The system switches the mode and starts the execution of a new process
d) The system switches mode and runs the debugger
21. The time required between moving an instruction one step down the pipeline is a
a) Clock cycle
b) Hit rate
c) Cycle rate
d) Processor cycle
22. Any condition that causes a processor to stall is called as
a) Hazard
b) Page fault
c) System error
d) Deadlock
23. The stalling of the processor due to the unavailability of the instructions is called as
a) Control hazard
b) Structural hazard
c) Input hazard
d) Output hazard
24. When multiple-instructions are overlapped during execution of the program, then function
performed is called.
a) Multitasking
b) Multiprogramming
c) Hardwired Control
d) Pipelining
25. Pipeline stalling concept is often given the name of
a) Load-use
b) Data Hazards
c) Bubble
 d) Multicycle datapath
26. The instruction being read from memory using the address placed in the PC and then is
placed in the IF/ID pipeline register in.
a) Instruction Fetch stage
b) Instruction decode stage
c) Execution
d) Memory Stage
27. Delay in finding the proper instruction to fetch is known as control hazard, also referred to
as
a) Structural Hazard
b) Data Hazard
c) Branch Hazard
d) Call Hazard
28. The eliminating stage of WAR and WAW hazards, is often called
a) Execution
b) Anti-dependence
c) Data hazards
d) Dispatch
29. Exceptions that are caused by some hardware event that is not under the control of the user
program, referred as
a) Asynchronous
b) Synchronous
c) Pipelined
d) Coerced
30. Pipelining that allows to achieve higher clock rates by decomposing the five-stage integer
pipeline into eight stages, is referred as
a) Bubbling
b) Stalling
c) Super pipelining
d) Deeper pipelining
 UNIT IV
MEMORY AND I/O ORGANIZATION

Memory hierarchy, Memory Chip Organization, Cache memory, Virtual memory.

Parallel Bus Architectures, Internal Communication Methodologies, Serial Bus Architectures,
Mass storage, Input and Output Devices.

1. The memory which is used to store the copy of data or instructions stored in larger
memories, inside the CPU is called
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
2. The next level of memory hierarchy after the L2 cache is
a) Secondary storage
b) TLB
c) Main memory
d) Register

3. Why we need to have secondary storage?

a) Store large volume of data that exceed the capacity of main memory
b)Perform arithmetic and logical operations
c) To give power to the system too
d)To help processor in processing

4. If a block can be placed at every location in the cache, this cache is said to be
a) Indirectly mapped
b) Directly mapped
c) Fully Associative
d) Partially Associative
5. The information when is written in the cache, both to the block in the cache and the block
present in the lower-level memory, refers to
a) Miss rate
b) Write-back
 c) Write-through
d) Dirty bit
6. The average time required to reach a storage location in memory and obtain its contents is
called the
a) Seek time
b) Turnaround time
c) Access time
d) Transfer time
7. In a memory-mapped I/O system, which of the following will not be there?
a) LDA
b) IN
c) ADD
d) OUT
8. Generally Dynamic RAM is used as main memory in a computer system as it
a) Consume less power
b) has higher speed
c) has lower cell density
d) needs refreshing circuitry
9. The policy for memory hierarchies: L1 data are never found in an L2 cache, refers to
a) Write buffer
b) Multilevel exclusion
c) Write-through
d) Multilevel inclusion
10. When the computer processor does not get a data item it requires in the cache, then the
problem is known as
a) Cache hit
b) Cache miss
c) File caches
d) Name cache
11. If each block having one place to be appear in the cache, this cache is said to be
a) Indirectly mapped
b) Directly mapped
c) Pages
d) Registers
12. Significant percentage of the spent time in moving data in two levels in the memory
hierarchy, then the memory-hierarchy is said to
a) Thrash
b) Mixed
c) Averaging
d) Write stall
13. Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data.
The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was
reduced to 125 nsecs and the number of cycles required for transfer stayed the same what
would the bandwidth of the bus?
a) 1 Megabyte/sec
b) 4 Megabytes/sec
c) 8 Megabytes/sec
d) 2 Megabytes/sec
14. A scheme in which portions of the I/O address space are given to I/O devices, is called
a) Data mapped
b) Memory-mapped I/O
c) Backplane
d) both a and b
15. Branch, MemWrite and MemRead are control lines set of
a) Instruction Fetch
b) Instruction decode
c) Memory Access
d) Execution
16. Forget to accounting the byte addressing or the cache block-size, in processing a cache is a
a) Pitfall
b) Fallacy
c) Fully associative
d) Set associative
17. ‘Aging registers’ are
a) Counters which indicate how long ago their associated pages have been referenced.
b) Registers which keep track of when the program was last accessed.
c) Counters to keep track of last accessed instruction.
d) Counters to keep track of the latest data structures referred.
18. Which cache write mechanism allows an updated memory location in the cache to remain
out of date in memory until the block containing the updated memory location is replaced in
the cache?
a) Write through
b) Write back
c) Read
d) Write
19. Which one of the following connects high-speed high-bandwidth device to memory
subsystem and CPU.
a) Expansion bus
b) PCI bus
c) SCSI bus
d) Serial bus
20. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitry
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
21. The sum of the contents of the base register and the sign-extended offset is used as a
memory address, the sum is known as
a) ALU instructions
b) Through put
c) Effective address
d) Load and store instructions
22. The best mode of connection between devices which need to send or receive large amounts
of data over a short distance is
a) BUS
b) Serial port
c) Parallel port
d) Isochronous port
23. The system is notified of a read or write operation by ___________
a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
 c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
24. To overcome the lag in the operating speeds of the I/O device and the processor we use
___________
a) Buffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
25. Process of reading data from permanent store and writing it to computers main store is
called
a) Saving the data
b) Loading the data
c) Writing the data
d) Reading the data
26. The process wherein the processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
27. The method which offers higher speeds of I/O transfers is ___________
a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
28. The serial communication is used for
a) short distance communication
b) long distance communication
c) short and long-distance communication
d) communication for a certain range of distance
29. The usual BUS structure used to connect the I/O devices is
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
30. Which of the following is major part of time taken when accessing data on the disk?
a) Settle time
b) Rotational latency
c) Seek time
d) Waiting time

UNIT V

ADVANCED COMPUTER ARCHITECTURE

Parallel processing architectures and challenges, Hardware multithreading, Multicore
and shared memory multiprocessors, Introduction to Graphics Processing Units, Clusters and
Warehouse scale computers - Introduction to Multiprocessor network topologies.

1. Execution of several activities at the same time is

a. Processing
b. Serial processing
c. Multitasking
d. Parallel processing
2. A computer system with at least two processors is called____________.
a. Uniprocessor
b. RAM
c. Multiprocessor
d. ROM
3. A set of computers connected over a LAN that functions as a single large
multiprocessor is called_______.
a. WAN
b. Cluster
c. Multitasking
d. Program
4. Execution time after improvement =
Executiontime affected by improvement
a. + Execution timeunaffected
Amount of improvement
 Creating
b. + Cache cohenrence
Parallelism
Executiontime unaffected
c. + Multithreading
Multiprocessor
Amount of improvement
d. ∗100
Executiontime affected by improvement
5. The memory per processor for strong scaling is approximately
P
a.
M
M
b.
P
M
c.
M
P
d.
P
6. Which allows multiple threads to share the functional units of a single processor in an
overlapping fashion?
a. Hardware
b. Software
c. Grid computing
d. Hardware multithreading
7. Main approach of hardware multithreading is
a. Fine-grained multithreading
b. Weak multithreading
c. Efficient multithreading
d. Weak multithreading
8. Hardware multithreading is having multiple threads contexts to span in same
processor and it is supported by
a. SMT
b. UPS
c. CPU
d. SISD
9. Executing several parts of a program in parallel by dividing the specific operations
within a single application into individual threads is
a. Multitasking
b. Multithreading
 c. Multiprocessing
d. Multicore
10. When the hardware executes from the hardware contexts determines the
a. Specialty of multithreading
b. Simplicity of multithreading
c. Difficult of multithreading
d. Granularity of multithreading
11. Multicore is usually the term used to describe
a. Two or more CPUs working together on the same chip
b. Two or more LAN working together on the same chip
c. Two or more CPUs working with different chip
d. Two or more LAN working with different chip
12. A distinct feature in multiprocessor systems is
a. Power balancing
b. Cache balancing
c. Load balancing
d. Error balancing
13. UMA stands for
a. Ultra multi access
b. Ultra memory access
c. Uniform multi access
d. Uniform memory access
14. When all the processors have equal access to all the peripheral devices, the system is
called as
a. Systematic multiprocessor
b. System multiprocessor
c. Symmetric multiprocessor
d. Simple processor
15. In COMA there is no longer a home address and the entire physical address space is
considered a huge
a. Multi cache
b. Single cache
c. Cache
d. No cache
16. GPU model could process
a) 10 million polygons per second
b) 10 instructions per second
c) 1 million polygons per second
d) 1000 instructions per minute
17. _________ allowed the CPU to improve graphics processing in 2D and 3D graphics.
a. Ohm’s Law
b. Cyber law
c. IoT law
d. Moore’s law
18. CPU-GPU combination is, one example of
a. Hetero-junction multiprocessing
b. Mono-geneous multiprocessing
c. Hetero-geneous multiprocessing
d. Double-junction multiprocessing
19. CPU supports
a. Serial execution of programs and less number of cores
b. Less number of cables
c. Special interfaces required
d. Special UPS required
20. GPU is developed by
a. Vvidia in 1999
b. Nvidia in 1999
c. VIndia in 1987
d. NIndia in 1987
21. A cluster is a collection of desktop computers or servers connected together by a
LAN to act as a
a. Small computer
b. Large computer
c. Single larger computer
d. Double larger computer
22. A simple metric to evaluate the efficiency of a datacenter or a WSC is called
a. Power utilization effectiveness
b. Power ultra-effort
 c. Poor ultra-effort
d. Poor utilization effectiveness
23. Height of the server is measured by
a. CPU units
b. Rack units
c. Memory units
d. RAM units
24. Warehouse-scale computers form the foundation of
a. Internet services
b. Amount of money
c. Energy efficiency
d. Indexing
25. Request-level parallelism is a way of representing tasks which are set of requests
which are to be to run in
a. Serial
b. Serial-Parallel
c. Parallel
d. Parallel-serial
26. The first improvement over a bus is a network that connects a sequence of nodes
together, and the topology is called as
a. Hybrid
b. Ring
c. Star
d. Mesh
27. For fully connected networks, the total network bandwidth is calculated by
P ×( P−1)
a.
2
P ×( P−1)
b.
4
P ×( P−1)
c.
6
P ×( P−1)
d.
8
28. An Omega network uses less hardware than the
a. LAN
 b. WAN
c. Crossbar network
d. Distance Network
29. A network that supplies a small switch at each node is
a. Single stage network
b. Multistage network
c. Bisection bandwidth
d. Total network bandwidth
30. A network that allows any node to communicate with any other node in one pass
through the network is
a. Distance Network
b. Single stage network
c. Multistage network
d. Crossbar network
Answers for Multiple Choice Questions
 Unit - I Unit - II Unit - III Unit - IV Unit - V
Q.N Answer Q.No Answer Q.N Answers Q.No Answer Q.No Answers
o s s o s
1 b 1 a 1 c 1 a 1 d
2 c 2 c 2 a 2 d 2 c
3 c 3 d 3 b 3 a 3 b
4 a 4 a 4 d 4 c 4 a
5 d 5 d 5 c 5 c 5 b
6 c 6 b 6 a 6 c 6 d
7 c 7 a 7 c 7 a 7 a
8 b 8 a 8 a 8 b 8 c
9 a 9 b 9 a 9 b 9 b
10 a 10 c 10 c 10 b 10 d
11 c 11 d 11 b 11 b 11 a
12 b 12 c 12 a 12 a 12 c
13 c 13 a 13 d 13 d 13 d
14 a 14 b 14 a 14 b 14 c
15 c 15 a 15 d 15 c 15 b
16 b 16 b 16 a 16 a 16 a
17 a 17 b 17 b 17 a 17 d
18 b 18 d 18 b 18 b 18 c
19 a 19 e 19 c 19 a 19 a
20 c 20 b 20 a 20 d 20 b
21 a 21 a 21 d 21 c 21 c
22 a 22 c 22 a 22 c 22 a
23 b 23 b 23 a 23 d 23 b
24 d 24 d 24 d 24 b 24 a
25 c 25 a 25 c 25 b 25 c
26 b 26 b 26 a 26 a 26 b
27 a 27 d 27 c 27 d 27 a
28 d 28 e 28 d 28 b 28 c
29 d 29 c 29 d 29 c 29 b
30 d 30 d 30 c 30 c 30 d