ANALYSIS OF INSTRUMENTATION AMPLIFIER USING

POLY SILICON THIN FILM TRANSISTOR

A PROJECT REPORT PHASE-I

Submitted by

ASHLEY ANN ALEX 312320106023

JANANI P 312320106057

in partial fulfillment for the award of the degree

of

BACHELOR OF ENGINEERING
in

ELECTRONICS AND COMMUNICATION ENGINEERING

St. JOSEPH’S COLLEGE OF ENGINEERING

Chennai-600119
JULY 2023
 St. Joseph’s College of Engineering
Chennai-600 119

BONAFIDE CERTIFICATE

Certified that this project report “ANALYSIS OF INSTRUMENTATION

AMPLIFIER USING POLY SILICON THIN FILM TRANSISTOR” is the
bonafide work of “ASHLEY ANN ALEX (312320106023) and JANANI P
(312320106057)” who carried out the project work under my supervision.

SIGNATURE SIGNATURE
DR.B. VICTORIA JANCEE, M.E., PhD DR.P. LATHA, M.E.,Ph.D
HEAD OF THE DEPARTMENT SUPERVISOR
ASSOCIATE PROFESSOR, ASSISTANT PROFESSOR,
DEPARTMENT OF ECE DEPARTMENT OF ECE
St. JOSEPH’S COLLEGE OF ENGINEERING St. JOSEPH’S COLLEGE OF ENGINEERING
OLD MAMALLAPURAM ROAD, OLD MAMALLAPURAM ROAD,
CHENNAI - 600 119. CHENNAI - 600 119.
 TABLE OF CONTENTS

CHAPTER TITLE PAGE NO

ABSTRACT II

LIST OF FIGURES III

LIST OF ABBREVIATION IV

1 INTRODUCTION 3

2 LITERATURE REVIEW 5

2.1 THIN FILM TRANSISTOR (TFT) 5

2.2 STRUCTURE OF THIN FILM TRANSISTORS 8

2.3 OPERATIONAL AMPLIFIER (OP-AMP) 12

2.4 UNDERSTANDING FROM THE JOURNALS 14

2.5 OBJECTIVES OF THE RESEARCH 18

3 REFERENCES 20
 ABSTRACT

An instrumentation amplifier is an integrated circuit used to amplify very low-

level signals, rejecting noise and interference signals. Since, it increases the disparity

among two inputs; it comes under the family of the differential amplifier. In general,

the instrumentation amplifier is using three op-amp circuits. Over several decades, Thin

Film Transistors have undergone a lot of development, evolution and refinement in the

field of electronics, since its conception. TFTs are being used as switching systems, flat

panel display, sensors, solar cells etc,. In this project the design of Hybrid Operational

Amplifier, using Poly Silicon TFT with MOSFET, was explained and designed by the

researcher, is used in our proposed instrumentation amplifier. We have used HSpice

circuit simulator to verify the proposed instrumentation amplifier using poly Si thin

film transistor.

The main function of this amplifier is to diminish surplus noise that is chosen by

the circuit. The capacity to refuse noise is familiar to every IC pins which are known

as the CMRR (common-mode rejection ratio). The instrumentation amplifier IC is an

essential component in the designing of the circuit due to its characteristics like high

CMRR, open-loop gain is high, low drift as well as low DC offset, etc.
 LIST OF FIGURES

FIGURE NO. NAME PAGE NO.

FIGURE 1.1 FET’s Classification 4

FIGURE 2.1 Poly-Si TFT Structure with 5

Different Layers

FIGURE 2.2 Bottom Gate Structure of an 13

A-Si:H TFT

FIGURE 2.3 Structure of Organic P- 15

channel TFT using
Pentacene

FIGURE 2.4 Structure of ZIO TFT 15

 LIST OF ABBREVIATIONS

TFT Thin Film Transistor

MOSFET Metal Oxide Semiconductor Field Effect Transistor

IC Integrated Circuit
DC Direct Current

AC Alternating Current
CMRR Common Mode Rejection Ratio
FET Field Effect Transistor
IGFET Insulated Gated Field Effect Transistor
JFET Junction Field Effect Transistor
OTFT Organic Thin Film Transistor

RFID Radio Frequency Identification

RAM Random Access Memory
PECVD Plasma-Enhanced Chemical Vapor Deposition
LCD Liquid Crystal Display
SOI-MOSFET Silicon-on-insulator Metal Oxide Semiconductor Field
Effect Transistor
CMOS Complementary Metal-oxide Semiconductor
UGF Unity Gain Frequency
 CHAPTER 1

INTRODUCTION

Since John Bardeen, William Shockley, and Walter Brattain discovered the world’s
first transistor in 1947, In-organic Field-Effect Transistors (FETs) have dominated the
mainstream microelectronics industry. The FETs are the fundamental building blocks
for both basic analytical circuits and the basic elements for digital combinational logic
circuits, and sequential logic circuits. Field Effect Transistor (FET) is an electronic
device of the most important type of semiconductor device used to control the flow of
electricity. FET operates as a capacitor with one plate which serves as a conducting
channel between two ohmic contacts, called as source and drain. The other plate called
as gate which controls the charge induced into the channel. The channel defines the
current path in the semiconductor. A gate voltage induced an electric field which
controls the channel to block or allow the flow of carriers from the source to the drain.
The carriers in the channel come from the source and move across the channel into the
drain. The FET acts like a resistor by which the resistance is controlled by the gate
voltage.

Figure 1.1 shows the classification of FETs which shows that FET can be
classified into two main groups of which one is Insulated Gate FET (IGFET) and
another one is Junction Field Effect Transistors (JFET). The JFET used a reverse biased
p-n junction to separate the gate from the channel. The conduction between the gate
and the channel has been prevented by an insulator, in an IGFET. The IGFETs can be
classified into two groups depending upon their fabrication. It can be formed from bulk
semiconductor such as silicon wafer or a thin layer of semiconductor which use silicon
di oxide for the gate insulator. These two groups form the foundation for the modern
electronic industry. If the IGFET is made from thin layer of semiconductor deposited
on a glass substrate that can be referred as Thin Film Transistors (TFTs). The most
familiar structure of an IGFET is Metal Oxide Semiconductor Field Effect Transistor
(MOSFET) and TFTs are the most important and commonly used semiconductor
devices in the modern electronic era. Among these two, Thin Film Transistor presently
demands more attention amongst the most common electronic devices.

Figure 1.1 FET’s Classification

4
 CHAPTER 2

LITERATURE REVIEW

2.1 THIN FILM TRANSISTOR (TFT)

The Thin Film Transistor is a three terminal device. The Field Effect
Transistor of Organic or In-Organic type requires a thin semiconducting layer that is
separated from a gate electrode by insulating gate dielectric, and source and drain
electrodes. It has channel width W separated by channel length L which are in contact
with semiconducting layer. The semiconducting layer is usually deposited using
evaporation, spin coating, or drop-casting, depending on the semiconductor. The gate
dielectric can be either Organic, In-organic or Hybrid Insulator. Most Organic
semiconductors are p-type, which means OTFT based circuits are like p-MOS devices.
In-organic semiconductors such as A-Si:H or Poly Silicon or mixed oxides are n-type
semiconductors which are readily available and familiar. Heineck et al (2009), reported
that enhancement and depletion mode devices can be developed using the same
material system using ZnO. This is the main advantage of In-organic semiconductors.
Additional advantages of many In-organic semiconductors are that they have high
carrier mobility and excellent stability Service (2006).

The structure and operating principles of Thin Film Transistors are similar to
those of the metal oxide field effect transistor (MOSFET), which is the most critical
device component in modern integrated circuits (ICs). The development histories of
TFTs and MOSFETs are similar. First functional TFT made from Hydrogenated
Amorphous Silicon (A-Si:H) with a silicon nitride gate dielectric layer was reported in
1979. Thin Film transistors (TFT) are gaining more interest in large area electronics
such as flexible displays, RFIDs, sensors, switching systems, solar cells, RAMs, low
5
cost computer logic, flat panel for image crystallization. Since their conception, TFTs
have undergone extensive evolution, development and refinement. As their intended
use went from switching systems to low cost computer logic to flat panel display
addressing new materials, structures and fabrication techniques were introduced.

TFT development is emerged along with that of the modern MOSFET. In the
first report of A-Si:H TFTs fabricated by the PECVD process only the technology
enjoyed great success, although, early demonstrations of functional devices and
products were published. In the past decades, device physics, material properties, and
fabrication processes have been developed to a great advancement in TFT. The TFT
LCD market in worldwide has grown to hundreds of billion recently. The TFT
architecture application is mainly for pixel driving in large-area LCDs and has also
been used in modern technology such as medical X-ray imagers, mobiles, monitor and
consumer goods. Research and development activities have been aiming at improving
its performance in low voltage and low power applications like large-area panels and
driver circuitry. In many universities, researchers have helped in the understanding of
material properties responsible for the TFT performance, the underlying chemistry and
mechanics of the fabrication processes. Organic and Oxide TFTs have been studied and
developed as possible alternatives for Si-based TFTs for lowering production costs and
improving carrier mobility. Advances in TFT technology will probably be used by the
LCD industry. Once outstanding challenges are resolved in newly developed TFT
products in the areas of flexible electronics, integrated circuits, sensors, etc. may be
realized.

It draws more attention towards the application of different types of TFTs,

mainly A-Si, and Poly Si, to increase the need for an accurate and efficient way to
simulate the circuits used on these devices. The dynamic characteristics of TFTs are
that the behavior of TFTs are typically switched on for ten of microseconds and then
switched off for tens of milliseconds. Because of these dynamic characteristics, TFTs
act as a switch in most applications. Amorphous Silicon (A-Si), is most widely used
6
active layer material while Poly Si is increasingly pursued as a next generation TFT
technology.

Their advantages compared to crystalline MOSFETs are having low price and
high capability of large area integration. These advantages compensates for low speed
of A-Si TFT which is its main disadvantage. Although, Poly Si TFT have many more
of the same applications as A-Si TFT its main advantages are both displays/ switching
and driver circuitry can be fabricated on the same chip and preferred in applications
necessary for high speed. As their intended uses began from switching systems to low
cost computer logic to flat panel display, addressing new materials, structures and
fabrication techniques were introduced. A-Si TFT is the most widely used active layer
material while Poly Si is increasingly pursued as a next generation TFT technology.

Since TFTs are from IGFET family, TFT differs from a typical MOSFET as
it is composed of very thin layer deposited on an insulating substrate, whereas most
MOSFETs are formed from a semiconductor wafer.

Despite the similarities with the commonly used MOSFETs, A-Si:H, Poly-Si
TFTs present some important differences. By introducing some analytical models,
efforts have been taken to describe the physical characteristics and properties of
Organic thin film transistors (Horowitz and Delannoy 1991). Similar results were
reported recently (Horowitz 2004). Calvetti et al (2005) stated that there were a few
efforts reported about development of an appropriate model describing the OTFTs’
characteristics, due to incomplete knowledge of the nature of the carrier transport
mechanism in Organic semiconductors. However it is learnt that the electrical
characteristics of OTFT are mostly similar to those of A-Si:H TFT. Efforts has been
carried out to modify the existing models for A-Si:H TFT in order to represent the
characteristics of OTFT (Necliudov et al 2000). There is a critical issue with Organic
TFT that they tend to degrade in ambient conditions (Sebastian et al 2008). Due to low
7
mobility of the TFTs, high performance interface electronics require operational
amplifier as the key building block, which is a difficult task. Allee et al (2009), has
improved a circuit on A-Si:H. Tarn et al (2010) developed an Op-Amp, which has been
designed on A-Si:H, which has low gain.

Based on the above discussions, in this study it is aimed to introduce a Nano

electronic device TFT for designing an Operational Amplifier and its application in low
voltage and low power applications.

2.2 STRUCTURE OF THIN FILM TRANSISTORS

Poly Silicon Thin Film Transistors (Poly-Si TFT) have become the essential
device both in microelectronics and in low cost Integrated Circuits, due to its low
temperature process.

In particular, various research works have been carried out on low

temperature Poly-Si TFTs, because they can be used for integrating driving circuits and
pixel elements on a common substrate in flat panel displays. The reason behind is that
Poly-Si TFTs have much higher electron mobility and drive current compared with A-
Si TFTs reported by Brotherton et al (1993) and Sposili Im (1996). However, in the
early days of Poly-Si TFT technology, these advantages could not be fully realized,
because of Solid Phase Crystallization process being the only source of acquiring the
Poly-Si Films. Due to low-temperature processes that have to be used for glass
substrates, numerous defects in Poly-Si grains and at grain boundaries exist and they
degraded the device characteristics. In recent years, these issues were overcome by
using a variety of advanced crystallization processes that have been developed and
explained by Voutsas (2003), Brotherton et al (1993) and Sposili and Im (1996).
Fabrication of Poly-Si TFT is possible and can be utilized for various research work
and implementation.

8
 A leakage current (Ion, off current) present inconsistently in the device, is the
problem of Poly Si TFT and this current depends strongly on the bias and temperature
which has been generated from grain boundary defects near the drain. An abnormal
leakage current is the main deficiency of Poly Si TFT. Thus, it is very important to
investigate on leakage current of Poly Si TFT and its reduction. The main reason of the
abnormal leakage current is due to the field-assisted generation mechanism.

Figure 2.1Poly-Si TFT Structure with Different Layers

Figure 2.1 shows the structure of Poly Si TFT which is a kind of three
terminal device: its substrate is floating just like SOI MOSFET. The modeling of Poly
Si TFT is the effective medium of approach which treats the non-uniform poly silicon
sample with grain boundaries as some uniform effective medium with effective
material properties. When Poly Si TFT operates at saturation as well as in the off state
and weak inversion region, there exists float body effect, due to parasitic bipolar
transistor as well as the field assisted generation mechanism from trap state in Poly Si
TFT grain boundary near the region of drain. The increase of drain current in saturation
is caused by the floating body effect. This short channel devices show a significant
decrease of the sub-threshold idealistic factor with increasing drain voltage. By using

9
the model, the relations of leakage current between terminal voltages, temperature of
the TFT can be obtained.

Figure 2.2 Bottom Gate Structure of an A-Si:H TFT

Figure 2.2 shows the bottom gate structure of Amorphous Silicon Thin Film
Transistor (A-Si TFT), which is also a three terminal device. It comprises of an un-
doped hydrogenated A-Si layer interceding between gate and preservation dielectrics,
together with low-resistivity source and drain contacts. This results that the TFT has
two interfaces of hydrogenated A-Si. One of the hydrogenated A-Si interfaces which
is deposited closer to the gate terminal and before hydrogenated A-Si film, is called as
front interface. Another interface called back interface which is closer to the drain and
source terminals. N-channel mode operation is most commonly available to use.
Compared to the N-channel transistor, equivalent P-channel transistor is not available
to use due to least amount of mobility of holes in A-Si TFT, thereby a resulting in
reduction of drain current. Due to the high defect density of doped materials, it is
difficult to deplete the channel which limits the depletion mode devices.

The operation of A-Si TFT is quite different from that of crystalline

MOSFETs. In the sub-threshold region the drain current is a poor function of the gate
voltage dictated by large trap density in the material as in crystalline MOSFETs. Above
10
threshold, most of the induced charge in hydrogenated A-Si TFT goes into traps and
only a small fraction enters the conduction band. This fraction increases as the gate
voltage increases. The field effect mobility increases with the gate voltage.

Figure 2.3 Structure of Organic P-channel TFT using Pentacene

The simplest Organic TFT models are very similar to those for conventional
p-channel MOSFET. The field effect mobility might depend on the channel length and
transport properties are very sensitive to the properties of Organic semiconductor gate
di-electric interface. Figure 2.3 shows the structure of the Organic p-channel TFT
which uses Pentacene as the active layer. Aluminium acts as the gate metal and
Parylene as the gate dielectric. Finally, the devices are encapsulated using a Parylene
process. The saturation mobility is 0.08 with an on/off current ratio greater than 10 4.
Recently, ZnO (and its derivatives) has attracted interest due to its high mobility and
electrical stability (Venugopal and Allee 2007; Shringarpure et al 2008) which is shown
in Figure 2.4.

11
 Figure 2.4 Structure of ZIO TFT

In this investigation, attempts are made to use Poly Si and A-Si TFTs use in
the design of Op-Amp, since available literatures of Organic TFTs are limited. This
research work concentrates on Poly-Si and A-Si TFTs which are used in the new Op-
Amp design.

2.3 OPERATIONAL AMPLIFIER (OP-AMP)

TFTs are having high immunity to noise, operates on low power voltage and
low static power consumption like MOSFET and CMOS. Significant power is drawn
only when TFT device is switching between on and off states and are not producing
much heat as MOSFETs. These TFT devices also allow a high density of logic
functions on a chip. As TFT possess, high carrier mobility, low voltage, low power
applications capabilities, effective ON state current, relatively to the applied voltage
and low inverse sub-threshold slope, it can be considered for design of high speed and
high performance electronic circuits. In order to evaluate the potential benefits of this
new technology, the assessment of performance for replacing MOSFETs by TFTs are
made at circuit level.

Low voltage and low power mixed signal circuits are becoming highly
important especially for portable electronics and wireless communication systems.
Nowadays, many analog design techniques and methodologies have been presented to

12
enable high performance analog signal processing at low supply voltages. One such
technique is the fully differential design technique that becomes widespread as it
reduces the problems associated with both reduced signals swings and noise coupling
(Philip et al 2007).

The direct-coupled amplifier is popularly known as an Operational

Amplifier (Op-Amp), which has high gain and high performance, and has feedback to
control its performance characteristics. It consists of several transistor amplifiers. Op-
Amps are the functional building blocks for many analog circuit designs which utilize
high gain, high input impedance, low output impedance and high bandwidth
characteristics of Op-Amp (Baschirotto et al 1997). Op-Amps are used for amplifying
the mixed signal input, controlling, generating non-sinusoidal or sinusoidal
waveforms over frequencies from DC to MHz. It can also utilize for computing
operations like addition, subtraction, multiplication, integration, differentiation.

The Op-Amp is a differential amplifier with high gain, which can be used as
differentiator, integrator, and summing amplifier. In many integrated analog and
mixed signal systems, Op-Amps are an essential part of it. While designing an Op-
Amp, the designers have to consider on gain bandwidth, slew rate, common mode
range and output swing offset. Since the negative feedback connection is the
mandatory design for Op-Amps, frequency compensation is necessary to be used to
achieve closed loop stability. It has been indicated by the researchers (Allen and
Holberg 2011, Razavi 2002, Johns et al 1997 and Ankit Sharma et al 2012) that
design of the input stage affects major performance measures such as DC gain, gain
bandwidth, and phase margin of an amplifier. Due to this reason the designer has
been given much importance on the optimal design of the input stage to maintain
these performance measures constant across the common-mode range. Though most
of the designer has designed towards keeping gain margin constant, but the overall
intention is to get a constant operation for all amplifier specifications. Almost many
designs use the same architecture of designing Op-Amp, whereas input stages have
13
the changes to obtain constant operation. A generally used architecture for low
voltage and low power amplifier design is a two stage amplifier. This architecture is
used because it improves its optimum performance to manipulate the input stage to
achieve the sequential and continuous operation that is desired in low voltage and low
power design.

2.4 UNDERSTANDING FROM THE JOURNALS

The first generation of CMOS op amps was limited to trans-conductance
amplifiers. They had modest performance and were able to drive only capacitive
loads. The second generation of these Op-Amps, in addition to high-performance
trans-conductance amplifiers, includes general-purpose Op-Amps. These Op-Amps
can drive resistive as well as capacitive loads with a level of performance which is
comparable to that of their bipolar counterparts, as reported by Monticelli (1986). For
these Op-Amps folded-cascade amplifiers are commonly used as the input stage. On
the other hand, for the output stage a variety of different circuits have been used,
Fisher and Koch (1987), Babanezhad and Gregorian (1987), and Castello (1984).

The important criteria for designing an output stage are as follows:

1) Low standby power dissipation which is controlled preferably by

supply-independent, current source;

2) Good current driving capability;

3) Large small-signal trans-conductance in order to provide some voltage

gain when driving heavy resistive loads and also to move the capacitive
load-dependent pole to higher frequencies; and

4) Simple circuit configuration so as to avoid additional parasitic poles.

Most of the output stages reported in the literature had limited driving
capability mainly because of the limited VGS of the output devices explained by Joseph

14
N. Babanezhad (1998).

Differential amplifiers with accurately balanced outputs can be easily realized

if the differential-mode circuitry and the common mode circuitry are treated equally in
the design process. A convenient way of accomplishing this is to use a topology that
combines the two parts as close as possible to the front end of the amplifier. In this way
most of the design issues such as gain, and compensation. are addressed at the same
time for both the differential and common-mode signal paths.

Operational amplifiers are used equally in both analog and digital circuits
(Holman et al 2007 and Maryam Borhani et al 2009). In order to achieve wide
common mode range, different techniques have been proposed to design Op-Amp
input differential pair with reduced supply voltage which includes the use of multi-
VT process (Bazarjani et al 1995), depletion devices (Griffith et al 1997) and the bulk
driving techniques (Blalock et al 1998). The multi-Vt process and depletion devices
technique require enhancement on a standard CMOS process that increases the
overall cost and operating the devices in the bulk driving technique may not be
accurately modeled by Spice. The CMOS Op-Amp is widely used as analog building
block for mixed signal circuits. Many Op-Amp designs are simple and robust,
providing good values for its functional parameters.

Amana (2012) had analyzed about the design and synthesis of two stage
CMOS Op-Amp and explained about the frequency compensation technique which is
necessary to avoid closed loop instability. The easiest method for compensation is to
connect a capacitor between input and output of the second stage. This method gives
high closed loop stability with lower bandwidth and results in splitting the poles.

When an Op-Amp needs to be operated at a high frequency, several

limitations have come into the forefront in the existing approaches. The Op-Amp
designed to work at a low voltage and low power, had been improved by Baruah (2010),

15
but it permitted a very low unity gain frequency.

Johns and Martin (1997), and Gregorian and Temes (1986), stated that the
design procedures were proposed for this Op-Amp which reduces the degree of
freedom in the design equations, therefore, preventing the possibility to meet optimized
performance

Ehsan Kargaran et al (2010, 2013), explained the simulation done in HSPICE

and show an operation at a low voltage and it consume very low power, but the increase
observed in the UGF which was not noteworthy to be considered.

Gonzalez et al (1997), have reported that, as the supply voltage decreases, it

became difficult to keep the transistors in saturation with the available voltage. The
effect of capacitive load on unity gain frequency, noise, speed and power balancing
were not considered, in these procedures.

Gupta (2010), has explained about a two stage and three stages CMOS Op-
Amp with fast settling, high DC gain and low power designed in 180nm technology
and reported that this method suffers from compressed gain bandwidth problem
because of very high gain of the first stage.

Mahattanakul and Chutichatuporn (2005), has discussed about the design

Procedure for Two-Stage CMOS Op-Amp with Flexible Noise-Power Balancing
Scheme. The design procedure that allowed the Cc a wide range and it would provide
a higher degree of freedom in the trade-off between noise and power consumption
which had been improved by Mahattanakul and Chutichatuporn (2005).

Mohammad Taherzadeh-Sani and Anas (2011); Anshu Gupta

et al (2010), proposed the multi-stage design that leads to the decrease of the phase
margin and UGF but it improves the gain and settling time.

16
 Palmisano et al (2001, 2000) explained about CMOS Op-Amp design
procedure which was operating on low power. This procedure had conditionally
allowed to use the limited range of compensation capacitor (condition for compensation
is, CC >> Cgs5). In this design, CC was the compensation capacitor greater than a
parasitic capacitor Cgs5 of MOSFET in the Op-Amp.

Palmisano and Palumbo (1995, 1997), explained about the compensation

strategy for two-stage CMOS Op-Amps design based on current buffer. And to achieve
stability in closed-loop conditions and clear of closed-loop wavering, two-stage CMOS
operational amplifiers adopt Miller compensation which is necessary in OP-AMP
design.

Pugliese et al (2008) have proposed a technique for Single Miller Feed

Forward Compensation and this technique improves stability and limits the bandwidth
reduction. A design procedure of multistage Op-Amp for settling time minimization
with low power and high accuracy level also proposed by Pugliese et al (2008).

Ramirez-Angulo (2007) explained and reported that the main challenges of

Op-Amp were a high DC gain and a high bandwidth with a high output swing
depending on the applications. To achieve a higher gain, multi-stage Op-Amp can be
used by cascading the stages. When the gain was increased the bandwidth had
considerably reduced, which is the drawback of the two stage Op-Amp.

Rosario et al (2003), have explained that it was difficult to compensate and

hard to stabilize for the two- stage Op-Amp, which is widely used in many applications.
Singh and Anu (2011), have introduced the Cascade compensation technique to
improve the stability in performance.

Vaibhav and Degang (2009), have improved the technique to limit to certain
range of the settling performance and the output swing. Zushu Yan et al (2011), have
analyzed about the Frequency compensation, which is essential for two-stage and
17
multi-stage Op-Amps.

The new Op-Amp design using TFT will provide good voltage gain, a good
common mode range and good output swing with low power dissipation. In this
research, an Op-Amp has been designed which exhibits high Unity Gain Frequency
(UGF) for optimized balancing of gain, speed, power, phase margin, and load.

The new method is to set a higher UGF of the Op-Amp working at a low
voltage supply. This permits the value of each circuit elements such as transistor aspect
ratios, bias current and compensation capacitor of the amplifier to be related to the
required electrical parameters and will provide good voltage gain, a good common
mode range and good output swing with low power dissipation.

2.5 OBJECTIVES OF THE RESEARCH

The general objective of this research is to design and analyze Op-Amp using
TFTs. It also aims to undertake a detailed performance analysis and a comparison
between TFT technology and bulk CMOS technology at circuit level for high
performance on low voltage, Low Power and Low Power Dissipation in operation.

After designing the Op-Amp using the Amorphous Silicon Thin Film
Transistor and Poly Silicon Thin Film Transistor, the same Op-Amps are used to design
integrator and differentiator and their performances have also been analyzed.

To achieve the above said objectives the following steps were carried out in
this research:

The specific objectives of this research work is to develop a new Op-Amp

using Thin Film Transistor to meet the requirements of low power consumption, low
input offset voltage, low die area etc. In this work, the transistor sizes and bias are
calculated first based on the DC gain specification. Then, the Miller capacitance is

18
predicted. After that, the trans-conductance of the first and second stages are adjusted
for better performance matching. Both the DC and AC performance of the Op-Amp are
synthesized and then evaluated considering device parasites into account. This process
was repeated until the performance of the Op-Amp meets the design specifications
within 5% variation. The success of this approach depends on the accurate predictions
of the Miller capacitance and the transistor trans-conductance.

19
 REFERENCE

[1] Amana Yadav, (2012), “A Review Paper on Design and Synthesis of Two stage
CMOS Op-Amp”, International Journal of Advances in Engineering &
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[2] Amana Yadav, (2012), “Design of Two-Stage CMOS Op-Amp and Analyze the
Effect of Scaling”, International Journal of Engineering Research and
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[3] Baruah, R. Kr., (2010), “Design of a Low Power Low Voltage CMOS Op-Amp”,
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High Swing Ultra- Low-Power Two Stage CMOS OP-AMP in 0.18 μm
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[7] Gupta, A., (2010), “A Two Stage And Three Stages CMOS OP-AMP With Fast
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[8] Mahattanakul, J., Chutichatuporn, J., (2005), “Design Procedure for Two-Stage
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