INTEGRATION, the VLSI journal 91 (2023) 60–66

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Integration
journal homepage: www.elsevier.com/locate/vlsi

A CMOS transimpedance amplifier with broad-band and high gain based on

negative Miller capacitance
Jiahong Zhang *, Zhuo Wang, Chao Ma
Faculty of Information and Automation, Kunming University of Science and Technology, China

A R T I C L E I N F O A B S T R A C T

Keywords: A CMOS transimpedance amplifier (TIA) with broad band and high gain based on negative Miller capacitance
Transimpedance amplifier (TIA) and capacitive degeneration has been proposed and designed. The theoretical analysis shows that by introducing
Feedforward common-gate (FCG) negative Miller capacitance into the feedforward common gate (FCG) amplifier circuit, the bandwidth limitation
Capacitive degeneration
caused by the internal parasitic capacitance can be reduced, and by cascading the capacitive degeneration-based
Negative miller capacitance
Transimpedance gain
common source (CS) amplifier as the gain stage, the amplifier gain can be improved simultaneously. The pro­
Broad-band posed TIA is designed and simulated in TSMC 65 nm CMOS process, The simulation results show that the − 3 dB
bandwidth of the amplifier circuit is 23.7 GHz, the transimpedance gain is 60.1 dBΩ, the average equivalent
input noise current spectral density is less than 40.7 pA/√Hz, the power consumption is 4.8 mW, and the circuit
layout area is 0.0027 mm2. In Comparison to the published TIA circuits, the bandwidth of the designed CMOS
TIA is increased by 12.7 GHz, the gain is increased by 18.1 dBΩ and the circuit layout area becomes smaller. All
the results demonstrate that the designed TIA can be used in the photoelectric detection circuit with broader
bandwidth and higher gain.

1. Introduction
As the first stage of the optical communication receiver, the tran­
simpedance amplifier (TIA) is used for converting and amplifying the
faint photocurrent detected by the photodiode (PD) to form voltage
signal that can be processed in the next digital signal processing (DSP)
unit. Therefore, a TIA with high transimpedance gain, low noise and
bandwidth is required to ensure the optical communication receiver
with lower bit error rate (BER) and high-speed. The basic TIA is usually
based on the common source (CS) amplifier combined with a shunt-
feedback circuit [1,2]. Based on CS amplifier circuits, the inverter
(Inv) amplifier composed of the N-MOSFETs, the P-MOSFETs and the
shunt-feedback has lower noise and higher gain due to the large trans­
conductance [3,4]. For the above CS based TIA and Inv based TIA, the
pole located at the input node is the main factor limiting the bandwidth.
This is because a photodiode (PD) is connected to the front end of the
TIA, and then the parasitic capacitance of the PD will be coupled with
the input impedance to form a pole at input node, which results in the
bandwidth of the TIA is limited by the pole. Therefore, a small input
resistance is required for the TIA circuit to reduce the bandwidth limi­
tation of the input pole. The common gate (CG) amplifier has become
one of the basic circuits of the TIA because of its smaller input resistance
[5]. Regulated Cascode (RGC) circuit has smaller input impedance by
adding a CS amplifier stage as the regulation circuit on the basis of
CG-TIA, which is therefore widely used as the input stage in the tran­
simpedance amplifier circuit [6–8]. However, RGC circuit has higher
power consumption and problems of gain and bandwidth falling due to
the insufficient of voltage headroom. In 2004, Christian Kromer et al. [9]
proposed the feedforward common gate (FCG) based TIA. By adding a
CG amplification stage into the regulation loop of the RGC, more voltage
headroom is released, and the circuit has a smaller input impedance,
which makes the FCG-TIA has wider bandwidth and higher gain than the
CG-TIA and RGC-TIA [10]. In addition, the RGC-TIA and FCG-TIA have
one and two more stages than the CG-TIA respectively, which results the
parasitic capacitors around the MOSFETs are coupled with the load
resistance in each stage and generating new poles, thus limiting the
bandwidth of the circuit.
Based on the above TIAs, researchers have proposed a variety of
techniques to improve the circuit performance. For example, shunt-
feedback technology is used in the CS amplifier circuit to increase
bandwidth by sacrificing gain [2], and current reuse technology is used
in the RGC-TIA circuit to release voltage headroom [7]. To reduce the

* Corresponding author.
E-mail addresses: zjh_mit@163.com (J. Zhang), 1220361228@qq.com (Z. Wang), 1450566025@qq.com (C. Ma).

https://doi.org/10.1016/j.vlsi.2023.03.004
Received 30 November 2022; Received in revised form 8 February 2023; Accepted 13 March 2023
Available online 17 March 2023
0167-9260/© 2023 Elsevier B.V. All rights reserved.
J. Zhang et al.
Fig. 1. Schematic of the FCG transimpedance amplifier.
bandwidth limitation caused by the poles, inductors or active inductors
are used to add zeros to compensate poles in the Inv-TIA, RGC-TIA and
FCG-TIA circuit. The inductive shunt peaking [9,11,12] is used to add
inductors at the load of each stage, while the inductive series peaking
[12–15] is used to add inductors between stages of the amplifier circuit.
But as the use of planar spiral inductors, the area of the CMOS circuit
layout is larger. The active inductor structure composed of field effect
tubes and resistors has inductance characteristics, which can replace the
load resistors in all stages of amplifier circuit, provide gain for amplifier
circuit while introducing zero point, and has smaller layout area
compared with the planar spiral inductor structure. Therefore, the active
inductive peaking technology is widely used in the design of TIA [16,
17]. But the active inductive peaking technology requires sufficient
voltage margin to meet the design requirements of bandwidth and gain
at the same time, which requires the tradeoff of power consumption,
bandwidth and gain in the circuit design. In addition, the capacitive
peaking [18], the capacitive degeneration [19,20], and negative Miller
capacitance [21] have also be used to expand bandwidth, and the
integration of capacitors is easier and the layout area is smaller than that
of inductors. Capacitive peaking is formed by adding capacitance into
the negative feedback loop, and the Q value of the circuit is controlled by
changing the capacitance so as to expand the bandwidth. The capacitive
degeneration is formed by using a capacitor and a resistor shunt to the
source of the transistor, so that the bandwidth of the circuit can be
expanded by introducing a zero to offset the bandwidth limitation
caused by the pole. However, as the capacitive peaking and degenera­
tion are commonly used in feedback loops and gain stage, for the circuit
has multiple stages, due to the bandwidth limitation caused by multiple
poles, the bandwidth expansion by using the capacitive peaking and
degeneration is not as good as that of the passive or active inductive
peaking. The negative Miller capacitance is obtain by using a capacitor
shunt with the amplifier circuit. The negative Miller capacitance is used
to reduce the bandwidth limitation caused by the input capacitance. But
simultaneously as a equivalent positive Miller capacitance is formed at
the output, the bandwidth is limited by the decrease of the pole
frequency.
Therefore, in this paper, an improved TIA has been proposed and
designed. The FCG amplifier is used as the input stage, the capacitive
degeneration-based CS amplifier is used as the gain stage and the
negative Miller capacitor is connected inside the circuit. The voltage
difference between the stages of the circuit forms two Miller amplifiers,
thus the capacitance connected between each amplification stage can be
equivalent to the negative Miller capacitance. As a result, the internal
parasitic capacitances can be reduced by the negative Miller capaci­
tances, which further reducing the internal poles and extending the
bandwidth of the circuit. Moreover, by cascading the capacitive
degeneration-based CS amplifier as the gain stage the gain of the circuit
61
Integration 91 (2023) 60–66
Fig. 2. Schematic diagram of the Miller effect of capacitance.
is improved, and a zero is introduced to compensate the bandwidth drop
due to pole frequency reduction caused by positive Miller capacitances.
As a result both the gain and bandwidth are increased simultaneously.
Based on the TSMC 65 nm CMOS process, the simulation analysis and
layout design of the proposed TIA are carried out by using the Cadence
software.
2. The basic circuit
2.1. FCG transimpedance amplifier
Fig. 1 shows the schematic of the basic FCG-TIA, where the signal is
input to the source of M1 and M2 by the IN node. The signal is amplified
sequentially through a CG amplifier stage composed of M2 and R2, and a
CS amplifier stage composed of M3 and R3. The amplified signal forms a
large voltage difference with the input signal from the source pole of M1.
Therefore, sufficient drain current can be generated in M1 even when the
source potential is low. The drain current generated in M1 is converted
into voltage through resistor R1, which results in the transimpedance
gain Z1(0) ≈ R1. M4 is regarded as the current source and provides the
bias current for M1 and M2. The input impedance of the FCG-TIA at low
frequency can be expressed as
Vin 1 1
Z1IN (0) = ≈ ( )≈ (1)
Iin gm1 1 − VX VY gm1 (1 + gm2 R2 gm3 R3 )
Vin VX
where the gmx (x = 1, 2, 3) is the transconductance, VX is the voltage at
the X node, and VY is the voltage at the Y node.
According to (1), the input impedance of FCG-TIA is inversely pro­
portional to the transconductance of M1, M2, and M3, as well as the load
resistance R2 and R3. Therefore, to reduce the bandwidth limitation
caused by the parasitic capacitance of the PD, the input impedance can
be reduced by increasing the ratio W/L of the transistor to increase the
transconductance or increasing the values of R2 and R3. However, the
parasitic capacitance around nodes X and Y will be increased with the
increasing of W/L ratio and is coupled with the load resistor R2 and R3,
which results the pole frequency is decreased and the bandwidth is
reduced. Therefore, based on the FCG amplifier circuit, the negative
Miller capacitance is proposed to reduce the parasitic capacitance
around nodes X and Y in this paper.
2.2. Negative miller capacitance
Fig. 2 shows the schematic diagram of the Miller effect of capaci­
tance. According to the Miller effect, for A>1, the equivalent negative
Miller capacitance C1 = C (1-A) and positive Miller capacitance C2 = C
(1-1/A) (where C is the feedback capacitance, and A is the gain of the
amplifier). Therefore, the corresponding parasitic capacitance in the
circuit can be reduced by using the negative Miller capacitor.
2.3. Capacitive degeneration
As shown in Fig. 3, the degeneration resistor RS and degeneration
capacitor CS are shunted to the source of the CS amplifier circuit to form
a capacitive degeneration structure. RD is the gain resistor, Cgb5, Cgd5,
Cgs5, Cds5, Csb5, and Cdb5 represent the parasitic capacitance between the
J. Zhang et al. Integration 91 (2023) 60–66

Fig. 3. CS amplifier circuit based on capacitive degeneration (a) schematic and (b) small signal circuit mode.

3. The proposed TIA

According to the above analysis that the negative Miller capacitance

can reduce the parasitic capacitance while the capacitive degeneration
can introduce zero, an improved TIA has been proposed and designed.
The schematic circuit is shown in Fig. 4.
The FCG circuit is used as the input stage, the capacitive
degeneration-based CS amplifier is used as the gain stage, and on this
basis, and between the X-Z, Y–O nodes the capacitors CXZ, CYO are
introduced respectively. According to the Miller effect, CXZ can be
equivalent to the negative Miller capacitance CX connected to node X
and the positive capacitance CZ connected to node Z, and CYO can be
equivalent to the negative Miller capacitance CY connected to node Y
and the positive capacitance CO connected to the output node O. Each
equivalent capacitance can be written as
⎧ ( ) ( )
⎪
⎪ VX 1
⎪ CZ = CXZ 1 −
⎪ = CXZ 1 − >0
⎪
⎪ VZ AX− Z
⎪
⎪
Fig. 4. Schematic circuit of the proposed transimpedance amplifier. ⎪
⎪ ( )
⎪
⎪ CX = CXZ 1 − VZ = CXZ (1 − AX− Z ) < 0
⎪
⎪
⎨ VX
gate-ground, gate-drain, gate-source, drain-source, source-ground, and (5)
( )
drain-ground of M5 respectively. According to the KCL and under small ⎪
⎪
⎪ VO
⎪ C = C 1 − = C (1 − A ) < 0
signal condition, the transfer function is given by ⎪ Y YO YO Y− O
⎪
⎪ VY
⎪
⎪
⎪
⎪ ( ) ( )
⎪
⎪ VY 1
⎪
⎩ CO = CYO 1 − = CYO 1 − >0
VO AY− O

( ( )
C
Vout − gm5 RD 1 + RS s CS + Csb5 − gmgs5
(2)
5 RS
ZS = ≈{ [ ( ) ]}[ ( )]
Vin 1 + RD s Cdb5 + 1 + gm51RD Cgd5 1 + gm5 RS + RS s CS + Csb5 −
Cgs5
gm5 RS

From (2), the zero frequency ƒz-S introduced by the capacitive where
degeneration and the low-frequency gain are
VZ R1 gm1
1 AX− Z = ≈ + R1 gm1 R3 gm3 > 1 (6)
fz− S ≈ (
Cgs5
) (3) VX gm2 R2
2πRS CS + Csb5 − gm5 RS
VO R1 RD gm1 R1 gm5 RD gm1
AY− O = ≈ + >1 (7)
− gm5 RD VY RS (1 + gm5 RS )gm2 R2 gm3 R3
ZS (0) ≈ (4)
1 + gm5 RS
And VZ is the voltage at the Z node, and VO is the voltage at the O node.
Therefore, from (3) to (4), the bandwidth limitation caused by the In addition, according to the KCL, for small signal, the input
dominant pole can be reduced by changing the value of CS to move the impedance of the circuit is given by
ƒz-S to the pole, while the amplifier gain can be improved by increasing
Vin 1
RD. Consequently, by cascading the capacitive degeneration-based CS ZIN (s) = ≈ [ ] ( ) (8)
amplifier as the gain stage, the gain and bandwidth of the TIA can be Iin gm1 1 − gm2 R2 gm3 R3
+ s Cpd + CMi
[1+R2 s(CM23 +CX )][1+R3 s(CM31 +CY )]
improved simultaneously.
The voltage gain

62
J. Zhang et al. Integration 91 (2023) 60–66

( VY VX )
gm1 R1 1 −
Vout Vin VY Vout
AV (s) = ≈
Vin [1 + R1 s(CM15 + CZ )] VZ
[ gm2 R2 gm3 R3 ] (9)
− gm1 R1 1 − [1 + RS s(CS + CMs5 )]gm5 RD
[1 + R2 s(CM23 + CX )][1 + R3 s(CM31 + CY )]
≈
[1 + R1 s(CM15 + CZ )][1 + RD s(CM5 + CO )][1 + RS s(CS + CMs5 ) + gm5 RS ]

From (8) and (9), the transfer function of the circuit is

Vout − gm1 R1 gm5 RD [1 + RS s(CS + CMs5 )]

Z(s) = = ZIN ⋅AV ≈ [ ]
Iin [ ( )] RS s(CS + CMs5 )
gm1 (1 + gm2 R2 gm3 R3 ) + s Cpd + CMi 1 +
gm5 RS + 1 (10)
{[1 + R2 s(CM23 + CX )][1 + R3 s(CM31 + CY )] + gm2 R2 gm3 R3 }
[1 + R1 s(CM15 + CZ )][1 + R3 s(CM31 + CY )][1 + R2 s(CM23 + CX )][1 + RD s(CM5 + CO )]

⎧
⎪
⎪ gm1 (1 + gm2 R2 gm3 R3 )
⎪
⎪ fp− IN ≈ ( )
Table 1 ⎪
⎪ 2π Cpd + CMi
⎪
⎪
Aspect ratios of the transistors.
⎪
⎪
⎪
⎪ 1
⎪
⎪ fp− ≈
M1 M2 M3 M4 M5 ⎪
⎪ X
2πR2 (CM23 + CX )
⎪
⎪
⎪
⎨
W/L 50 66.6 83.3 50 16.6 1
fp− Y ≈ (12)
⎪
⎪ 2πR3 (CM31 + CY )
⎪
⎪
⎪
⎪
⎪
⎪ 1
⎪
⎪ fp− Z ≈
⎪
⎪ 2πR1 (CM15 + CZ )
⎪
⎪
where Cpd is the parasitic capacitance of the PD, CMxy (x = 1, 2, 3 and y ⎪
⎪
⎪ 1
⎪
⎪
= 1, 2, 3) is the sum of the parasitic capacitances between the corre­ ⎩ fp− O ≈
2πRD (CM5 + CO )
sponding transistors, CMi is the sum of parasitic capacitances around the
input node, CM5 is the sum of parasitic capacitances around the drain of According to (12), because the input resistance 1/gm1(1 + gm2R2
M5, and CMs5 is the sum of the parasitic capacitances around source of gm3R3) of the FCG circuit is small, the input pole frequency is high. In
M5. All these capacitances can be described as Equation (13), as CM23 + CX, CM31 + CY are reduced due to the intro­
⎧ duction of the equivalent negative Miller capacitances CX and CY, the
⎪
⎪
⎪
⎪ pole frequencies ƒp-X, ƒp-Y are increased.
⎪
⎪
⎪
⎪ Meanwhile, as CM15 + CZ, CM5 + CO are increased due to the
⎪ CMi = Cgs2 + Csb2 + Csb1 + (1 + gm2 R2 gm3 R3 )Cgs1
⎪
⎪
⎪ [ ]
⎪
⎪
⎪
⎪ 1
⎪
⎪ CM15 = Cdb1 + Cgb5 + 1 − Cgd1
⎪
⎪ gm1 R1 (1 − gm2 R2 gm3 R3 )
⎪
⎪
⎪
⎪
⎪
⎪ 1
⎪
⎪ +(1 + gm5 RD )Cgd5 + Cgs5
⎪
⎪ 1 + gm 5 RS
⎪
⎪
⎪
⎪
⎪
⎨ CM23 = Cgd2 + Cdb2 + Cgs3 + (1 + gm3 R3 )Cgd3
⎪
( ) ( )
⎪ 1 1
⎪
⎪ C M31 = C db3 + C gb1 + 1 + C gd3 + 1 + Cgs1
⎪
⎪ gm3 R3 gm2 R2 gm3 R3
⎪
⎪
⎪
⎪
⎪ +[1 − gm1 R1 (1 − gm2 R2 gm3 R3 )]Cgd1
⎪
⎪
⎪ ( )
⎪
⎪
⎪
⎪ 1
⎪
⎪ C M5 = Cdb5 + 1 + Cgd5
⎪
⎪ gm5 RD
⎪
⎪
⎪
⎪
⎪
⎪ − 1
⎪
⎪ CMs5 = Csb5 + Cgs5
⎪
⎪ gm 5 RS
⎪
⎪
⎪
⎪
⎪
⎩

(11)

from (10), the pole frequency ƒp-IN at the input node and the pole fre­
quencies ƒp-X, ƒp-Y, ƒp-Z, ƒp-O at the X, Y, Z, O nodes can be written as

Fig. 5. Bandwidth comparison of the proposed TIA with the current two
FCG-TIAs.

63
J. Zhang et al. Integration 91 (2023) 60–66

Fig. 9. Layout of the circuit.

introduction of the equivalent positive capacitances CZ and CO, the pole

frequencies ƒp-Z and ƒp-O are reduced. However, by using the capacitive
degeneration at the gain stage, the zero frequency ƒz-S is introduced.
1
fz− S ≈ (13)
2 π RS C S
Fig. 6. Equivalent noise current spectral densities of the proposed TIA and the According to (13), under the condition that the gain is guaranteed
other two FCG-TIAs. (RS remains constant), by changing the value of CS so that ƒz-S ap­
proaches the smaller of the ƒp-Z and ƒp-O, the bandwidth is pushed higher
based on the zero-pole compensation.
Moreover, the low-frequency transimpedance gain of the proposed
FCG-TIA can be expressed as
R1 gmS RD
Z(0) ≈ − (14)
1 + gmS RS
According to (14), because gmSRS » 1 results 1 + gmSRS ≈ gmSRS, and
(19) can be simplified to
R1 RD
Z(0) ≈ − (15)
RS
As a result, from Equation (16), by designing RD > RS, the tran­
simpedance gain of the proposed TIA can be greatly improved compared
with the basic FCG-TIA (Z1(0) ≈R1).

4. Results and discussion

Based on the TSMC 65 nm CMOS process, the simulation analysis of

Fig. 7. Eye diagram of the 25 Gb/s input current with 100uA.
the proposed circuit is carried out by using the Cadence software. The
supply voltage is set as1.8 V, the bias voltage is set as 1.3 V, the parasitic

Fig. 8. MONTE-CARLO Analysis (a) transimpedance gain and (b) -3 dB frequency bandwidth.

64
J. Zhang et al. Integration 91 (2023) 60–66

Table 2
Performances comparison of the proposed TIA and other published COMS TIAs.
[2] [7] [12] [15] [11] [17] This work

Year 2018 2018 2019 2019 2020 2021 2022

technique CS-Diff RGC-Current Inv-Inductive Shunt Inv-Inductive Series RGC-Inductive Shunt RGC-Active Inductive FCG-Negative Miller
Feedback Reuse Peaking Peaking Peaking Peaking capacitance
Process 180 nm 65 nm 65 nm 65 nm 180 nm 130 nm 65 nm
CMOS CMOS CMOS CMOS CMOS BICMOS CMOS
Input Capacitance 250 200 250 – 500 230 200
(fF)
Gain(dBΩ) 45.2 62 42 49 49.7 53.2 60.1
Bandwidth (GHz) 21.2 11 24 29.9 9.2 14 23.7
Power(mW) 10.3@1.8 10@1 V 3@1.2 V 4.42@1.2 V 5.3@1.8 V 9.8@1 V 4.8@1.8 V
V
Noise current(pA/ 63.1 30 – 30 15.3 16.8 40.7
√Hz)
Number of 0 0 3 3 1 0 0
Inductors
Area(mm2) – 0.0800 0.0200 0.0200 0.0667 0.0210 0.0027
FoM 1.48 9.24 3.15 3.97 8.65 9.52 24.51

capacitance of the PD is set as Cpd = 200 fF, the resistances are set as R1
= 1.1 kΩ, R2 = R3 = 1 kΩ, RD = 3 kΩ, RS = 600 Ω, and the capacitances
are set as CXZ= CYO = 1 fF, CS = 20 fF. The designed aspect ratios W/L of
transistors M1, M2, M3, M4 and M5 are shown in Table 1, where all the
transistor channel lengths are designed as L = 60 nm.
The frequency response comparison of the proposed TIA with the
basic FCG-TIA and the FCG-TIA with capacitive degeneration are shown
in Fig. 5. From Fig. 5, the gain of the basic FCG-TIA is 57.2 dBΩ, and the
bandwidth is 15.2 GHz, the gain of the FCG-TIA with capacitive
degeneration-based CS amplifier is increased to 60.1 dBΩ while the
bandwidth is extended to 17.6 GHz due to the introduction of zero. The
gain of the proposed TIA is 60.1 dBΩ, and the bandwidth is further
extended to 23.7 GHz by using negative Miller capacitance.
For the basic FCG-TIA, its small input resistance reduces the limita­
tion of the photodiode parasitic capacitance on the bandwidth, but the
limitation of the parasitic capacitance between the amplifier stages re­
mains, resulting in a lower bandwidth. For the FCG-TIA with capacitive
degeneration-based CS amplifier, by using the cascaded CS amplifier,
the gain improved due to the gain resistance is greater than the degen­
eration resistance. On the other hand, when the zero introduced by the
capacitive degeneration is greater than the dominant pole, the gain
response will be raised firstly and then fall down, which makes the
bandwidth become wider, but also causes the gain curve is not flat and
even spike. Moreover, as the capacitive degradation can only introduce a
single zero, the bandwidth expansion for the FCG-TIA with multiple
poles is limited.
Compared to the basic FCG-TIA and the FCG-TIA with capacitive
degeneration, the negative Miller capacitance and capacitive degener­
ation have been combined within the proposed TIA. By using the
negative Miller capacitance the bandwidth limitation caused by para­
sitic capacitance around the nodes inside the amplifier circuit has been
reduced. Meanwhile, a zero is introduced to compensate the bandwidth
drop due to pole frequency reduction caused by positive Miller capaci­
tance. As a result, the bandwidth of proposed TIA is further improved.
Furthermore, the equivalent noise current spectral densities of the
circuits are shown in Fig. 6. From Fig. 6, the average equivalent input
noise current spectral densities of the basic FCG-TIA, the FCG-TIA with
capacitive degeneration, and the proposed TIA are 29.3 pA/√Hz, 33.5
pA/√Hz, and 40.7 pA/√Hz respectively.
The 10 ns transient simulation was carried out by inputting 231− 1
pseudo-random binary sequence (PRBS) signals with peak-peak value of
100 μA(one value of +50 μA, zero value of − 50 μA), signal period of 40
ps (speed of 25 Gb/s), rising edge of 4 ps, and falling edge of 4 ps? The
output transient signals are repeatedly superimposed in an 80ps window
to form the eye diagram. Fig. 7 is the simulated results. It can be seen
that the eye diagram has better expansion, smaller jitter, and complete
symmetry, which can meet the optical fiber communication re­
quirements of 25 Gb/s.
The MONTE-CARLO analysis is done for 800 runs to analyze the non-
ideal effects of fabrication process. The results are shown in Fig. 8. Form
Fig. 8 the mean value and standard deviation of the transimpedance gain
are 59.9 dBΩ and 0.3 dBΩ, and the mean value and standard deviation of
bandwidth are 23.71 GHz and 875.26 MHz.
Fig. 9 shows the designed layout area of the proposed TIA. The N-
MOSFETs, capacitors, and resistors are designed using the NCH, MIM,
and Rnpoly technology respectively. As can be seen from Fig. 9, the
layout area is mostly occupied by resistors due to the fact that the values
of the designed resistors are larger. However, as there is no inductors in
the circuit, the total layout area is as small as 0.0027 mm2.
In addition, Table 2 shows the performance comparison between the
proposed TIA and other recently published TIAs. Compared with the
circuit shown in Refs. [2,11], and [17], the bandwidth and gain of the
proposed TIA is increased at least 2.5 GHz and 6.9 dBΩ respectively.
Compared with the circuit shown in Ref. [7], the gain is 2 dBΩ lower, but
the bandwidth is increased by 12.7 GHz. Compared with Ref. [12,15],
the bandwidth is 0.3 GHz and 6 GHz lower respectively, but the gain is
increased by 18 dBΩ and 11 dBΩ. Besides, for Ref. [12,15], under the
same 65 nm CMOS process, as inductors are used in the circuit, the
layout area is about 7 times larger than the proposed TIA.
Considering that the performance of each circuit is determined by
several parameters including gain, bandwidth, noise, power consump­
tion, etc, the (figure of merit) FOM is used to evaluate the comprehen­
sive performance of TIAs. The FoM is written as [22].
Gain(Ω)⋅Bandwidth(GHz)⋅PD Capacitance(pF)
FoM = ( ) (16)
Input Noise √pA
̅̅̅̅ ⋅Power(mW)⋅(Number of inductors + 1)
Hz
As can be seen in Table 2, the FoM of the proposed TIA is 24.51,
which is improved compared with the existing techniques.
5. Conclusion
In this paper, a modified FCG-TIA has been proposed, designed and
simulated. By introducing the equivalent negative Miller capacitance,
the parasitic capacitance around the internal nodes of the amplifier
circuit is decreased, which results the internal pole frequency is
increased and the bandwidth of the circuit is improved. Besides, a
capacitive degeneration-based CS amplifier is used as the gain stage, a
zero is introduced to compensate the bandwidth decrease due to pole
frequency reduction caused by positive Miller capacitance.
Based on the TSMC 65 nm CMOS process, the performances of the
circuit are simulated, and the layout is designed. The results show that
the bandwidth is 23.7 GHz, the transresistance gain is 60.1 dBΩ, the

65
J. Zhang et al.
average equivalent input noise current spectral density is 40.7 pA/√Hz,
the power consumption is 4.8 mW, and the layout area is 0.0027 mm2.
Compared with the current reported TIAs, the bandwidth, trans­
resistance gain, and layout area of the proposed TIA have been
improved. All the results show that the proposed TIA has the potential
capability to be used in the optical receiver with higher speed.
Author statement
Jiahong Zhang: Conceptualization, Methodology, Investigation, Su­
pervision, Formal analysis, Writing – original draft. Zhuo Wang: Data
curation, Formal analysis, Software, Validation, Writing – original draft.
Chao Ma: Data curation, Visualization, Investigation;
Funding
This work was supported by the National Natural Science Foundation
of China [NO.62162034], the Basic Research Program General Project of
Yunnan Province [NO.202201AT070189].
Declaration of competing interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
Data availability
Data will be made available on request.
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