LiveCareer » Resume Search » Design Verification Engineer
Design Verification Engineer Resume Example
Customize This Resume
By clicking Customize This Resume, you agree to our Terms of Use and Privacy Policy
SEARCH FOR RESUMES BY INDUSTRY, JOB TITLE OR KEYWORD.
Design Verification Engineer
Search
JESSICA
CLAIRE
resumesample@example.com
(555) 432-1000
100 Montgomery St. 10th Floor
SKILLS
• IEEE 802.3 Ethernet standard
• IEEE 802.1AE MACSEC
• System Verilog UVM
• Simulation tools: QuestaSim,
Cadence Incisive, Synopsys DVE,
Verdi
• Formal verification using Jasper
• RTL Design using Verilog
• C++ and scripting using Python,
Perl, Shell
• AHB, AXI, APB protocols
• Micro-processor architecture
CERTIFICATIONS
Advanced diploma in RTOS and
Embedded Systems 6/2009 -
12/2009
Assembly and Embedded C
Programming on AVR Atmega128 and
ARM 7 LPC2148.
Communication protocols: RS-232,
I2C, and SPI), Data Structures, RTOS
Porting.
Application Development using uC-
OS II.
Embedded Linux Programming and
Application Development such as
‘chat' applications, primary and
backup server using socket
programming.
EDUCATION AND
TRAINING
North Carolina State University
Raleigh, NC • 2012
Master of Science: Computer
Engineering
Courses: ASIC Design, ASIC
Verification, Computer Architecture,
Architecture of Parallel Computer,
Advanced Microprocessors
PROFILE
Design Verification Engineer with nine years of experience
in verifying Ethernet IP, Video Encoder, NIC and other
complex systems using System Verilog (UVM). Experience
in Verilog, Python, Perl and Shell Scripting. Experienced in
full design verification flow on both ASIC and FPGA.
Experience in design using verilog, Spyglass RTL analysis
and Synthesis.
PROFESSIONAL EXPERIENCE
Amazon.Com, Inc. - Asic Engineer
Avenel, NJ • 08/2019 - Current
• Verification Network Interface Card ASIC
Full ownership of Transmit queue manager block. Built a
constrained random UVM test bench from scratch in a
reusable manner so as to be included in top-level
verification. Interacted with cross-functional members
from architecture, design and driver teams to bring the
block to closure. Coordinated with other DV block owners
on common components.
Lead contract workers
Register layer automation scripts in python
• Verification of Video Encoder: H264 and VP9 codecs
Owned 3 blocks within the video encoder pipeline:
Deblocking filter, Integer Motion Estimation, Command
DMA. Drove them to closure. Worked on AXI and AHB
interface BFM.
Built a random stimulus generator using SV constraints to
generate random motion vectors which were used by
multiple blocks in the pipeline for coverage closure.
• Built a DVS (data-valid-stall) coverage tool using Python
and System Verilog UVM.
Accenture Contractor Jobs - MTS Design Verification
Engineer
Fort Collins, CO • 04/2017 - 08/2019
• Verified the RX PCS based on Clause 82 of IEEE 802.3 on
100G and 40G Ethernet IP
• Lead a team including offshore CW's on verification of
Auto-negotiation (Clause 73) and Link Training logic
(Clause 72, 93 of IEEE 802.3).
Test plan creation, test writing, results and coverage
tracking. Enabled a team in Penang to reuse our tests +
testbench for verifying the above features on 10G/25G,
hence saving 6-8 weeks of effort.
• Lead the testbench architecture and test plan creation
for "Dynamic reconfiguration" feature.
This feature changes the previous static speeds and mode
to dynamically switch between speeds: 100G, 25G, 10G
and modes: full stack (MAC+PCS), PCS only, OTN, FLEXE.
We scaled our existing bench to work for multi-channel
architecture hence reusing existing tests.
 • Verification of a Pipelined LC-3 Brewer Science - Verification Consultant for Microsoft
Microprocessor (System Verilog Vichy, MO • 03/2016 - 04/2017
VMM, QuestaSim)
• Verification of Saas FPGA for Bing search acceleration
• Design of Packet Forwarding
(System verilog UVM)
Engine for Fast Address Lookups
The Data Access Layer within the Saas FPGA handles
in a router (Verilog, Modelsim,
posting list access requests from higher layers and fetches
Synopsys Design Vision)
corresponding index from a memory hierarchy that is
• Cache and Memory Hierarchy
composed of on-chip RAM, on board DDR and host memory.
Design (C++)
In previous versions, verification stimulus was a simple
• Dynamic Instruction Scheduling
playback of query files. I helped with the generation of
Simulator Applying Tomasulo's
synthetic stimulus data in the form of a system verilog
algorithm (C++)
library for verifying the system. This helped in achieving
University of Mumbai 100% code and functional coverage by testing all possible
Mumbai, Maharashtra • 2009 corner cases.

Bachelor of Science: Electronics Icon - Verification Engineer

and Telecommunications
Panorama City, CA • 12/2012 - 03/2016
• Verified the MAC and Statistics blocks (System Verilog-
UVM)
Verified IEEE 802.3 clause 3 - Ethernet MAC layer involving
frame packaging and processing along with several custom
features. Register readable MAC statistics were
functionally verified.
• Verified the MACSEC block compliant with IEEE 802.1AE
(System Verilog-UVM)
Responsible for verification of the highly complex receive
classifier that would preprocess the frames and extract
useful information that would be used by the GCM-AES
core.
• RTL Design of MDIO (Verilog)
• Bug analysis tool for mining data from Bugzilla (Perl)
(Individual project)
• Verified Layer 1 Fibre Channel compliant with FC-FS-6
(System Verilog-UVM)
Verified from testplan to coverage closure: 32G and 16G
fibre channel using 64b/66b transmission word format and
8G, 4G and 2G fibre channel 8b/10b transmission word
format.
• Verification of Energy Efficient Ethernet in the Low
Speed Physical Coding Sublayer(LS PCS) compliant with
Clause 36 of IEEE 802.3 (System Verilog-UVM)
(Individual project)
• Integrated third party Avago 16nm and 28nm Serdes IP
and BPAN (Backplane auto-negotiation) with our
universal MAC IP for interoperability testing.

International Research And Development Centre - Senior

Research Associate
City, STATE • 08/2010 - 07/2011
• Implemented several Computational algorithms for

Customize This Resume

By clicking Customize This Resume, you agree to our Terms of Use and Privacy Policy

Disclaimer
Resumes, and other information uploaded or provided by the user, are considered User Content governed by our Terms &
Conditions. As such, it is not owned by us, and it is the user who retains ownership over such content.

How this resume score

could be improved?
Many factors go into creating a strong resume. Here are a few tweaks that could improve the score of this
resume:

75
AVERAGE

Resume Strength

Formatting

Personalization

Target Job
 Resume Overview

School Attended
North Carolina State University
University of Mumbai

Job Titles Held:

Asic Engineer
MTS Design Verification Engineer
Verification Consultant for Microsoft
Verification Engineer
Senior Research Associate
Research Associate

Degrees
Master of Science
Bachelor of Science

Customize This Resume

By clicking Customize This Resume, you agree to our Terms of Use and Privacy Policy

Similar Resume
Design Verification Engineer
Intel Corporation, VPG Group
Las Vegas, Nevada

Design Verification Engineer

MANGSTOR
Austin, Texas

Design Verification Intern

Arrow Devices
 Gainesville, Florida

View All

*As seen in:

*The names and logos of the companies referred to in this page are all trademarks of their respective holders. Unless specifically stated otherwise, such references
are not intended to imply any affiliation or association with LiveCareer.

Resume Cover CV About Help & Languages Customer Service

Letter Support
Resume CV About EN DE customerservice@livecareer.com
Builder Cover Examples Us Work Here
UK NL 800-652-8430 Mon- Fri 8am -
Letter
Resume Builder CV Privacy Contact Us 8pm CST
Examples Templates Policy ES PT Sat 8am - 5pm CST, Sun 10am -
Cover FAQs
Resume CV Terms FR PL 6pm CST
Letter
Templates Examples Formats of Use Accessibility
IT
Resume Cover
Formats Letter
Resume Templates
Objectives Cover
Letter
How to
Formats
Write a
Resume How to
Write a
Cover
Letter

© 2023, Bold Limited. All rights reserved.