Short Course On

Phase-Locked Loops and Their Applications

Day 3, PM Lecture

Behavioral Simulation Exercises

Michael H Perrott
August 13, 2008

Copyright © 2008 by Michael H. Perrott

All rights reserved.
 A Modern “Analog” Custom IC

ƒ A 2.5 Gb/s CDR for

high speed links
- Analog
amplification and
phase sensing
- Digital
filtering and
calibration
- RF
clock generation
(2.5 GHz)
ƒ How do we design
such chips?

M.H. Perrott 2
 Simplified View of a Top Down, Mixed-Signal Design Flow

High Level
System Design Investigation &
Architecture Analysis

Circuit Design Circuit Design Code Creation

Schematic Creation
Analog Digital Place & Route

Extracted Layout
Creation Circuit Circuit Digital Test Vectors
PVT Corners Verification Verification Timing Checks
Monte Carlo Analog Digital

System
Verification System Level
Circ. & Arch. Test Vectors

M.H. Perrott 3
 The Many Simulation Tools Involved …
Popular Tools
System Design
Architecture Matlab/Simulink
ADS

Circuit Design Circuit Design

Analog Digital
SPICE Verilog/VHDL

Verilog AMS
Circuit Circuit AMS Designer
Verification Verification
Analog Digital

System
Verification ????????
Circ. & Arch.
M.H. Perrott 4
 Goal: Create a Universal Simulator

System Designer
Analog Designer
Digital Designer

Managing
Kernel

SPICE Verilog
VHDL
Matlab

ƒ The challenges of developing the Managing Kernel

- Difficult to match up simulator signals at their boundaries
without overly complicating the life of the user
- Difficult to maintain fast simulation speed
M.H. Perrott
- Difficult to retrain designers on a new tool with a new flow 5
 A Different Approach

ƒ Look for commonality among simulators to allow

“universal” simulation models to be used
- C++ provides one such hook
ƒ Allow designers to use their tool of choice while
sharing “universal” simulation models

SPICE Verilog
VHDL
Matlab

C/C++ C/C++
PLI Calls C/C++ PLI Calls
(Verilog AMS Mex functions
& AMS Designer)

Key idea: bootstrap into existing simulators

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 The VppSim Simulator Greatly Simplifies This Process

ƒ Graphically driven generation

Cadence Schematic
Entry
of simulator blocks based on a
C++ primitive library
C++ primitive
library
Automatic
Simulation wrapper
parameter file generation

Verilog Verilog PLI

PLI Calls Mex & Code Gen.
Function

AMS
NCVerilog
Designer
Matlab

Analog Designer Digital Designer

System Designer
M.H. Perrott 7
 C++ Code Can Also Be Directly Simulated

Cadence Schematic Automatic

Entry C++ system CppSim
generation
C++ primitive
library

Simulation
Automatic ƒ Advantage:
parameter file
wrapper
generation - Very fast!
Verilog Verilog PLI
PLI Calls Mex & Code Gen.
Function

AMS
NCVerilog
Designer
Matlab

Analog Designer Digital Designer

System Designer
M.H. Perrott 8
 CppSim Compiler

CppSim Module C++ Class for Simulation File

Description Module Object Time step value
Name Constructor Number of sim steps
Inputs, Outputs Destructor Probing of signals
Parameters State Variables
Code Functions

CppSim Module C++ Class for

Description Module Object
Name Constructor C++
Inputs, Outputs Destructor Simulation
Parameters State Variables Program
Code Functions

CppSim Module C++ Class for SPICE Netlist

Description Module Object Topology of
Name Constructor system
Inputs, Outputs Destructor - Generated by
Parameters State Variables Cadence or
Code Functions Sue2

M.H. Perrott 9
 VppSim Compiler (for NCVerilog)

CppSim Module C++ Class for Verilog Wrapper Simulation File

Description Module Object for Module Time step value
Name Constructor Verilog PLI Number of sim steps
Inputs, Outputs Destructor function calls Probing of signals
Parameters State Variables Embedded C++
Code Functions Class Object

CppSim Module C++ Class for Verilog Wrapper

Description Module Object for Module
Name Constructor Verilog PLI Verilog
Inputs, Outputs Destructor function calls Simulation
Parameters State Variables Embedded C++ Native Verilog
Modules
Program
Code Functions Class Object
ASCII file
descriptions

CppSim Module C++ Class for Verilog Wrapper

Description Module Object for Module SPICE Netlist
Name Constructor Verilog PLI Topology of
Inputs, Outputs Destructor function calls system
Parameters State Variables Embedded C++ - Generated by
Code Functions Class Object Cadence

All CppSim modules supported (including vector signals)

Same timing approach for module execution as CppSim
M.H. Perrott 10
 VppSim Modules for AMS
CppSim Module C++ Class for Verilog Wrapper
Description Module Object for Module
Name Constructor Verilog PLI
Inputs, Outputs Destructor function calls
Parameters State Variables Embedded C++
Code Functions Class Object

CppSim Module C++ Class for Verilog Wrapper

Description Module Object for Module
Name Constructor Verilog PLI AMS
Inputs, Outputs Destructor function calls Simulation
Parameters State Variables Embedded C++ Program
Code Functions Class Object

CppSim Module C++ Class for Verilog Wrapper

Description Module Object for Module
Name Constructor Verilog PLI
Inputs, Outputs Destructor function calls
Parameters State Variables Embedded C++
Code Functions Class Object

Not all CppSim modules are supported (i.e., no vector signals)

M.H. Perrott
Different timing approach for module execution 11
 Example with Double Signals
CppSim module VppSim module
module: leadlagfilter ////// Auto-generated from CppSim module //////
parameters: double fz, double fp, module leadlagfilter(in, out);
double gain parameter fz = 0.00000000e+00;
inputs: double in parameter fp = 0.00000000e+00;
outputs: double out parameter gain = 0.00000000e+00;
static_variables: input in;
classes: Filter filt("1+1/(2*pi*fz)s", output out;
"C3*s + C3/(2*pi*fp)*s^2",
"C3,fz,fp,Ts",1/gain,fz,fp,Ts); wreal in;
init: real in_rv;
code: wreal out;
filt.inp(in); real out_rv;
out = filt.out;
assign out = out_rv;

initial begin
assign in_rv = in;
end

always begin
#1
$leadlagfilter_cpp(in_rv,out_rv,fz,fp,gain);
end
endmodule
M.H. Perrott 12
 The Issue of Timing/Ordering

(1) Best Execution Order

Execution Order A B C
A
E
B Delay D
C
D E

Impact of Alternate Ordering Arrangement

(2)
Execution Order A B Delay C
A
E
C Delay D
B
D E

ƒ Ordering influences delays

ƒ CppSim blocks are ordered automatically or by user
M.H. Perrott 13
 Cadence Interface

ƒ Choose between CppSim, VppSim (for NCVerilog), and

AMS with VppSim modules
ƒ CppSim and VppSim run in above window or in Matlab
M.H. Perrott 14
 Windows Version of CppSim

ƒ Will be used in class today

ƒ Available for free download at http://www.cppsim.com

ƒ Initial part of this session: fractional-N example

ƒ Remaining part of this session: example of your
choice

M.H. Perrott 15
 Windows Interface

M.H. Perrott 16