The Veloce Emulator: Laurent VUILLEMIN Platform Compile Software Manager Emulation Division

The Veloce Emulator
and its Use for Verification and System

Integration of Complex Multi-node SOC
Computing System
Laurent VUILLEMIN
Platform Compile Software Manager
Emulation Division
Agenda
 What is Emulation
 Use models
 Veloce Architecture Overview
 Veloce Software
 Practical : Use Veloce to verify Veloce
© 2010 Mentor Graphics Corp. Company Confidential

2 www.mentor.com
Agenda
 Use models
 Veloce Software

3 www.mentor.com
Verification Challenges
Software
Systems
Debug
4 www.mentor.com
Typical Development Cycle
Hardware
Hardware
Development
Development Fab
System Integration
Software Development
Block-level Chip-level System

Verification Verification Verification
Time to
Market
Design Cycle
5 www.mentor.com
Typical System Development
Hardware Development Fab
System Integration
Software Development
Block-level Chip-level System

Verification Verification Verification
Time to
Market
Design Cycle
6 www.mentor.com
Software Simulation
module counter (ck, en,

 Model is
represented in
step, dout);
input ck, en;
input [3:0] step
Data Structures
output [3:0] dout
reg [3 : 0] dout;
Compute and
always @ (posedge ck)
begin
if ( en ==1 )

propagate signal
dout = dout+step;
end
endmodule
values
RTL Model
module counter (ck, en, step,

dout);
input ck, en;
input [3:0] step
output [3:0] dout
reg [3 : 0] dout;

begin
if ( en ==1 )
dout = dout+step;
end
endmodule
Test bench
7 www.mentor.com
Clock Speed Scaling Stalls
Emulation Required
to Extend Performance
Source: Recording Microprocessor History 4/6/2012 Andrew Danowitz, Kyle Kelley, James Mao,
John P. Stevenson, Mark Horowitz http://queue.acm.org/detail.cfm?id=2181798
www.mentor.com
Emulation
module counter (ck, en,

step, dout);
input ck, en;
input [3:0] step
output [3:0] dout
reg [3 : 0] dout;

begin
if ( en ==1 )
dout = dout+step;
end Map RTL model in Control execution
endmodule
Programmable Logic and get results
Programmable
RTL Model
Logic
•Multiples FPGA reproduce Model behavior from high level description

9 www.mentor.com
Start Early – Continue for Entire SoC Life
Post Silicon
Bringup and
Systems Validation
Validation
Software,
Firmware &
Fullchip/SoC Device
Verification Drivers
Block-level
Verification
Architecture
Phase

www.mentor.com
Agenda
 Use models
 Veloce Software

11 www.mentor.com
Modern SOC environment
Embedded SW Debugger
SoC PHY PHY PHY PHY

Display
CPU USB Ethernet SATA
Processor
Master IF SlaveIF Slave IF Slave IF Slave IF
RSP
Arbiter
Master IF Master IF Fabric Fabric

JTAG Software
CPU
Memory PCI
Slave IF Slave IF Express
PHY
UART GPIO

12 www.mentor.com
ICE use Model
 The emulator is connected to actual Hardware
External
Hardware
Cables
DUT

13 Veloce www.mentor.com
Ethernet Verification With ICE
Ethernet Network Stimulus Generation / Analysis Tools
Live
Traffic
iSolve
Ethernet

14 www.mentor.com
Co Emulation
Testbench Xpress (TBX)
Testbench
PCI E 1/2
DUT
X-actor
 Testbench divided in 2 parts
AGP 1/2
X-actor
one in emulator the other in
Transactions Station
USB 1/2
X-actor
 Communication via
1/2 X- transactor
actor
 Software sends commands

that are interpreted by
transactor to generate DUT
stimulus
High-speed
Interface
Software Hardware
15 www.mentor.com
Veloce Use Models
Simulation Acceleration
OVM/UVM SystemVerilog C/SystemC
Accelerated Transactors
Co-Model Channels
SW Debug
Testbench Xpress
Codelink VProbe Fast ISS QEMU
Software Debug
Virtual Protocol Solutions

USB SATA Video Ethernet PCIe
VirtuaLAB Solutions
Physical Protocol Solutions

PCIe SATA Video USB Ethernet .... Physical I/O
iSolve Solutions

16 www.mentor.com
Agenda
 Use models

 Veloce Software

17 www.mentor.com
Veloce 2 Architecture
AVB2 Maximus2
Crystal2 Chip
X 16
X 64
+ 40 SXB (Switch boards)

+ 4 CXB (clock board)
Quattro2
16 AVB2
+ 6 SXB (Switch boards)
+ 1 CXB (clock board)

18 www.mentor.com
Crystal 2 IC
 Programmable Logic Array
 Set of LUT an Sequential elements
 Interconnect Network
Control
 Memories :
Programmable Logic
 User Memories model
Array
Debug  Virtual Wire Logic
Resources  Transport signals between chips
 Debug Resources
Virtual Wire Trace every Sequential element and
Memories 
Logic memories
 Triggers
 Control
 Load configuration
 Control emulation

19 www.mentor.com
Agenda
 Use models
 Veloce Software
— Compile Software
— Runtime Software

20 www.mentor.com
Software Overview
N
e
PC Farm
t
w
o Emulator host
r
Compile Servers k
Low
User Compile Configuration Runtime
Level
SW SW
design bitstream SW
Transform User Interface

design in Control Emulator
bistream Collect debug data

21 www.mentor.com
Compile software
Design
+Testbench
TBX Partition Testbench between SW and Emulator
RTL
RTLC Perform RTL Synthesis
Gate netlist
Partitioning in Crystal
Sytem Routing
Platform Compile
Crystal Place and Route
Ressource Allocation
Bitstream

22 www.mentor.com
Runtime Software
Mainten Ressour
ance ce
Server Server
Emulator Message Bus
Runtime Emulator
Server Host
Server
LLSW
User Message Bus
Visibility
UI
Server

23 Veloce DAC 2014 www.mentor.com
Agenda
 Use models
 Veloce Software

— Challenges
— The verification infrastructure
— Verifying ASIC
— Verifying the Compilation software
— Low level software integration
— Firmware validation debug
— Runtime software integration

24 www.mentor.com
Challenges
 Complex system
— ASIC
— FPGAs Firmware
— Mutliple software components
 Verifying all component of the system and their
interactions
 Time to get a bug
 Size :
— Detailed model of a full Emulator of next generatio will not fit in
current generation

25 www.mentor.com
Addressing the challenges
 Use a comodel approach for more abstraction level and

connection with the software
 Divide verification in steps based on functionality
 Simplify the model by using different abstraction level

depending on what functionality is tested

26 Veloce DAC 2014 www.mentor.com
Verification Infrastructure
More details on Veloce
Control Control Control

Chip
LLSW
on host
Crystal Crystal
Veloce Control Bus
Control
Commands

Verification Infrastructure
Emulation model
Control
Transactor Control Control
Software Chip
Crystal Crystal
Veloce Control Bus
Emulator
Nature of the Software, Transactor and Model in emulator depend

on abstraction level

ASIC verification : example of Trace
Data Transac DDR

Comodel SW tor
Control
Controler
DDR
SW translator Macro Block
Trace Capture Trace

control
Veloce
Comands
Design
Crystal
Emulation Model
Trace Capture, Trace Control and DDR Controler are Accurate models
Design is a gate level netlist generating random data
Data are either manually generated or come from actual compile
Run million cycles on multiple designs

Verification of compile SW
Bitstream
Transac Configuration
Comodel SW tor
Control
Block
LLSW
Bitstream
reader Macro Block
Veloce
Comands
Crystal
Emulation Model
Macro and Configuration blocks are Accurate models

Bitstream is the output of actual compile flow
Verify behavior of design

Verification of Low Level Software 1/2
Example : Virtual Wire Synchronisation
Data multiplexed
on serial link
Virtual Wire Virtual Wire
Control Control
Logic Logic
Crystal Crystal
Virtual Wire need a training/Calibration sequence

This sequence is controled by Low Level Software

Verification of Low Level Software 2/2
Trans Control
Actual LLSW Comodel SW actor Chip
Control Control
VW Block VW Block
Crystal Crystal
Emulation Model
Control block in Crystal and VW block are accurate model

Actual LLSW communicate with the model through comodel SW
and transactor

Verification of Firmware 1/2
Example : Trigger Reduction
AVB Level
System Level
reduction
reduction
FPGA
AVB Level FPGA
reduction
Trigger Trigger
Logic FPGA Logic CXB
Trigger Trigger
Logic Macro Block Logic Macro Block
Crystal Crystal
Macro Block Macro Block
AVB
Crystal Crystal
AVB
A trigger express a condition on values coming from the design

At AVB and System level it is implemented in FPGA
A binary is genrerated by runtime SW to express condition
Verification of Firmware
Trigger
binary Transac
Comodel SW Control
AVB Level
tor
reduction
System
FPGA Level
reduction
Trig Trig
FPGA
ger ger
Logi Logi
c c
AVB Level
SW translator reduction CXB
Macro Macro
FPGA
Block Block
Crystal Crystal
Trig Trig
ger ger
Logi Logi
c c
AVB
Macro Macro
Block Block
Veloce Crystal Crystal
Comands AVB
Emulation Model
Design is modeled as gate level netlist

Trigger binary is generated by actual runtime SW
Verify behavior of trigger in multiple design sequences

Runtime SW Verification
Ressource Emulator
Server Host
Server
Emulator Message Bus LLSW
Runtime
Server Comodel SW
User Message Bus Crystal

Transac Control
tor
UI Macro Block
Design
Actual Runtime Server is used Memories

High level model for the HW
Emulation Model

QUESTIONS

Veloce
36 www.mentor.com

The Veloce Emulator: Laurent VUILLEMIN Platform Compile Software Manager Emulation Division

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

The Veloce Emulator: Laurent VUILLEMIN Platform Compile Software Manager Emulation Division

Uploaded by

Copyright:

Available Formats

The Veloce Emulator

and its Use for Verification and System

 Veloce Architecture Overview

 Practical : Use Veloce to verify Veloce

© 2010 Mentor Graphics Corp. Company Confidential

 Veloce Architecture Overview

 Practical : Use Veloce to verify Veloce

© 2010 Mentor Graphics Corp. Company Confidential

Block-level Chip-level System

Hardware Development Fab

Block-level Chip-level System

module counter (ck, en,

module counter (ck, en, step,

always @ (posedge ck)

module counter (ck, en,

always @ (posedge ck)

•Multiples FPGA reproduce Model behavior from high level description

© 2010 Mentor Graphics Corp. Company Confidential

© 2010 Mentor Graphics Corp. Company Confidential

 Practical : Use Veloce to verify Veloce

© 2010 Mentor Graphics Corp. Company Confidential

SoC PHY PHY PHY PHY

Master IF Master IF Fabric Fabric

© 2010 Mentor Graphics Corp. Company Confidential

 The emulator is connected to actual Hardware

© 2010 Mentor Graphics Corp. Company Confidential

Ethernet Network Stimulus Generation / Analysis Tools

© 2010 Mentor Graphics Corp. Company Confidential

 Software sends commands

Virtual Protocol Solutions

Physical Protocol Solutions

© 2010 Mentor Graphics Corp. Company Confidential

 Veloce Architecture Overview

 Practical : Use Veloce to verify Veloce

© 2010 Mentor Graphics Corp. Company Confidential

+ 40 SXB (Switch boards)

© 2010 Mentor Graphics Corp. Company Confidential

© 2010 Mentor Graphics Corp. Company Confidential

 Veloce Architecture Overview

 Practical : Use Veloce to verify Veloce

© 2010 Mentor Graphics Corp. Company Confidential

Transform User Interface

© 2010 Mentor Graphics Corp. Company Confidential

TBX Partition Testbench between SW and Emulator

RTLC Perform RTL Synthesis

© 2010 Mentor Graphics Corp. Company Confidential

Emulator Message Bus

© 2010 Mentor Graphics Corp. Company Confidential

 Veloce Architecture Overview

 Practical : Use Veloce to verify Veloce

© 2010 Mentor Graphics Corp. Company Confidential

© 2010 Mentor Graphics Corp. Company Confidential

 Use a comodel approach for more abstraction level and

 Divide verification in steps based on functionality

 Simplify the model by using different abstraction level

© 2010 Mentor Graphics Corp. Company Confidential

Control Control Control

© 2010 Mentor Graphics Corp. Company Confidential

Nature of the Software, Transactor and Model in emulator depend

© 2010 Mentor Graphics Corp. Company Confidential

Data Transac DDR

SW translator Macro Block

Trace Capture Trace