ACM/IEEE International Design Automation Conference, Anaheim, CA, 1997
STARBIST: Scan Autocorrelated Random Pattern Generation
K.H. Tsai1, S. Hellebrand2, J. Rajski3, M. Marek-Sadowska1
1
Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA
2
Institute of Computer Structures, University of Siegen, Siegen, Germany
3
Mentor Graphics Corporation, Wilsonville, OR, USA
Abstract. This paper presents a new scan-based BIST scheme
which achieves very high fault coverage without the deficiencies
of previously proposed schemes. This approach utilizes scan order
and polarity in scan synthesis, effectively converting the scan
chain into a ROM capable of storing some “center” patterns from
which the other vectors are derived by randomly complementing
some of their coordinates. Experimental results demonstrate that a
very high fault coverage can be obtained without any modification
of the mission logic, no test data to store and very simple BIST
hardware which does not depend on the size of the circuit.
1 Introduction
The scan-based Built-In-Self-Test (BIST) schemes,
which rely on full/partial scan design for testability, use Linear
Feedback Shift Registers (LFSRs) as generators of pseudo-ran-
dom patterns, and employ Multiple-Input Shift Registers (MISRs)
as test response compactors, are becoming widely adopted due to
their conceptual simplicity and ease of implementation. These
schemes naturally extend scan-based test methodology with
ATPG generated patterns applied from an ATE to BIST. The addi-
tional hardware required to implement the BIST hardware is not
large and there are commercially available tools for its automated
synthesis. The designers welcome the advantages that BIST offers
provided that the quality of the test is as good as that of the state-
of-the-art ATPG. However, very high fault coverage usually can-
not be easily achieved without addressing the problem of pseudo-
random pattern resistant faults.
There are two types of methods proposed to solve this
problem, one by modifying the mission logic to make the resistant
faults pseudo-random testable, and the other by increasing the
ability of the test pattern generators to target pseudo-random pat-
tern resistant faults. Test point insertion is the main technique of
the first type [16, 7, 11, 12, 4, 13]. Low hardware overhead and no
extra memory needed to achieve very high fault coverage are the
main advantages of this technique. However, the modification of
the mission logic may not be acceptable by designers due to the
possible performance degradation and its impact on the design
flow. In a reusable core defined by a netlist such modification of
the mission logic may simply not be possible.
The second type of methods, which contain reseeding
[8, 6], weighted random patterns [17, 3, 9], pattern mapping and
*This research was supported in part by the NSF grant MIP 9419119
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1
other techniques [1, 5, 14, 10], focus on the characterization of
complete test sets. These methods extend the conventional
pseudo-random test pattern generators based on LFSRs by biasing
the patterns to cover random pattern resistant faults. They achieve
very high fault coverage in an acceptable number of patterns, but
they need extra memory to store seeds, weight sets or additional
logic has to be implemented. The extra memory needed is usually
proportional to the size of the circuit and is very expensive for
large designs.
In this paper we propose a new BIST structure to gener-
ate high quality test patterns without extra memory to store deter-
ministic patterns, seeds or weights. Unlike previous methodol-
ogies, this new structure doesn’t use the conventional LFSR
directly to generate pseudo-random patterns. Our method doesn’t
modify the mission logic, thus there is no performance degrada-
tion and no need for resynthesis. This new approach is based on an
experimental observation that a very high fault coverage can be
obtained by a small number of clusters of test vectors. Each clus-
ter contains one parent test vector in the center and a number of
children derived from the parent by complementing some number
of coordinates in a pseudo-random manner. The parent vector is
computed by a specialized ATPG algorithm capable of targeting
many pseudo-random pattern resistant faults.
The implementation makes use of scan order, polarity
between the neighboring cells, and control points inserted
between scan cells. With these features the scan chain has the
properties of a ROM capable of encoding several parent test vec-
tors. The children are generated by a simple hardware capable of
complementing coordinates of parents at random and no addi-
tional memory is required to enhance the capabilities of the gener-
ator. It is demonstrated experimentally that the entire test
information required for high quality test can be encoded in the
scan chain.
In the next section we discuss a simple example, well-
known in the context of weighted random techniques. We propose
the solution to this example which demonstrates the motivations
of this paper. The principle of a compressed hierarchical structure
of the test patterns is presented in the third section. Section 4 gives
a detailed description of the required elements including the con-
trol signals and the encoding technique for a fixed number of
deterministic patterns. An overview of the complete BIST archi-
tecture and the synthesis algorithm follow in sections 5 and 6.
Section 7 presents the experimental results, and finally the paper is
concluded in section 8.
2 A Motivational Example
In this section the basic principles of the proposed
approach will be introduced with the help of the AND-OR circuit
shown in Figure 1. This circuit contains random pattern resistant
faults and has been used to illustrate basic concepts of weighted
random patterns [15]. To test the stuck-at-zero fault at node y, all
ACM/IEEE International Design Automation Conference, Anaheim, CA, 1997
inputs must be set to 1, and if uniformly distributed pseudo-ran-
dom patterns are applied, the detection probability is 2-32, which
results in an unacceptable test length. If weighted random patterns
are used, setting each input to 1 with the probability of 31 ⁄ 32 , the
32
same fault can be detected with a probability of ( 31 ⁄ 32 ) = avoiding control points in the mission logic as well as external test
0.362, implying relatively short test time. At the same time each
of the stuck-at-one faults on the inputs of the AND gate is
detected with a probability of 1 ⁄ 32 ⋅ ( 31 ⁄ 32 )31 = 0.01168, which
means that on average 86 vectors are required to detect it. How-
ever, the stuck-at-one fault at the output z requires the comple-
mentary weight 1 ⁄ 32 , and to ensure a complete test of the circuit,
the two different weights have to be stored for each circuit input.
p0 1 1 1 … 1 1 p1 0 0 0 … 0 0
x1
...
y 0 1 1 … 1 1 1 0 0 … 0 0
...
x32 1 0 1 … 1 1 0 1 0 … 0 0
T0
...
z 1 1 1 … 0 1 0 0 0 … 1 0
1 1 1 … 1 0 0 0 0 … 0 1
Figure 1: 32-input AND-OR circuit and it’s test set.
On the other hand, a complete test is provided by the
vectors shown in Figure 1 which exhibit a high degree of regular-
ity. The test set is composed of two parts T0 and T1, each of which
is characterized by a basic pattern p0 and p1, respectively, being
referred to as the parent patterns. The remaining patterns Ti \ {pi},
i = 1, 2, can be derived from the parent pi by complementing a sin-
gle bit position and are therefore called the children of pi. Further-
more, p1 is obtained by complementing p0. A proper exploitation
of this regular structure allows a very simple scan-based BIST as
shown in Figure 2. To obtain the targeted parent pattern p0 of Fig-
ure 1, a test point is inserted into the scan chain, such that during
scan-in the constant value “1” is available at the input of the scan
cell corresponding to x1. Because of the structure of the test set the
approach can rely on a “predict & correct” scheme for the remain-
ing patterns. The exceptions from the parent p0 are generated by a
simple hardware unit and no further storage effort is required.
c0 x1 x32
c1
c0 c1 mode
exception
comparator
pattern X 1 shift “1”
counter 0 0 shift “0”
shift 1 0 shift scan chain
counter
Figure 2: Scan-based BIST for the circuit of Figure 1.
Moreover, randomizing the generation of the children
can further simplify the BIST hardware while retaining a high
fault coverage with a relatively small number of patterns. If each
bit of child is flipped from p1(p0) with probability α = 1 ⁄ 32 , then
the probability to generate a particular child within Hamming dis-
tance 1 from the parent cube p1(p0) is given by 1 ⁄ 32 ⋅ ( 31 ⁄ 32 )31 =
0.01168, and on the average 348 random children provide all pat-
terns within Hamming distance 1. The BIST implementation can
be easily generalized to deal with arbitrary parent patterns. If
inversions between scan cells are use appropriately, then any given
pattern p and its complement p can be “hardwired” in the scan
chain.
This example illustrates two important properties of
complete test sets for many non-trivial circuits. First, there is a
small number of clusters, each characterized by a parent cube (or
center) which has a large number of highly effective test vectors in
its close vicinity. Second, there is a great deal of regularity
between the centers.
2
3 The Star Test Principle
The objective of the proposed approach is to develop a
scan-based BIST guaranteeing a very high fault coverage while
data storage. Furthermore, the complexity of the BIST pattern
generator should not depend on the circuit size. The presented
solution assumes that a single scan chain will be inserted and that
there are no restrictions with respect to the ordering of the cells.
Also, it is assumed that the scan cells can be connected with arbi-
trary inversions between them. In this scenario, the randomized
pattern generation scheme of section 2 is adapted as follows:
ATPG is used to determine a few powerful parent cubes which can
be efficiently combined with randomly derived children. The rela-
tions between parent cubes will be exploited to regenerate the
whole set of parents from one basic cube encoded in the scan
T1
chain. The BIST implementation will then rely on an appropriate
scan ordering, interscan test points, the use of inversions between
cells and an exception generator.
The proposed strategy of pattern generation will be
referred to as star test and is defined more precisely as follows: A
test pattern c, which is generated from a pattern t by randomly
inverting the components of t with probability α, is called a type α
(random) child of t. The average Hamming distance between an
n-bit test pattern t and its type α children is n·α, and therefore a set
T*(t, α, nc) of nc type α children is called a star test around t with
nc type α children. Finally, a test set T is called a star test, if it is
obtained as the union of subsets P, T1, …, Tk, where P = {p1, …,
pk} is a set of deterministic cubes and for each i, i = 1, …, k, Ti
consists of one or more star tests around pi.
To elucidate the high fault detection potential of star
tests, Figure 3 shows the results of an empirical analysis per-
formed for the benchmark circuit s38417 [3]. In this experiment
ATPG was used to generate a compact test set with 70 cubes for
the random pattern resistant faults remaining after 32K pseudo-
random patterns. Each of the 70 cubes served as parent of 2K chil-
dren of type 0.5 and 2K children of type 0.25. First, 4K of ordi-
nary pseudo-random patterns were applied and resulted in 89.34%
coverage, each parent on average covers an additional 1.04% to
90.38% (light bars). When each parent with its 4K children were
applied, they yield average 96.34% coverage (dark bars). In other
words, 4K of the vectors derived from a parent cover 5.96% more
faults than 4K of pseudo-random patterns.
98 Fault efficiency
97
96
96.34
95
94
93
92
91
90.38
90
89.34.
89
Figure 3: Fault efficiency of star tests compared to
conventional pseudo-random patterns for circuit s38417.
The results clearly show that the concept of generating
stars around the deterministic cubes is very powerful. The star
ACM/IEEE International Design Automation Conference, Anaheim, CA, 1997 3

tests were able to detect a large portion of faults that were neither
covered by the same number of pseudo-random patterns nor by
the parent deterministic pattern. Furthermore, since only a single
test cube together with its children can already provide more than
97% fault efficiency, it is very likely that a few clusters are suffi-
cient to ensure complete or very high fault coverage. Figure 4
shows the ideal structure of a complete star test.
center of parents
parents children
To reproduce this rectangle during BIST the simple
hardware structure sketched in Figure 6 is sufficient. The back-
ground pattern (1, 1, 1, 0) is “stored” by introducing an inversion
between the last two scan cells and by inserting a test point pro-
viding a constant “1” (as explained in section 5, the required con-
stant can always be taken from the preceding scan cell). The
“envelop” signal ENV_4 ensures that this control point can only
be activated during the appropriate shift cycles. Generally, if the
scan section to be loaded by this control point has length n and the
rectangle corresponds to scan cells k through l, then the envelop
signal must be turned on during shift cycles (n+1-l) through (n+1-
k). The actual pattern to be loaded is determined by the waveform
signal WV_4 which combines the envelop with the signal EQU
generating the desired exceptions. The exact timing of both sig-
nals is shown in the included diagram.

Figure 4: Structure of a star test. scan cells scan cells

The test set is hierarchically composed of two levels of envelop 0110
“stars”. The first level star consists of several parent patterns, each generator ENV_4 1010
WF_4
of which is obtained by ATPG, and one virtual center p0 which is LoadSC EQU 1100
2 1 0 1111
DecSC shift
determined by the regularity analysis described in section 4. Each counter
2 comparator
of the parent cubes then forms the center of a second level star LoadWC
2 1 0 2
with children characterized by their flipping probability α. IncWC waveform
counter
ENV_4
WF_4 (waveform counter = 0)
4 Regularities and Basic Hardware Elements WF_4 (waveform counter = 1)
WF_4 (waveform counter = 2)
In this section the correspondence between regular WF_4 (waveform counter = 3)
structures in the star tests and the components of an efficient scan-
based BIST implementation will be described. Furthermore, it
end of scan_in shift
will be explained how these structures can be extracted from a
given test set. Since our experiments demonstrate that four deter- Figure 6: Hardware and timing diagram for a regular
ministic parents are sufficient to achieve very high fault coverage, rectangle of size four.
the pattern generator described in this section will focus on at
Another type of submatrix in P allowing a simple BIST
most four parent patterns.
implementation is one whose rows can be partitioned into a regu-
a) Generation of parent cubes lar rectangle and rows representing the inverted background of the
regular part as illustrated in Figure 7.
To study the relations between the parent cubes, the set
P is stored as an m × n-matrix with rows corresponding to test
cubes and columns corresponding to the inputs of the combina- … 0 1 1 … 1 1 1 background
tional part of the circuit. Possible entries are “0”, “1” or “X” … 1 0 1 …
- . .
(don’t care). The proposed technique identifies columns and sub- . - . . background value
… 1 1 0 … . . -
matrices in the matrix P which can be reproduced from one basic - complement of
… 0 0 0 … - - -
cube using simple hardware elements. For this purpose the col- background value
umns of P are classified into don’t care, monotonic, regular and original parent cubes rectangle characteristics
random columns as explained below.
Figure 7: Semi-regular rectangle.
Don’t care columns only contain the “X”-entries and
therefore pose no encoding problem. Monotonic zero (one) col- To regenerate such submatrices, which are also referred
umns are defined as columns with all entries being “0” (“1”) or to as semi-regular rectangles, only a small modification must be
“X” and can be trivially derived from a single cube with the corre- added to the architecture of Figure 6 which will be shown later in
sponding entry “0” (“1”). If all entries of a column except one are Figure 11 as part of the complete architecture.
“0” (“1”) or “X”, this column is referred to as regular column with
To implement several rectangles their backgrounds can
the background value “0” (“1”), and submatrices consisting of
be combined to one large background vector, and one control
several adjacent regular columns, such that the exceptions are
point is sufficient to reproduce this vector during BIST. The hard-
located on the main diagonal are called regular rectangles. Figure
ware to generate envelop and waveform signals must be modified
5 shows a regular rectangle with background (1, 1, 1, 0) as an
accordingly. In general, there is a trade-off between the complex-
example.
ity of the hardware necessary to drive one control point and the
number of control points inserted. If only rectangles of the same
1 1 1 0 background width are combined, then the hardware can be kept simple and the
… 0 1 1 0 …
- . . . overall costs low.
… 1 0 1 0 … . background value
. - . .
… 1 1 0 0 … - complement of Rectangles of different widths can be adjusted by insert-
. . - . background value
… 1 1 1 1 … ing additional don’t care columns. As an example Figure 8 shows
. . . -
original parent cubes
the BIST scheme and the timing diagram for the control signals of
rectangle characteristics
four regular rectangles, each of width four. The diagram is similar
Figure 5: Regular rectangle. to the one shown for a single rectangle on Figure 6, except that the
ACM/IEEE International Design Automation Conference, Anaheim, CA, 1997 4

envelop signal ENV_16 is enabled for a period of 4·4 = 16 clock Instead of giving the exact description of the algorithm,
cycles and the waveforms repeat periodically. To accomplish this we show an example to demonstrate the analysis procedures. In
timing, the comparator has only the two least significant bits of the the first step (cf. Figure 9) the columns are grouped into the five
shift counter and the waveform counter (WC) as inputs. types as defined before: regular, semi-regular, monotonic, don’t
care and random. After collecting this information, the regular
It is certain to define other regular structures which also
columns are rearranged to form regular rectangles (cf. Figure 10).
lead to a relatively simple BIST hardware. Within the framework
Don’t cares in monotonic and in don’t care columns may be
of this paper, however, we restrict ourselves to the regular and
changed to “0” or “1” to obtain additional regular columns needed
semi-regular rectangles introduced above. Columns of the matrix
for the completion of regular rectangles. Also, don’t care entries in
P which do not fall into the category of monotonic, don’t care,
the regular columns are assigned to the corresponding background
regular columns or are not contained in semi-regular rectangles
values. Similarly, semi-regular rectangles are built making use of
are called random columns. According to our empirical experi-
don’t care and monotonic columns. The quality of the result may
ence (cf. section 7), however, in many cases three or four parent
depend on the number of available don’t care columns and the dis-
cubes are sufficient, and in this case random columns do not
tribution of don’t cares in monotonic columns. For all the circuits
occur. Due to the paper size limitations, we give the following
we analyzed the number of don’t care columns and monotonic
property without a proof.
columns are sufficient to provide good results (cf. section 7).
scan cells scan cells
Step2:
WF_4x4 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 Rearrange the order of columns and properly insert don’t care columns among
ENV_16
1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 (semi-) regular columns, such that they can form (semi-) regular rectangles.
EQU 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1
1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 col k.heo..iq..nl.jm..bdrsacfgh........
p1 0X1X0XX00XX01X01XXXX001XX11XXXXXXXX
ENV_16
p2 1X101XX01XX00X00XXXX00XX111XXXXXXXX
WF_4x4 (WC = 0)
p3 1X001XX01XX00X10XXXX00XX111XXXXXXXX
WF_4x4 (WC = 1) p4 1X111XX11XX11X11XX0000X1111XXXXXXXX
WF_4x4 (WC = 2)
WF_4x4 (WC = 3)
Step3:
Replace the don’t cares in (semi) regular rectangles and monotonic columns
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value of shift counter by proper values.

Figure 8: The control logic and timing diagram of four bg 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 X XXXXXXX

p1 - . . . - . . . - . . . - . . - . . . . . . . . . . . . .......
compatible regular rectangles p2 . - . . . - . . . - . . . - . . - . . . . . . . . . . . .......
p3 . . - . . . - . . . - . . . - . . - . . . . . . . . . . .......
Property If the matrix P does not have more than four rows and p4 . . . - . . . - . . . - - - - - - - . . . . . . . . . . .......
the number of don’t care columns is sufficiently high, then a sub-
set of columns can be partitioned into regular and semi-regular . center value
- complement of
rectangles and the remaining columns are either monotonic or semi-regular
background value
don’t care columns. regular rectangles
rectangles

b) Regularity analysis for parent cubes
In general, the matrix P produced by ATPG does not
necessarily allow an optimal partitioning into (semi-) regular,
monotonic, don’t care and random columns. However, since it is
assumed that the scan order can be freely determined, it is possible
to reorder the columns. For combinational tests the patterns can be
applied in an arbitrary order, which also allows row permutations.
Furthermore, don’t care columns can be inserted to build regular
or semi-regular rectangles. To determine the best row and column
order we propose a heuristic algorithm proceeding in three steps
(cf. Figures 9 and 10).
Original patterns:
col. . . . . . . a . b c . . . . . . d e f g h i j k l m n o p q r s . .
p1 X X X X X X X 1 X X X X X X X X X X X X 1 1 0 0 0 1 1 0 0 1 0 0 0 X X
p2 X X X X X X X X X X X X X X X X X X 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 X X
p3 X X X X X X X X X X X X X X X X X X 0 1 1 0 0 1 1 0 0 0 1 1 1 0 0 X X
p4 X X X X X X X X X 0 1 X X X X X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 X X
Step1:
Classify the columns into five different types: regular, semi-regular,
monotonic 0’s, monotonic 1’s and don’t care columns.
col e i n h k o q j l m b d r s a c f g p . . . . . . . . . . . . . . . .
p1 X 0 0 1 0 0 0 0 1 1 X X 0 0 1 X X 1 1 X X X X X X X X X X X X X X X X
p2 0 0 0 1 1 1 1 0 0 0 X X 0 0 X X 1 1 1 X X X X X X X X X X X X X X X X
p3 0 0 0 0 1 1 1 1 0 0 X X 0 0 X X 1 1 1 X X X X X X X X X X X X X X X X
p4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 X 1 1 1 1 X X X X X X X X X X X X X X X X
regular semi 0’s 1’s Don’t care
Figure 9: Original parent cubes and step 1 of the regularity
analysis for s1238.
Figure 10: Steps 2 and 3 of the regularity analysis for circuit
s1238.
5 The Complete Architecture
To give a complete description of the STAR-BIST tech-
nique, we use the test cubes of the previous example and show
how the scan chain and the control signals are connected and syn-
chronized. The scan chain is ordered such that it starts with cells
corresponding to regular rectangles. These are followed by cells
corresponding to semi-regular rectangles, monotonic and don’t
care columns as shown in Figure 11.
The parent patterns determined by the regularity analy-
sis of Figure 10 have been rearranged such that all rectangles have
width four and can share the same waveform signal. Furthermore,
an additional semi-regular rectangle has been constructed from
don’t cares columns, which makes it possible to combine three
regular and three semi-regular rectangles to groups being driven
by the same waveform signal WF_4×3. This extra adjustment
reduces the area overhead, but will be possible only if the number
of don’t care or compatible monotonic cells is large enough,
which is true for this case. The first control point used to generate
the regular columns is inserted at the first scan cell to guarantee a
constant scan-in value (“1” in the example). The scan cells are
connected together by properly switching between positive and
negative polarity to form the center pattern. The waveform signal
for the regular rectangles (WF_4×3) generates the parent values
when Child_EN is “0”. When Child_EN is “1”, the n-input AND
ACM/IEEE International Design Automation Conference, Anaheim, CA, 1997 5

gate fed by the LFSR synthsizes the output signal “1” with proba- Fhard and that during the actual BIST no pseudo-random patterns
bility α = 2-n to generate type α children. will be applied. If F hard ≠ ∅ , the parameters nc and k for the star
test are selected, where k denotes the number of different types of
Parent cubes: children generated around each cube and nc is the number of chil-
bg 111011101110000000000000000011111XX dren to be applied of each type. Since patterns generated for ran-
p1 011001100110100010001000000011111XX dom pattern resistant fault usually are very efficient, the set Fhard
p2 101010101010010001000100000011111XX
p3
p4
110011001100001000100010000011111XX
111111111111111111111111000011111XX
is used as target fault list Ftarget during the first iteration of the
ATPG-loop (steps 3 through 6) which follows to determine the set
STAR-BIST architecture: of parent cubes P.
semi-regular monotonic don’t care
cells cells cells In each iteration of this loop a complete test set T for
Ftarget is generated by ATPG, and since we try to find very power-
regular cells ful parent cubes while retaining a high degree of freedom for the
WF_4x3 remaining synthesis steps, an ATPG tool is used, which can per-
form dynamic pattern compaction and minimize the number of
I_EN specified bits. For each cube in T don’t cares entries are then fixed
to the majority value found in the corresponding components of
Child_EN the remaining cubes. To find the best flipping probabilities α1, …,
αk a small sample from T can be used and fault simulated together
from LFSR from LFSR with different types of children. In general, the best values found
control point for 1 1
control point for in our experiments ranged from ----- - to --- . The complexity of the
regular columns semi-regular columns 32 2
algorithm can be reduced by fixing the values for α1, …, αk and
Figure 11: The final scan chain and control logic for circuit skipping step 4 in the following iterations. Our experiments
s1238. showed only slightly different results when doing so.
The next control point used to generated semi-regular
columns is inserted between the first semi-regular cell and the last start
step 3 parent
regular cell. Since the background value of the last regular cell is
circuit C patterns
“0”, which indicates that the constant “0” is shifted into the semi- step 1 fault list F determine test
P
regular cells when the first control point is disabled, an OR gate is set T for Ftarget
simulate N pseudo- step 7
chosen and the waveform signal (WF_4×3) is complemented to by ATPG
random patterns regularity
ensure the controlling value being generated at the conflict posi- to determine Fhard step 4 analysis of P
tions. To guarantee that the last regular cell will always shift the select flipping
required constant value to the semi-regular cells during the scan-in yes rates α1, …, αk step 8
mode, the regular cells need to be initialized to this value, which yes
Fhard = {}? no step 5 synthesize
can be done by applying extra shift clocks when scanning in the scan chain and
Ftarget = {}
first pattern. This initialization does not make the test application find p ∈ T with control points
no or
of our technique longer than for a traditional scan-based BIST, |P| = pmax? best star tests
around p
since the number of clock cycles for scan-in generally is smaller end
for the proposed technique than the traditional scan-based BIST. step 2
step 6
end
Other logic of the control point is similar to the first one, except set P := P ∪ {p} and
select nc, k,
one more signal I_EN is added to inverse the scan_in value at the set P := {},
update Ftarget
last phase. Ftarget := Fhard

6 Synthesis Algorithm
To synthesize the BIST hardware for a star test as
described in the previous sections two tasks have to be solved.
Firstly, a set P of parent cubes and flipping probabilities α1, …, αk
must be determined, such that the resulting star test with nc chil-
dren of type α1, …, αk around each parent achieves a sufficiently
high fault coverage. To support a hardware optimal BIST imple-
mentation the number of parent cubes should be as small as possi-
ble, preferably not exceeding four, because in this case a
partitioning into regular structures can be guaranteed (cf. section
4). Secondly, for the set of parents P an appropriate scan ordering
must be found allowing to partition the columns of P into (semi-)
regular rectangles and monotonic and don’t columns. In doing so,
the number of required control points and different envelop and
waveform generators is to be minimized. To solve these tasks the
algorithm shown in Figure 12 has been developed, which takes as
input the combinational part of the target circuit C and a fault list
F (if possible all redundant faults are removed from F).
The algorithm starts with fault simulating N pseudo-ran-
dom patterns to identify the random pattern resistant faults Fhard
⊂ F. It should be noted that this step is only performed to calculate
Figure 12: Flow chart of the STAR-BIST synthesis algorithm.
After selecting the children’s types, each cube in T
together with its k·nc children is fault simulated against the set
Ftarget (in the first iteration against the entire fault set F), and the
best cube p is selected and added to P. Then the target fault list is
updated to all faults in F which are not covered by the star test
determined so far. Steps 3 to 6 are repeated until a sufficiently
high fault coverage is reached or the number of parent cubes
reaches the user-defined limit pmax. As final step, the regularity
analysis explained in section 4 is performed for P, which decides
the configuration of the scan chain, the control points and the con-
trol signals as described in the previous section.
7 Experimental Results
The synthesis algorithm of section 6 has been applied to
the random pattern resistant circuits of the ISCAS’85 and ISCAS’
89 benchmark suite. Table 1 shows the results for a four phase star
test (pmax = 4) with 2K type 0.25 and 2K type 0.5 children in each
phase. To characterize the circuits in columns 2 through 4 the
number of collapsed irredundant faults and the fault efficiency FE
are given. The columns titled ϕ1 to ϕ4 show the fault efficiency
ACM/IEEE International Design Automation Conference, Anaheim, CA, 1997 6

FE achieved after each phase of the star test. Note that the star test [2] F. Brglez and H. Fujiwara: A Neutral Netlist of 10 Combina-
does not use pseudo-random patterns in advance and targets the tional Benchmark Designs and a Special Translator in For-
entire set of irredundant faults. The results show that the selected tran; IEEE Int. Symp. on Circuits and Systems (ISCAS),
types of children 0.5 and 0.25 provide a high quality test for all the Kyoto, 1985
circuits. In general, using only the conflict rate 0.25 resulted in a [3] F. Brglez, D. Bryan and K. Kozminski: Combinational Pro-
fairly good coverage in the cases we investigated. The type 0.5 files of Sequential Benchmark Circuits; Proc. IEEE Int.
children were selected additionally to cover the easy to detect Symp. on Circuits and Systems, 1989, pp. 1929-1934
faults, because these patterns can be considered as equivalent to
equi-probable pseudo-random patterns. In fact, our results tell us [4] K.-T. Cheng, C.-J. Lin: Timing-Driven Test Point Insertion
that these type 0.5 children work even better than pseudo-random for Full-Scan and Partial-Scan BIST; Proc. IEEE Int. Test
patterns in detecting the easy faults. Conf., Washington, DC, 1995, pp. 506-514
[5] M. Chatterjee and D. K. Pradhan: A New Pattern Biasing
Technique for BIST; Proc. of VLSI Test Symp., 1995, pp.
Table 1: Results for a four-phase STAR-BIST (2048 children 417-425
of type 0.25 and 2048 children of type 0.5 are applied in each
phase) [6] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B.
#target 32Kp.r.
Courtois: Built-in Test for Circuits with Scan Based on
Circuit ϕ1 ϕ2 ϕ3 ϕ4 Reseeding of Multiple-Polynomial Linear Feedback Shift
faults patterns
c2670 2478 97.49% 97.22% 99.27% 99.88% 99.96%
Registers; IEEE Trans. on Computers, Vol. 44, No.2, Febru-
c7552 7417 96.00% 98.50% 99.54% 99.72% 99.81%
ary 1995, pp. 223-233
s838.1 933 80.72% 80.72% 97.32% 99.25% 99.58% [7] V. S. Iyengar, D. Brand: Synthesis of Pseudo-Random Pat-
s5378 4681 99.51% 98.72% 99.72% 99.96% 100% tern Testable Designs; Proc. IEEE Int. Test Conf., Washing-
s9234 6641 90.84% 93.92% 98.67% 99.50% 99.87% ton, DC, 1989, pp. 501-508
s13207 10340 97.93% 95.23% 98.90% 99.94% 100% [8] B. Koenemann: LFSR-Coded Test Patterns for Scan Designs;
s15850 11564 95.44% 97.57% 99.89% 99.99% 100% Proc. Europ. Test Conf., Munich 1991, pp. 237-242
s38417 33039 95.68% 98.09% 99.46% 99.79% 99.94%
[9] S. Pateras, J. Rajski: Cube-Contained Random Patterns and
s38584 34945 97.49% 96.97% 99.60% 99.93% 99.99%
their Application to the Complete Testing of Synthesized
Though table 1 shows the results of four phases, the Multi-level Circuits; Proc. IEEE Int. Test Conf., Nashville,
fault coverages are already very high after three phases, so the last 1991, pp. 473-482
phase can be eliminated to further reduce one control point (no
[10] J. Rajski: Spherical pseudo-random pattern testing, apparatus
semi-regular rectangles in three phases star test parents). The
and method; USA patent application, 1996
length of LFSR used to generate the probability α is 32 bits.
[11] Y. Savaria, M. Yousef, B. Kaminska, M. Koudil: Automatic
Test Point Insertion for Pseudo-Random Testing, Proc. Int.
8 Conclusions Symp. on Circuits and Systems, 1991, pp. 1960-1963
This paper presents a novel scan-based BIST technique [12] B. H. Seiss, P. M. Trouborst, M. H. Schulz: Test Point Inser-
which gives high fault coverage and no performance degradation tion for Scan-Based BIST; Proc. Europ. Test Conf., Munich
in addition to full scan and low area overhead. The test application 1991, pp. 253-262
time is also reduced since the number of the test cubes is signifi- [13] N. Tamarapalli, J. Rajski: Constructive Multi-Phase Test
cantly smaller than in other existing techniques. The other benefit Point Insertion for Scan-Based BIST; Proc. IEEE Int. Test
of STARBIST is that the technique does not modify the mission Conf., Washington, DC, 1996, pp. 649-658
logic, so no logic resynthesis is required. The control point(s) are
[14] N. A. Touba and E. J. McCluskey: Synthesis of Mapping
added between the scan cells, not inside the mission logic as the
Logic for Generating Transformed Pseudo-Random Patterns
current test point insertion techniques do. Though our experiments
for BIST; Proc. IEEE Int. Test Conf., Washington, DC, 1995,
are based on the stuck at fault model, this technique could be
pp. 674-682
applied to other fault models used for IDDQ test, memory fault
test, and delay fault test. [15] J. A. Waicukauski, E. Lindbloom and O. Forlenza: WRP: A
Method for Generating Weighted Random Patterns; in: IBM
Journ. of Research and Development, Vol. 33, No. 2, March
9 Acknowledgment 1989, pp. 149-161
The authors are very grateful to Rob Thompson for the [16] M. J. Y. Williams and J. B. Angell: Enhancing Testability of
helps of ATPG in the experiments. The insightful comments from Large Scale Integrated Circuits Via Test Points and Addi-
Chien-Chung Tsai and the helps from Nagesh Tamarapalli are also tional Logic; IEEE Trans. on Computers, vol. C-22, 1973, pp.
highly appreciated. 46-60
[17] H.-J. Wunderlich: Self Test Using Unequiprobable Random
References Patterns; Proc. IEEE 17th Int. Symp. on Fault-Tolerant Com-
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