Electronic Design Automation

Lec10 Floor Planning, Placement

By: Dr. Eman El Mandouh
So, what’s next? From Logical To Physical Design

We’ve basically finished the Front-End of the design process

and we will now start the Back-End

➢ Move between tools with a logical approach to ones with a

physical approach to design implementation.

➢ Then, Drawing up a floorplan.

➢ Place our gates considering congestion and timing.

➢ With our flip-flops in place, so designing a clock-tree can be done

➢ And finally, we can route all our nets, according to DRCs, timing,
noise, etc.

➢ Before tape out, we will clean things up, verify, etc.

Floor planning Goals and Objectives
➢ Floor planning is a mapping between the logical description (the netlist) and the physical description (the
floorplan).

➢ Find Approximate location of a set of modules that need to be placed on the layout surface.

➢ Aviable region typically considered rectangular.

➢ Modules are also rectangular shape (some exception L-shape)

Goals of floor planning:

➢ Arrange the blocks on a chip.
➢ Decide the location of the External Pins (I/O pads.)
➢ Decide the Power Supply & Ground Planning
➢ location and number of the power pads.
➢ Decide the type of power distribution.
➢ Decide the location and type of clock distribution.

Objectives of floor planning are:

➢ Minimize the chip area (total layout area)
➢ Minimize delay
➢ Minimize routing congestion (Max Route-ability)
Floor Planning Inputs & Outputs
Inputs
➢ Design netlist Area requirements (required)
➢ Power requirements (required)
➢ Timing constraints (required)
➢ Physical Partitioning Information (required)
➢ Die size (required)
➢ I/O placement (optional)
➢ Macro placement information (optional)

Outputs
➢ Die/block Area
➢ I/Os Placed
➢ Macros Placed
➢ Power Grid Designed
➢ Power Pre-routing
➢ Standard Cell Placement Areas
Design ready for standard cell placement
 IO Ring
✓ I/O are put as ring and distributed around the chip
✓ I/Os are not scale with the number of wires inside the chip, so they are very
expensive (in terms of area).
✓ I/Os are not only needed for connecting signals to the outside world, but also
to provide power to the chip.
✓ I/O planning is a critical and very central stage in Floor planning the chip.

How do we choose our chip size?

✓ Core Limited : Classic way , lot of Logic, The
Core is very Big

✓ Pad Limited : nowadays , lot of I/O’s many

connections to things outside of chip, many
wasted area inside the chip not used for
logic.
Chip Area Utilization
Utilization refers to the percentage of core area that is taken up by standard cells.
➢ A typical starting utilization might be 70%

High utilization can make it difficult to close a design: Routing congestion,

Local congestion
➢ Can occur with pin-dense cells like multiplexers
➢ Run a quick trial route
to check for routing congestion
Hard Macro Placement
Macros are big cells (IP’s, ROM, RAM)

When placing large macros, we must consider impacts on routing, timing and power.

Usually push them to the sides of the floorplan.

Placement algorithms generally like , perform better, with a single large rectangular placement area.
Place power hungry macros away from the chip center.

After placing hard macros, mark them as FIXED.

Placement Regions
Sometimes, we want to “help” the tool put certain logic in
certain regions or cluster them together.

Place and Route tools define several types of placement

regions:

➢ Soft guide –try to cluster these cells together without a defined area.

➢ Guide–try to place the cells in the defined area.

➢ Region–must place the cells in the defined area, but other cells may
also be placed there.

➢ Fence–must place the cells in the defined area and keep out all other
cells.
Placement Blockages and Halos
Placement blockage halos are areas that the tools should not place any cells.

These, too, have several types:

Hard Blockage –no cells can be placed inside.

Soft Blockage –cannot be used during placement but

may be used during optimization add repeater, buffers

Partial Blockage –an area with lower utilization.

Halo(padding) –an area outside a macro that should be

kept clear of standard cells.
Multiple Power Domain Design
Define power domains
➢ Create power domain names
➢ List of cells connected to VDD1, VDD2, GND1,…
➢ Draw the power domains

Place macros: Take into account:

➢ Routing congestion
➢ Orientation
➢ Manual usually better then Auto

Place switches
For the power down domains
Power Consumption and Reliability
IR Drop : The drop in supply voltage over
the length of the supply line
A resistance matrix of the power grid is constructed
The average current of each gate is considered
The matrix is solved for the current at each node, to
determine the IR-drop

EM: Electromigration refers to the gradual

displacement of the metal atoms of a conductor
as a result of the current flowing through that
conductor.

Can result in catastrophic failure do to either

Open: void on a single wire
Short: bridging between to wires
Power and Ground Routing
Each standard cell or macro has power and ground signals,
i.e., VDD(power) and GND(ground): They need to be connected as
well

Power/Ground mesh will allow multiple paths from P/G

sources to destinations

You can imagine that they are HUGE NETWORKS!

Guidelines for a good floorplan
Hierarchal Top Level Designs vs Flat Top Design Approach

Flat Top Level

Floor Planning

If the
If the design is too big, partition it into hierarchies design is
Faster runtime, less memory needed for EDA tools too big, Hierarchal Top
partition Level Floor
it into Planning
hierarchi
es
•Advanta
ges
•Faster
Floor Planning Summary
Initialize Design: Define Verilog netlist, (timing, SDC, extraction, etc.), LEF, IO placement

Specify floorplan: Define floorplan size, aspect ratio, target utilization

Place hard macros

Define regions and blockages: If necessary, define placement regions and placement
blockage

Define Global nets: Tell the tool what the names of the global nets (VDD, GND) are and
what their names are in the IPs.

Create Power Rings: Often rings for VDD, GND are placed around the chip periphery, as
well as around each individual hard IP.

Build Power Grid: Build power stripes on metal layers. Make sure power connects to
hard IPs robustly

Assign Pins: Assign pins to the periphery of the floorplan.

ASIC Placement
✓ We have successfully synthesized our design into a technology mapped gate level netlist.
✓ We have designed a floorplan with pre-placed blocks.
✓ Now we will move into detailed placement of the standard cells.

Placement is the stage of the design flow, during which each instance (standard cell) is given an exact
location.

Inputs:
➢ Netlist of gates and wires.
➢ Floorplan

Output:
➢ Exact Location of each gate.

Goal
➢ able to route (connect all nets)

Is it Hard? Yes
➢ Bad Placement → Much more wire
➢ More Wire : Bigger, Slower Chip
➢ Route will not be able to connect wires or meet timing
ASIC Placement: Simple Random Placer
Simple Model of Chip
✓ Simple Grid (Chess Board Like)
✓ Cells (Gates) go into grid slots
✓ Pins ( Fixed at Edges)
Simple Model of Gates
✓ All Gates are Exactly Same Size
✓ Each grid slot can hold 1 gate

Wire in Layout is Called “Net”

✓ Whole set of gates + wires → netlist
✓ Nets Categorized By how many
things (points) connected to it
What Does a Placer Do?
✓ Optimize the ability of the Router to connect all nets
✓ By Minimize expected wirelength : for each wire in design estimate the
expected length of routed wire
✓ Minimize this Cost Function (Objective)

✓ Placer solves for gate locations to minimize this cost Function.

ASIC Placement: Simple Random Placer
Wirelength Estimation : HPWL
ASIC Placement: Simple Random Placer
Half Permitter Wirelength Estimation : HPWL
ASIC Placement: Simple Random Placer Algorithm

First Step : HPWL = HPWL(i) + HPWL(j) +

HPWL(k)
= (4-1)+(5-3) + ((3-2)+(3-1) + (4-2)+(5-1)
= 5+ 3+6 = 14

After Swap Step : HPWL = HPWL(i) + HPWL(j)

+ HPWL(k)
= (4-1)+(5-1) + ((3-2)+(3-1) + (4-3)+(5-3)
= 7 + 3 + 3 = 13

3
Practical Placers Using → Analytical Placers Approach
Question:
➢ Can we write an equation whose minimum is the placement?
➢ If we have a cost function (such as wirelength) that is a function of the gate coordinates
➢ Then we could find the minimum of f and this would be our optimal placement!

Does This Approach Work ? YES!

➢ All modern placers are based on analytical placement.
➢ We need to write the cost function in a mathematically friendly way.
➢ Then, we can just differentiate and equate to 0!
Analytical Placement Cost Function
Instead of HPWL, let’s define a new wirelength model: Quadratic wirelength
Analytical Placement Cost Function
What about a k-point net (k>2)?
One last point:
•Assume that gates are dimensionless points.
Analytical Placers Approach
Example of quadratic wirelength calculation:
Analytical Placers Approach
Example of quadratic wirelength calculation:
Analytical Placement Calculation
Now that we have an analytic expression for the cost
function, we can use basic calculus to minimize it!
Analytical Placement Calculation
Placement Results
Quadratic Placement Problem
What does a real quadratic placement look like?
All the gates want to be in the same place!

How can we solve this?

Recursive Partitioning!
Recursive Partitioning : How to Partition
Recursive Partitioning : How to Contain
Recursive Partitioning : How to Contain
Small Recursive Partitioning Example
Small Recursive Partitioning Example
Small Partitioning Example
Small Partitioning Example