An FPGA Implementation of a Soft-in Soft-out Decoder for Block Codes
Abdul-Rafeeq Abdul-Shakoor, Ron Kerr, John Lodge, and Valek Szwarc
Communications Research Centre Canada
3701 Carling Ave., Box 11490, Station H
Ottawa, Ontario, K2H 8S2, Canada.
ABSTRACT
This paper presents an FPGA implementation of the Vector
SISO algorithm for the (64, 57) extended Hamming code
(EH) and (64, 51) extended Bose, Chaudhri, and
Hocquenghem code (EBCH). The decoder architecture is
defined in VHDL and the circuit is implemented on a Xilinx
XC2VP100-1704ff–5 FPGA device. To achieve the required
throughput, a pipelined data path architecture operating off a
master clock was selected. To reduce gate count, the
dynamic range of intermediate results was limited through
use of saturation arithmetic. The decoder functionality was
verified by means of a test bench that compared the decoded
bit stream with error free transmitted signals. SISO decoder
design choices that impact the bit error rate (BER) are also
presented.
Keywords: Vector SISO decoder, BCH and EH codes.
1. INTRODUCTION
The Bose, Chaudhuri, and Hocquenghem (BCH) class of
linear block codes has been effectively used to correct for
channel induced errors in wireless communications.
Throughput, power, and gate count considerations dictate
that, for efficient realization of decoders, both algorithm
and architecture need to be optimized to meet design and
performance requirements. Recently a number of soft-
decision decoding algorithms [1-7] have been proposed for
decoding linear block codes. The optimal soft-in soft-out
(SISO) decoder is based upon maximum a posteriori
probability (APP). A suboptimal SISO approach that is
numerically less complex is the max-log-APP algorithm [8].
However, full max-log-APP decoding is computationally
too intensive to be practical for many block codes. Here, we
present a design and implementation of an algorithm for
linear block code decoding [4] that is closely related to the
max-log-APP algorithm but of lower realization complexity.
The application of the algorithm can be extended to the
decoding of more powerful composite code structures such
as Turbo Product Codes (TPC) where the overall code
structure is decoded in an iterative manner based on SISO
decoding of the individual constituent codes.
2. BACKGROUND
The Vector SISO algorithm has been applied to a number of
linear block codes, both binary [4, 10] and non-binary [9].
Here FPGA implementation of a binary version will be
presented. For the sake of completeness, some of the details
of the algorithm provided in [4] will be presented here.
Here we consider general linear codes for which
codewords can be generated from c = iG, where i is a row
vector of k information bits, c is a row n-vector of coded bits
and G is a k x n generator matrix. A parity check matrix,
H, is any (n-k) x n matrix of rank (n-k) for which GHT = 0.
A parity check matrix is referred to as being in pseudo-
systematic form relative to a set of n-k bit positions if, by
moving the corresponding n-k columns and appropriately
ordering them, the matrix can be put into form H = [ I H’],
where I denotes the identity matrix. If we are given bit
values for the k positions corresponding to the non-identity
portion of the pseudo-systematic parity check matrix, it is
easy to form the entire codeword by selecting the remaining
n-k bits to satisfy the parity constraints. We refer to forming
codewords in this manner as “recoding”.
The Vector SISO algorithm uses a reliability vector based
on the best decision bits, vbest, and the soft input values to
the decoder y. The vector y is the input to the decoder
where the sign of the value provides a representation of the
logical value and the magnitude is assumed to be
proportional to the reliability of the sample. Here, decision
bits are bipolar values +1 and -1 representing binary ‘0' and
‘1' respectively. The reliability vector is given as the
element-by-element product of the two vectors, vbest and y.
In this implementation, we have taken the best decision
vector at the input to be the sign of the soft-input values y.
Given this assumption, the reliability vector can be
computed by taking the absolute value of the elements of y.
The next step is to modify the current parity check matrix
to a pseudo-systematic form based on n-k least reliable bit
positions. In doing so, we divide the bit positions into two
classes, most-reliable and least-reliable similar to [11]. This
method ensures that the least reliable bit (lrb) positions are
linearly independent. This is accomplished by utilizing row
reduction of the parity check matrix. The algorithm selects
the first parity check equation from the parity check matrix.
In this equation, the algorithm finds the bit position with the
minimum value in the reliability vector corresponding to the
bits involved in the equation. This corresponds to the
position of the least reliable bit for this equation. The
algorithm then carries out row reduction to remove the
effect of this position from any of the other n-k-1 parity
equations in the parity check matrix. The algorithm then
moves to the next unprocessed equation and repeats the
process of finding the least reliable bit position and
removing it from the other equations. This process
continues until all n-k equations have been processed. This
step is referred to as the row reduction step and, after it is
finished, the parity check matrix is in pseudo-systematic
form relative to the n-k lrb positions.
The parity check matrix is used to form extrinsic
information for the most-reliable bits (mrb). An
approximation for the extrinsic information, for a binary
single parity check equation, consists of the minimum
magnitude within the equation with the sign that satisfies
the parity equation [12]. Extrinsic information for an mrb in
the jth position of the codeword, is the sum of the extrinsic
values from all of the parity equations in which it is
involved, i.e.
e j = ∑ d 'j ,m y m (1)
where e j is the extrinsic value for the jth position in the
codeword, d 'j ,m is the decision for jth bit from equation m
that satisfies the parity equation constraints, and y m is the
minimum value found for equation m.
The soft-input information is combined with the extrinsic
information for the mrb positions. A decision vector is
based on the signs of the composite information vector. The
k decisions on the mrb positions are used to recode the lrb
positions.
At this point the current decision bits on the mrb and the
recoded lrb bits form a new best decision vector based on
the code information and the soft-input values.
The new decision bits and values from the composite
vector are used to create the soft-output information for the
lrb positions. Similar to the computation of the mrb
extrinsic, the lrb extrinsic has the sign that satisfies the
parity equation and a magnitude equal to the minimum
magnitude of the composite information with d’ the
contribution of the lrb value subtracted. In this way, the
soft-output values of the lrb take advantage of the extrinsic
and soft-input values of the mrb positions.
3. SISO ALGORITHM
i) Form an initial “reliability” vector by taking the
absolute values of the elements of y.
ii) Select the n-k linearly independent bit positions that
are the least reliable in the sense that they correspond to the
smallest elements in the reliability vector. We will refer to
these as “least reliable bits” (lrb). Similarly, the remaining k
bit positions are referred to as “most reliable bits” (mrb).
iii) Using row reduction techniques put H into pseudo-
systematic form such that the identity portion of the parity
check matrix corresponds to the lrb. Let d’ denote the
vector of best decisions found to the given point in the
algorithm, where “best” means the code word with the best
metric. Initially, d’ will be the code word obtained by
performing hard decisions on y for the mrb and then using
the pseudo-systematic parity check matrix selecting the lrb
values to satisfy the parity constraints.
iv) Compute the extrinsic information for the mrb. For
the ith mrb, a reasonable approximation to the extrinsic
information is to take the metric difference between the best
decision code word, d’, and the recoding solution with all of
the mrb remaining the same except for the ith position
which is flipped, resulting in code word dj’. Thus, the
extrinsic information from Equation (1) becomes
ˆ
llrie = di′ * ∑ dm′ ym , (2)
m≠i
′ ≠ d m, j '
dm
where each of the indices in the sum, m, corresponds to an
lrb and multiplication by d’i accounts for the possibility that
the ith bit may not be a +1 in the vector of best decisions.
v) Compute the mrb metric differences by summing the
extrinsic information and the intrinsic information and
compare with the signs of the mrb in the current best code
word. If any of the signs differ, then a better code word than
the current best code word has been found. Consequently,
there is a new best code word. If the signs differ in several
locations, the location with the highest magnitude composite
value (intrinsic plus extrinsic) is the one considered (as
flipping this bit position will make the biggest improvement
in the code word metric). If there are no sign differences,
go to STEP vii. Otherwise, form the new best code word by
first changing the sign of the appropriate mrb and then
computing the lrb using recoding.
vi) Form the new reliability vector by performing
element-by-element multiplication between the new best
decision vector and y. Note that the reliability vector is now
a signed vector with the “smallest” elements being negative
(i.e., where the intrinsic information and the “best” decision
differ in sign). Go back to STEP (ii).
vii) Compute the soft outputs for the lrbs. Recall that
each row in the pseudo-systematic parity check matrix
represents a parity equation that includes only a single lrb,
with the remainder of the entries being mrbs. Furthermore,
the magnitude of the composite information (intrinsic plus
extrinsic) for each of the mrbs represents the difference
between the metrics for the best code word and the recoded
code word with the given mrb flipped. Each of these mrb
composite information values are candidates for the
composite information value (with the appropriate sign
adjustment) for the lrb, since it will always be among the
bits whose sign differs between the pair of code words
involved in the metric difference. The best choice is the one
with the smallest magnitude because this is the one with the
best pair of metrics. (one of the pair is always the metric for
the best path d’).
Computational procedures have been developed for all of
the above steps which translate into very efficient
architectures or software realizations for vector processing.
As will be demonstrated by the examples, the basic
algorithm described above performs very well as a SISO
decoder for the constituent codes in a composite turbo-like
code such as a turbo product code [3]. It also performs well
as a soft-in decoder for relatively small distance block codes
such as extended Hamming codes and low-distance BCH
codes. However, its performance is quite sub-optimal for
fairly powerful codes. Some additional processing can be
used to improve the performance for such codes. Here we
describe one ad hoc approach that shows promise.
For codes with a large minimum distance, it is possible to
test d’ to determine with fairly high reliability whether or
not it is the correct code word [4]. This can be done by
comparing the normalized metric (i.e., the inner product of
the code word and the received vector divided by the sum of
the absolute values of the received vector) to a threshold
value. If the threshold is exceeded, then we accept d’ as the
decoded code word. If not, then we do some additional
processing to find a better code word. Given that the basic
algorithm only changes the sign of one mrb at a time, a
possible approach is to change the signs of groups of 2 or
more of the mrbs, perform recoding, and compute the
corresponding metrics. However, the number of possible
combinations grows very quickly for groupings of greater
than 2 bits. Here we take a different approach. If the best
code word found by the basic algorithm is not accepted,
then we subtract a small scaled version of it from the
received vector in order to bias the results away from the
already found solution and repeat the basic algorithm. This
procedure can be repeated until a code word is found that
passes the threshold test or until the maximum number of
allowed attempts is reached.
4. DECODER ARCHITECTURE AND ITS
IMPLEMENTATION
Based on the vector SISO decoding algorithm of Sect. 3,
the hardware decoders for respectively single and double
error correcting EH (64, 57) and EBCH (64, 51) linear
codes are presented here. The decoders process
simultaneously 64 symbol input blocks and with a latency
of 5 clock cycles and outputs a decoded 64 symbol block
every clock cycle. The decoder architecture depicted in Fig.
1 consists of three processing modules identified as the Row
Reduction Block (RRB), Most Reliable Bit Block (MRB),
and Least Reliable Bit Block (LRB). In terms of the
algorithmic description in Sect. 3, the RRB, MRB, and LRB
blocks execute steps (i-iii), (iv-v), and (vi-vii) respectively.
To achieve high throughput, the data path architecture
was fine-tuned to minimize the delay variations in the
pipelined stages. To reduce the gate count, the dynamic
range of the intermediate results was limited through the use
of saturation arithmetic [13]. Thus data corresponding to 64
symbols in a block are simultaneously operated on and
routed between the blocks depicted in Fig. 1. The soft inputs
to the decoder’s RRB section at the B0 bus consist of 8 bits
per symbol for both decoder realizations. The RRB
hardware shown in Fig. 2 operates on the parity check (H)
matrix and, in the process, the soft inputs are stored in a
single register with 8 bits per symbol. Since only positive
numbers or symbol magnitudes need to be forwarded to the
MRB block, the most significant bits (MSB) are truncated
and output bus B1 consists of only 7 bits per symbol
resulting in area savings.
Extrinsic computation in the MRB block depicted in Fig. 3
involves further operation on the updated H-matrix to
compute the most reliable bits. The LRB block in Fig. 4
Soft inputs Soft outputs
RRB MRB LRB
B0 B1 B2 B3
Clock
Fig. 1: SISO decoder block diagram.
computes least reliable bits from the received vector. The
MRB intermediate values increase to 10 bits per symbol in
conformance with Matlab simulation results in Sect. 5 [4].
Hence busses B2 and B3 consist of 10 bits per symbol. The
(N-K) rows of the N column H matrix are referred to as the
parity check equations in current algorithm implementation.
The received N symbol codeword processed along with H
matrix is also referred to as a soft input. From the soft inputs
and 1st parity equation (i.e 1st row of H matrix), a most
reliable bit is generated and the most reliable bit position is
found and the parity check matrix is updated with
Soft inputs
y => N symbol register
y
| y| => N symbol buffer register (i)
Parity check (H) matrix row 1 to
row (N-K) (ii)
Repeated (N-K) times.
Index register (ii)
Minimum search algorithm (ii)
Row reduced new H matrix (iii)
RRB (out)
Fig. 2: Row Reduction Block (i, ii, iii
refer to SISO algorithm steps in Sect. 3)
this information. Likewise all the (N-K) rows of the parity
check matrix are processed and a new matrix is generated
and output by the row-reduction block. As depicted in Fig.
2, the RRB block takes 2 clock cycles to process the data
and generate the pseudo systematic matrix by way of row
reduction. The circuit block diagrams in Figs. 3 and 4
depict the computation of the most and least reliable bits
respectively from the received vector. Each computation is
completed in 2 clock cycles and the soft-output results are decoder. In such a decoder, the soft-input can be the
provided at output of the LRB block. combination of reliability information derived from the
received channel samples and the soft-outputs from previous
decoding operations. The values tend to grow with multiple
RRB(out)
iterations so an 8-bit word size for the input was selected.
The intermediate values within the decoder were limited to
Updated H matrix from RR block
10-bit word size through use of saturation arithmetic to
prevent overflow. If a value in the decoder saturates at the
Compute new MRB indices for each row (iv) maximum value, it signifies that the corresponding bit is

Repeated (N-K) times.

reliable as it has a large magnitude. In a TPC application, a
normalization routine is necessary to ensure that the values
Compute signs of soft inputs (iv) and compute
product of signs (iv)
remain within a range to prevent too many values from
reaching saturation. Such a normalization routine was
indeed implemented in the hardware.
Compute error arrays for each row producing a
single row of extrinsic matrix (v) To verify the performance of the EH (64,57) and EBCH
(64,51) decoders with additive white Gaussian noise, the
Total extrinsic = soft inputs + error matrix (v) algorithm with 8-bit word input and 10-bit internal word
size with saturation arithmetic was implemented and
MRB(out) simulated in Matlab. A nominal value of one from the
Fig. 3: Most Reliable Bit Block (iv and v channel was scaled to a quantized level of 64. In Figs. 5 and
refer to SISO algorithm steps in Sect. 3) 6, the codeword error rate versus the signal to noise ratio
Eb/N0, is shown for binary phase shift keying for the two
5. MATLAB AND HARDWARE codes along with an ideal hard decision decoder for
SIMULATION RESULTS comparison. The ideal decoders correct either 1 or 2 errors
for EH (64,57) or EBCH (64,51) respectively. As seen in
As one of the decoder functions is to act as component the figures, for a codeword error rate of 10-2 gains of 1 dB
decoder for a TPC application, the input values were and 0.8 dB are provided for the EH (64,57) and EBCH
quantized to 8-bit word size. The word size was chosen to (64,51) codes respectively. The hardware implementation
allow for growth of input values when used in an iterative results in Table 1 and simulation results in Figs. 5 and 6
shows that code performance, area, and throughput are a
Soft inputs MRB(out) function of the code configuration, namely the values of N
y
and K, and consequently register sizes and extent of parallel
Soft inputs => N symbol register
processing. The throughput results show that the two
decoders process the 64 symbol data blocks at the master
clock rates of 20.4 and 15.3 MHz.
For each soft input < 0, Composite vector = soft The Table 1 results show that the EBCH (64,51) decoder
index register stores -1 inputs + MRB(out). (vi) requires 25% more CLB slices than the second decoder and
otherwise stores +1. (vi) this corresponds to the difference of their respective H
matrices with 13 rows for the former and 7 for the latter.

Threshold vector (Vth) = composite 10

0

vector - first row of MRB(out) extrinsic

Repeated (N-K) times.

matrix (vii) -1
10

Take absolute of Vth (vii)

Codeword error rate

-2
10

Product of signs of Vth (vii) 10

-3

Compute the LRB extrinsic (vii) 10

-4

Ideal 1-error hard decision decoder

Vector SISO, 8 bit input, 10 bit internal
Decoded bits
0 1 2 3 4 5 6 7 8
E b /N 0 (dB)
LRB(out)
Fig. 5: Codeword error rate for EH (64,57) on the AWGN
Fig. 4: Least Reliable Bit Block (vi, vii refer to SISO channel. An ideal 1-error correcting hard decision decoder
algorithm steps in Sect. 3) is shown for comparison.
 0
10
-1
10
Codeword error rate
10
-2
-3
10
10
-4
Ideal 2-error hard decision decoder
Vector SISO, 8 bit input, 10 bit internal
0 1 2 3 4 5
E b/N0 (dB)
Fig. 6: Codeword error rate for EBCH(64,51) on the
AWGN channel. An ideal 2-error correcting hard decision
decoder is shown for comparison.
Table 1: Hardware implementation and simulation results
for (64, 57) and (64, 51) codes.
Code CLB Slices
(N,K)
EH (64,57) 12,200
EBCH (64,51) 15,266
The number of parity check equations (or rows in H matrix)
directly affects the hardware requirements of the vector
SISO decoder. The differences in parity check matrix
dimensionality also impacts on the master clock frequency
and decoder throughput as confirmed by results in Table 1.
Design efforts to lower the gate count by reducing the
intermediate word sizes showed that this would result in
performance degradation.
The implementations presented here are based on the
Xilinx XC2VP100-1704ff–5 FPGA device. The decoder
implementations incorporated a self-test circuit consisting of
a pseudo-random sequence generator, a comparator, delay
circuits, and multiplexers to route the signals. In normal
operation, the SISO decoder operates independently. The
self-test circuit enables on-chip at-speed verification of the
decoders.
6. SUMMARY
The SISO decoder implementation has resulted in a high
throughput circuit design. The VHDL code has been tested
and verified by comparing its results with that of the Matlab
based function models presented in [4]. The decoder
architecture is applicable to a wide range of linear block
codes such as Hamming codes, BCH codes, and binary
images of linear codes defined over GF(2m). Furthermore,
the decoder is sufficiently flexible so that it can be used in a
TPC decoder to provide improved bandwidth efficiency at
relatively low implementation cost [14].
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