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FPGA based telemetry system for meteorological balloon instrumentation

Conference Paper · January 2014

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Jayant Chouragade T. V. Chandrasekhar Sarma

National Atmospheric Research Laboratory National Atmospheric Research Laboratory
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 FPGA based telemetry system for meteorological balloon instrumentation
Jayant Chouragade, T.V.Chandrasekhar Sarma
National Atmospheric Research Laboratory, Gadanki-517112, AP, India
jayant@narl.gov.in, tvcsarma@narl.gov.in

1. INTRODUCTION

This paper presents design and implementation of a wireless data transceiver system, for use
with meteorological balloon based sounders over ranges of about 200 km, using FPGA and commercial
off-the-shelf transceiver IC (ADF7021). Use of ADF7021 enables identical hardware design for both
transmitter and receiver, except frontend and reduces complexity. Control logic, frame
formatter/synchronizer, Reed Solomon encoder/Decoder, Cyclic Redundancy Check and PC interface
functions are implemented in the FPGA. Two antenna systems - omni directional and directional,
coupled to identical receiver channels provide coverage over a wide range of elevation angles.

2. SYSTEM ARCHITECTURE

The overall system design specifications are given in Table 1.

Table-1: Design specification of the telemetry system
Parameter Specification
Range 200-250Km
Operating frequency 400-406Mhz with 100KHz step size
Modulation GFSK
Transmit power +20dBm
Data rate 2.4kbps, 4.8kbps and 9.6kbps
Transmitter power consumption 330mW peak
No. of receiver channels Two
Receiver antenna system 1. Monopole 2. RHC QHA
Receiver front-end gain 20dB
Error correction and detection RS(255,223) and CRC16
Receiver sensitivity -110dbm @ 4800bps and PER=10-3
Interface RS232 or TCP/IP
Software LabVIEW based

2.1 TRANSMITTER

The basic block diagram of the transmitter hardware is shown in Figure 1. Low power
transceiver ADF7021 is interfaced with Xilinx Spartan-3A FPGA which performs the modulation of the
data which is amplified to +20 dBm by RFMD ultra low noise LNA SPF5122. A TCXO with 3.5 ppm
accuracy clocks the ADF7021 for stable and accurate operation of its PLL. Total power requirement of
the transmitter is only 330 mW.

2.2 RECEIVER
 A two channel receiver as shown in figure-4 is implemented to receive the transmitted data.
Frontend LNA and filter block (based on RFMD SPF5122) provides 20 dB gain and 10 MHz bandwidth.
Demodulated and decoded signal is processed further in the FPGA.

Figure 1: Transmitter block diagram.

Figure-4: Receiver block diagram

4. SUMMARY

Overview of the implementation of a FPGA based long range telemetry system using off-the-
shelf transceiver is presented. Identical design architecture of transmitter and receiver reduces the
design cycle and NRE cost significantly. Use of FPGA as processing unit reduces the power requirement
significantly, hence very suitable for battery powered operation on board e.g radiosonde and tethered
balloon. A two channel receiver with monopole and quadrifilar helix antenna eliminates the use of
directional antenna system with switching logic and simplifies the receiver design.

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