Powered By

ORGANIZED BY
DEPARTMENT OF EEE, KUET

EVENT RULEBOOK
VLSI BATTLEGROUND

Technical Partner

EEE DAY 2023

EVENT DESCRIPTION

Why 'VLSI Battleground' Matters: This contest

is more than a competition; it's an inspiration.
It's a blazing beacon calling upon students in
Bangladesh to not just learn, but to embrace
VLSI, to study it passionately.

After completing the registration of this

contest the participants will receive
confirmation mail with details of the venue and
the starting time of the competition. The
participants must be present in the right
location before the time.

Page 01
 ELIGIBILITY

Students at the undergraduate level and

recent graduates from any university may
apply.

Team can be formed with minimum of two

members and maximum of three members

Cross-university teams are allowed.

Page 02
REGISTRATION INFO

Registration Fee Per Team :

800 Tk BDT ( 2 Member)
1300 Tk BDT ( 3 Member )

Registration Deadline : 31/10/2023

To Register, scan the QR code

Page 03
COMPETITION DETAILS

Participants must bring their student IDs

for the verification process.

During the competition, participants are

NOT allowed to :
Leave the area
Communicate with anyone outside
their own team

Each team must install the required

software before the event.

For any issues, the team leader will be

the point of contact.

Participants must bring their own laptops

(minimum 1 laptop per team).

Page 04
COMPETITION DETAILS

Students must also bring multi-plug,

adapters and charging cords .

Limited use of the Internet is allowed

during the competition. (Browsing AI-
based websites and uses of social media
are not allowed).

Each team must prepare a report of their

designs & simulations and upload the
results and required design documents to
pre-specified cloud storage. Storage links
will be shared at the beginning of the
competition. The link will be automatically
deactivated upon the expiration of the
competition.

Page 05
COMPETITION DETAILS

Total Duration: 5 Hours (Excluding Break)

The judge's decision is final; NO appeal

will be entertained.

The competition will end at the same time

for all teams and will NOT be extended.

The authority reserves the right to

amend the rules.

Any participant or team that is found to

be in violation of the regulations may be
disqualified by the organizers.

Page 06
MODULE - 1

Digital Design and Verification

Tools : (Can use any of the following)

Quartus
ModelSim
EDA Playground (Online tool)

Syllabus :

DLD / Digital Logic Design

Digital design (RTL) using Finite State
Machine
Linear / Class based Test Bench

Page 07
MODULE -1

Digital Design and Verification

Important Notes

For digital design and verification, the

following hardware description languages
can be used: Verilog, SystemVerilog, and
VHDL.

While writing a testbench for technical

evaluation, a linear testbench is
considered acceptable. However, a class-
based testbench will be awarded extra
marks.

Page 08
 MODULE - 1

Digital Design and Verification

Important Notes

Participants are required to submit the

following files for evaluation:

1.Design Files: These should include the

design implementation files.

2.Testbench Files: These should include the

testbench code written to verify the design's
functionality.

3.Waveform: A waveform file showing the

simulation results of the design and its
interaction with the testbench.

Page 09
MARKING CRITERIA

The evaluation and judging of designs will consider the

following factors:
1.Functionality: The design should meet the specified
requirements and perform the intended tasks correctly.

2.Performance: The design should demonstrate efficient

and reliable operation within specified performance
metrics.

3.Design Methodology: The design should adhere to

established best practices and industry standards.

4.RTL Code Quality: The design's RTL (Register Transfer

Level) code should be well-structured, readable, and
maintainable.

5.Testbench Coverage: The testbench should provide a

comprehensive stimulus to exercise the design and detect
potential bugs thoroughly.

6.Documentation Clarity: The design should be

accompanied by clear and concise documentation,
explaining its functionality, design choices, and any special
considerations.

Page 10
MODULE - 2

Analog Circuit Design and Verification

Tools : (Can use any of the following)

LTSpice
HSpice

Syllabus :

Basic Electronics
DLD
VLSI
Analog Circuit
1. Current Mirrors
2. Differential Amplifier

Page 11
 MODULE - 2

Analog Circuit Design and Verification

Process Design Kit Rule

Drive Link for Library

Page 12
MODULE - 2

Analog Circuit Design and Verification

Important Notes

Participants must include the design

library provided above. Use of any other
library/PDK is strictly forbidden.

Design the circuits from the transistor

level. Symbols have to be created if the
same block is going to be used in higher-
level design. Use of built-in symbols/blocks
(Logic gates/Adders etc.) is strictly
prohibited.

Page 13
MODULE -2

Analog Circuit Design and Verification

Important Notes

Participants are required to submit the

following files for evaluation:

1. All the schematic files (i.e. files with *.asc

extension if LTspice is used)

2. A well-documented report containing

the snapshots of the schematics, input-
output waveforms, calculations, and/or
result summary table

Page 14
CONTACT INFO

Tanveen Hossain
VLSI Battleground Segment Co-Ordinator
Department of EEE, KUET
Mail ID: hossain1803032@stud.kuet.ac.bd
Contact No: +8801906277118

Majed
VLSI Battleground Segment Co-Ordinator
Department of EEE, KUET
Mail ID: majed1803052@stud.kuet.ac.bd
Contact No: +8801714069113

Khulna University of Engineering & Technology, Khulna

Page 15