Higher Technological Institute ‘oth of Ramadan City ~ 6th of October Branch Department of Electronics and communications Engineering Term: ‘OCT. 2023 ~ [rime allowed: ‘90 mins. Subject: Logie design? EEC 142 Group: 123.45, Examiner: | ASST. Prof. Suzan Shukry ‘Asessment Mark: 40 marks | ‘Final Exam UESTION(1) LOL, LO [10 Marks) 1a} Show how to get +Ve edge Tip flop from SR LATCH with NANO gates only (3 MARKS) b).A sequential circuit with two T-FFs, one input xand one output y has the following input and output equations: V7MARKS) ‘Tax’ +BX) Tos AxB y=A'B'+X i) Draw the logic diagram, i) Derive the state table ii)Sketch the state diagram QUESTION(2) _L03,L04,LO6 10 Marks] 4) Derive the state equation of JK flip flop . (amarks) b) Design a sequential circuit having the state diagram of Figure (2) using K-FF (7 MARKS) UESTION(3} _L03 105,106 a2 Marks] 2) Using_0-FFs Design synchronous counter that counts from 0 up to 10 and return back 100 (6 MARKS) bjoesign a ripple counter that go through the counting sequence from to and back to 7 using ave edge JK FFs (verify your design using waveforms ) (6 MARKS) Examination Committee Ipagewra Figure 1 UESTION(4) LOS,LOS [s marks] For the circuit shown in figure 2 ifthe content of register A and register B initially 1011, and 1110 respectively . Find the contents of register A and register B for the given clock and shift UL [pagent