Introduction to CMOS RF Integrated Circuits Design

III. Low Noise Amplifiers

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-1
Outline

 Figures of merit
 Basic Structure
 Input and output matching
 Noise (NF)
 Gain (over the band)
 Linearity (IIP3, SFDR)
 Stability

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-2
Figures of Merit (FOM)

•Frequency
•Noise Figure
•Linearity (CP-1dB, IIP3)
•Bandwidth and Q
•Gain S21
•Power Consumption
•Supply Voltage
•Stability

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-3
Typical Values

NF ~ 2dB
IIP3 ~ 0 dBm
CP-1dB ~ -10 dBm
Gain 15~ 20 dB
S11, S22 < -10 dB
S12 < - 30 dB
Supply Voltage ~ 1.2-1.8 V
Current ~ 5 mA

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-4
CS Structure

Vout
RS Cu Cdb+CL

Vin

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-5
Dominant Pole

The input cap is usually the dominant pole: Vout

RS Cu Cdb+CL

Vin
0 1  Rs (Cin  AV Cu )
0 1  RsCin (1  AV u )  RsCin AV u

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-6
Dominant Pole

For a voltage gain of gmRL,at low freq., we have:

1 Cin
0  RsCin AV u  ( g m Rs )( g m RL ) u
gm
R 1
 Av
2 s
u
RL T
RL 1
0 Av  T
2

RS u
If Av=10 and RL/Rs=2,u=0.2
T
0 
10

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-7
Observations

 For high frequency operation

 higher T is desirable  high gm  high current
 Less capacitance is desirable
 Lower gain  reduce Miller capacitance? …but we
usually need a certain amount of gain. So what to do?
(Think….cascode?)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-8
Input Matching--Why

•Provides Good Termination for Transmission Line

from Antenna (Antenna/RF filters usually are designed with
50Ω terminations, same as the measurement equipments)
•Maximizes Power Transferred
•Conjugate matching
•Preserves Characteristics of Duplexer Filter
•Stability

Connection length ≥ λ/4 should be considered a

transmission line

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-9
Input Matching - Resistive Termination

Extra Noise from RT => NF  3 dB

Input Noise Source is Attenuated => NF is
degraded further

RT
Zin

Zin = RT = 50 

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-10
Input Matching - 1/Gm Termination

Require Large Power to Achieve 50-Ohm

Matching
Unity Current Gain => Current Noise
becomes Significant and Limited Reverse
Isolation

Zin

Zin = 1/gm = 50 

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-11
Input Matching - 1/Gm Termination

v 2

F  1 eq

4kTR s

1
BJT : Fmin 1 1.51.8dB
2 g m Rs
2
MOS : Fmin 1 1.7  2.2dB
3g m Rs

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-12
Input Matching--Resistive Shunt Feedback

•Added noise RF
•Broadband Amplification due to
Feedback => More Power to Reduce
Noise

Zin

Zin = RF /(1+Av)= 50 

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-13
Input Matching--Inductive Degeneration

LG
•Ideal Inductors are Noiseless => No
Extra Noise Contribution
•More Flexibility in Design and
Optimization
Zin LS

Zin = 50 

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-14
Input Matching--Inductive Degeneration

Zin  ZL  ZC  (1 gmZC )ZL

G gs gs S

1 gm LS
 s(LG  LS ) 
sCgs Cgs
1
 T LS @ f 
2 (LG  LS )Cgs

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-15
Input Matching--Inductive Degeneration

•Low-Q Inductors:
•Relatively Broad Band
•Small Design Headroom for Matching
•Small Noise => Large Gm => Small LS => Large
LG => LG parasitic resistance contributes more
noise
•Inductors, in particular LG, have been implemented
using bondwire or off-chip

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-16
LNA - Performance

•NF and gain of the LNA determine NFtotal

•LNA is there to improve the overall nosie performance
(NFMix >NFLNA )
•High IIP3 of LNA is usually desired for reducing in-band
IM distortions
•Total IIP3 is usually determined by Mixer and the
following blocks, not by LNA
•Matching is optimized for overall signal performance in
the front-end

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-17
LNA - Noise Figure

i g2 in2,d

in2,d  4KTgd 0f

i  4KTgg
2
g c
ig id*
 2C gs2 ig2id2
gg 
5g d 0
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou III-18
LNA - Noise Figure

en2  Rn 4 KTf
i S2  G S 4 KTf
iu2  Gu 4 KTf
ic2  YC en2
YS  GS  jBS
i  YC  Y e
2 2 2

NF  1  u S n
YC  GC  jBC
iS2
2
NF  1  2 Rn (Gopt  GC )  ( Rn / Gs ) YS  Yopt

Yopt  Gopt  jBopt  Gu / Rn  Gc  jBc

2

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-19
LNA - Noise Figure

2
vRg

in2,d

•The current gain of the MOS Amplifier is given by:

vs 1
io  g m v1  g m ( )
Rs  Rg 
1 jCgs
jC gs
vs vs
 gm  gm
( Rs  Rg ) jC gs  1 ( Rs  Rg ) jC gs

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-20
LNA - Noise Figure

•This can be re-written as:

T 1
io  Gm vs Gm   j
 ( Rs  Rg )
•The total noise is given by:

i 2o ,T  Gm ( v 2 g  v 2 s )  i 2 d
2

•The noise figure is given by:

v2g i 2d
F  1 2

v s G 2m v 2 s

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-21
LNA - Noise Figure

•Substitution of the various noise sources leads to:


( ) gm
 2
 
Rg
F  1 ( ) ( Rs  Rg ) 2
Rs Rs T

•Assume Rs>>Rg
Rg  2 
F  1 ( ) ( ) g m Rs
Rs T 
It’s important to note that this expression contains both the channel noise and
the gate induced noise. If we assume that Rg = Rpoly + 1/5gm, and the noise is
independent from the drain thermal noise, we get a very good approximation
to the actual noise without using correlated noise sources.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-22
LNA - Noise Figure

•The optimal value of Rs

F Rg   2
  2  ( )( ) g m  0
Rs Rs  T
Rg   2
 ( )( ) gm
Rs
2
 T
  2 T 2 Rg
Rs ,opt  Rg ( )( ) g m  ( )
 T  
( ) gm

 
Fmin  1  2( ) g m Rg ( )
T 

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-23
LNA - Noise Figure

Let’s find Rs,opt for a typical amplifier. Say fT = 75GHz, f = 5 GHz, and
(γ/α)= 2. Also suppose that by proper layout Rpoly is very small. The
intrinsic gate resistance is given by:

1 1
Rg  R poly  
5gm 5gm
Rg 1 10 1
 0 .1  0. 1 gm   S  40ms
Rs 5 g m Rs 5  50 25
Note that for Vgs-VT = 200mV, the required current is:

1 1
I ds  g m (Vgs  VT )  40ms  200mV  4mA
2 2
fT Rg 5  25
Rs ,opt   15  119
f  2
( ) gm

  2 52
Fmin  1  2( ) g m Rg ( )  1   1.08  0.35dB
T  15 25

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-24
LNA - Noise Figure

•for a given circuit / bias source admittance Ys;

•there is an optimum admittance to Fmin!
•the RF Filter / Duplexer impedance Rs= 50Ω(Ys= matching is
a must!)
•the NF optimization is fixed), but by changing the bias and
W/L ratios circuit
•it is difficult/impossible 50Ωinput matching and Fmin
•The noise is higher at higher frequencies

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-25
LNA - Noise Figure

RLG LG RG

RS Zin LS

RLS

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-26
LNA - Noise Figure

2
vRg

in2,d

It’s fairly easy to calculate the noise for the case with inductive degeneration.
Simply observe that the input generators noises see a gain of Gm2 to the
output.
The drain noise, though, requires a careful analysis. Since it flows partly into
the source of the device, it activates the gm of the transistor which produces
a correlated noise in shunt with drain noise.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-27
LNA - Noise Figure

in2,d

The above equivalent circuit shows that the noise component

flowing into the source is given by the current divider:
jLs 1
v  ( g m v  id )  
 jLg  Rs jC gs
1
jLs 
jC gs

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-28
LNA - Noise Figure

At resonance:

jLs 1
v  ( g m v  id )  
Rs jC gs
Ls
v  ( g m v  id ) 
RsC gs
g m Ls Ls
v (1  )  id
RsC gs RsC gs

When matched, Rs  T Ls

Ls id g m Ls i
2v  id g m v   ) d
RsC gs 2 RsC gs 2

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-29
LNA - Noise Figure

So we see that only 1/4 of the drain noise flows into the output! The total
output noise is therefore

i 2d
 Gm ( v  v s) 
2 2 2 2
i o ,T g
4
v2g i 2d  2  g m ( 2 Rs ) 2
Rg
F  1 2
 2 F  1 ( ) ( )
v s 4v 2 sGm Rs T  4 Rs
Rg  2 
F  1 ( ) ( ) g m Rs
Rs T 

The inductive degeneration did not raise the noise ! So the minimum noise
figure Fmin is the same.
The advantage is that the input impedance is now real and programmable
(ωTLs). By proper sizing, it’s possible to obtain a noise and power match.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-30
LNA - Effective Gm

Either By Short-Cut or By Series Resonant Tank:

ZC
Gm  gm gs
 g m Q in 
R s  Z in
gmZC T
 Gm   o  gs

2Rs 2 o R s

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-31
LNA - Effective Gm

W    W , L   L , V   V , L   LG /  GS GS G

 I   I DD

    T T

T T
 G m   Gm
2 o R s 2 o R s
 Same Gm as Cgs and Power are Reduced!

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-32
LNA – Linearity Consideration

i  gmVgs  bVgs2  cV gs3

d
V RS Lg Iin Id
i  in
in 2R
s
i V V Q
Vgs  in  in  in
 C gs 2Rs C gs
0 0
2 Vin
V Q V Q V Q
Cgs
i  gm in  b( in )  c( in )3
2
d 2 2 2
4 g mQ / 2 16g m
A2 ,  
in IP3 3 c(Q / 2)3 3cQ 2 LS
Larger gm or Smaller Q  larger IP3 
larger power consumption or larger Cgs
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou III-33
LNA – Linearity Consideration

 Maximize Q or Vgs => NF Degradation

 For Same Power, Minimize Device Size
 For Same Device Size, Maximize Power
 Maximize Supply Voltage
 Minimize Gain
 Employ Differential Topology

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-34
LNA – Output Loading

 Small Resistive Load => Small Gain

 Large Resistive Load => Problems with Bandwidth, Voltage
Headroom and Linearity
 Inductors Resonate Output Capacitance for High Frequency, High
Gain, and Narrow-Band Filtering

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-35
LNA – Output Loading

 For Low-Q Inductors, May Need Negative-Gm

Compensation to Achieve High and Tunable Q and Gain
 Negative-Gm Compensation Circuitry Degrades NF,
Linearity, and Power

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-36
LNA – Output Matching Network

 Driving Off-Chip Filter Needs Output Matching:

 Preserve Filter Characteristic
 Need 50-Ohm Buffer
 Consumes Power and Degrades Linearity
 LC Resonant Loading Can Also Be Used for Matching
 Driving On-Chip May NOT Need Matching

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-37
LNA – Stability Criteria

Z in  R s Zo  RL
S  , S 
Z in  R s Zo  RL
11 22

Po Pin
S  AP 
21
, S  12
Pin Po
S S S S 1
11 22 21 12

1   S  S
2 2 2

K  1 11 22

2S S 21 12

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-38
LNA – Cascode Design

 Increase Reverse Isolation =>

Improved Stability vo
 Increase Voltage Gain
VB
 Eliminate Input Miller Capacitance LG
 Sacrifice Voltage Headroom and
Linearity

Zin LS

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-39
Comparison

Zin F(50 Ohm) Gain Typical

NF (dB)
CS/Shunt 4 g m RL
Rsh 2  10
Resistor g m Rs 2

Common 1/gm 1  g m RL
5
Gate

Feedback RF  RL  6
1
R
 s (1 
1 2
)  g m RL
Stage 1  g m RL g m Rs RF g m Rs

Inductor g m Ls  1 2 2
1 ( )  g mQin RL
Source C gs g m Rs Qin
Degeneration

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-40
LNA – Differential Design

 Insensitive to Parasitic Inductors

 Reject Common-Mode Noise (Substrate, Supply)
 Improved Linearity and Dynamic Range
 Higher NF for Same Power or Same NF for Doubled
Power
 Larger Chip Area

 Antenna and Duplexer Filter Are Single-Ended

 Need Baluns to Convert Single-Ended Signals to
Differential

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-41
Cascode With Inter-Stage Matching

Ca vo
Without Lint, M1 is loaded by
VB M2 Z=1/(gm2+jωCgs2)

Lint provide inter-stage matching

Lint
(Ca is for stable reason)
LG •The gain of first stage is improved
M1 •The NF reduced
•Larger silicon area
Zin LS

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-42
Low Voltage Operation

vdd
No stacked transistors.
VB is used to control the gain.
LG VB Which will not affect input matching.

Zin
LS L0 C0

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou III-43
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou III-44