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• RW: This is Read/write pin, you will set it to 0, if you are going
to write some data on LCD.
– And set it to 1, if you are reading from LCD module.
– Generally this is set to 0, because you do not have need to
read data from LCD.
• E: This pin is used to enable the module when a high to low pulse
is given to it.
– That transition from HIGH to LOW makes the module
ENABLE.
Hex
Command to LCD Instruction Register
Code
0F LCD ON, cursor ON
01 Clear display screen
02 Return home
04 Decrement cursor (shift cursor to left)
06 Increment cursor (shift cursor to right)
05 Shift display right
07 Shift display left
0E Display ON, cursor blinking
80 Force cursor to beginning of first line
C0 Force cursor to beginning of second line
38 2 lines and 5×7 matrix
83 Cursor line 1 position 3
3C Activate second line
08 Display OFF, cursor OFF
C1 Jump to second line, position 1
OC Display ON, cursor OFF
• Commonly used LCD instructions
• Each command is a 8-bit hexadecimal data
Command Interpretation
30 H LCD interprets this as the user would like to set LCD in 8-bit mode,
use only 1 line (row) of LCD and the font size of 5X7 (i.e. 5 dots
(pixels) in row and 7 dots (pixels) in a column)
P1 P0 D0-D7
EA A0
| ROM/
8051 LATCH A7 EPROM
ALE
clock
A8 Address
P3 | lines
A15
PSEN OE
P1 D0 data
P0 | lines
D7
RAM
8051 LATCH A0
ALE clock |
A7 address
lines
RD P3 P2
2
LINEAR AND ABSOLUTE DECODING
i. Absolute Decoding
all higher address lines : decoded to select memory chip for
specific logic levels.
for other logic levels memory chip is disabled.
generally used in large memory systems.
figure below shows memory interfacing using absolute decoding.
Vss
P0.7 D7-D0
EA |
P0.0
74LS373 A7-A0
ALE G OC 16k x 8
8051 RAM
P2.0
| A8-A13
P2.5
P2.6
P2.7 CS
PSEN
P3.6 WR
P3.7 RD
ALE G OC 16 x 8
8051 RAM
P2.0
| A8-A13
P2.5
P2.6 CS (A14)
P2.7 A15
PSEN
P3.6 WR
P3.7 RD
1
Address Mapping(Memory Map)
i. Absolute Decoding
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
ii. Linear Decoding
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end x 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
i. all higher address lines are |i. few or individual address lines
decoded to select memory or | are decoded to select memory or
I/O device. | I/O device.
ii. more hardware : decoding |ii. less hardware : decoding logic.
logic. | (sometimes none.)
iii. decoding circuit : higher |iii. decoding circuit : less cost.
cost. |
iv. No multiple addresses. |iv. multiple addresses possible.
v. used in large systems. |v. used in small systems.
Solved Examples:
Example 1: Design a µController system using 8051.Interface the external RAM
of size 16k x 8.
Solution: Given, Memory size: 16k
that means we require 2n=16k :: n address lines
here n=14 :: A0 to A13 address lines are required.
A14 and A15 are connected through OR gate to CS pin of external RAM.
when A14 and A15 both are low (logic ‘0’), external data memory(RAM) is
selected.
Address Decoding(Memory Map)for 16k x 8 RAM.
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
ALE G OC 16k x 8
8051 RAM
P2.0
| A8-A13
P2.5
P2.6
P2.7 CS
PSEN
P3.6 WR
P3.7 RD
FIGURE 5 16K X 8 MEMORY (RAM) INTERFACING TO µC 8051.
4
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