CSN 506 : Tutorial 1, 2, and 4 (23 Jan, 02 Feb,13 Feb -2024)

1. Some microprocessors today are designed to have adjustable voltage, so a 15% reduction
in voltage may result in a 15% reduction in frequency. What would be the impact on
dynamic energy and on dynamic power?

2. Assume a disk subsystem with the following components and Mean time to failure (MTTF):

○ 10 disks, each rated at 1,000,000-hour MTTF

○ 1 ATA controller, 500,000-hour MTTF

○ 1 power supply, 200,000-hour MTTF

○ 1 fan, 200,000-hour MTTF

○ 1 ATA cable, 1,000,000-hour MTTF

Using the simplifying assumptions that the lifetimes are exponentially distributed and that
failures are independent, compute the MTTF of the system as a whole.

3. Suppose that we want to enhance the processor used for Web serving. The new processor is 10
times faster on computation in the Web serving application than the original processor. Assuming
that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of
the time, what is the overall speedup gained by incorporating the enhancement?

4. A common transformation required in graphics processors is square root. Implementations of

floating-point (FP) square root vary significantly in performance, especially among processors
designed for graphics. Suppose FP square root (FPSQR) is responsible for 20% of the execution
time of a critical graphics benchmark. One proposal is to enhance the FPSQR hardware and
speed up this operation by a factor of 10. The other alternative is just to try to make all FP
instructions in the graphics processor run faster by a factor of 1.6; FP instructions are responsible
for half of the execution time for the application. The design team believes that they can make all
FP instructions run 1.6 times faster with the same effort as required for the fast square root.
Compare these two design alternatives.
 CSN 506 : Tutorial 1, 2, and 4 (23 Jan, 02 Feb,13 Feb -2024)

5. Suppose that when Program A is run, the user CPU time is 3 seconds, the elapsed wallclock time
is 4 seconds, and the system performance is 10 MFLOP/sec. Assume that there are no other
processes taking any significant amount of time, and the computer is either doing calculations in
the CPU, or doing I/O, but it can't do both at the same time. We now replace the processor with
one that runs six times faster, but doesn't affect the I/O speed. What will the user CPU time, the
wallclock time, and the MFLOP/sec performance be now?

6. You are on the design team for a new processor. The clock of the processor runs at 200 MHz. The
following table gives instruction frequencies for Benchmark B, as well as how many cycles the
instructions take, for the different classes of instructions. For this problem, we assume that (unlike
many of today's computers) the processor only executes one instruction at a time.

Instruction type Frequency Cycles

Loads & Stores 30% 6 cycles
Arithmetic instructions 50% 4 cycles
All others 20% 3 cycles

A. Calculate the CPI for Benchmark B.

B. The CPU execution time on the benchmark is exactly 11 seconds. What is the ``native
MIPS'' processor speed for the benchmark in millions of instructions per second?
C. The hardware expert says that if you double the number of registers, the cycle time
must be increased by 20%. What would the new clock speed be (in MHz)?

**3rd Tutorial on OMP (Programs done in class and slide shared)

 CSN 506 : Tutorial 1, 2, and 4 (23 Jan, 02 Feb,13 Feb -2024)

Solution 1:

Solution 2:

Solution 3:

Solution 4:
 CSN 506 : Tutorial 1, 2, and 4 (23 Jan, 02 Feb,13 Feb -2024)

Solution 5:

Solution 6:

A.

B.
 CSN 506 : Tutorial 1, 2, and 4 (23 Jan, 02 Feb,13 Feb -2024)

C.