EXCEL ENGINEERING COLLEGE

(Autonomous)
Department of Computer Science and Engineering
III Semester
20EC306-DIGITAL LOGICs AND MICROPROCESSOR
Regulation 2020
UNIT II COMBINATIONAL LOGIC CIRCUITS

Q.No Questions Marks CO BL

1 Define De-Multiplexing. 2 CO2 R
 A Demultiplexer is a circuit that receives information on a single line and transmits
this information on one of 2n possible output lines.
2 Differentiate Combinational circuits and Sequential Circuits. 2 CO2 R
Combinational circuits Sequential circuits
Memory unit is not required Memory unit is required
Parallel adder is a combinational Serial adder is a sequential circuit.
circuit
The output depends on only present The output depends on present
input input and past output
3 What is decoder? 2 CO2 R
 A decoder is a combinational circuit that converts binary information from ‘n’ input
lines to a maximum of 2n unique output lines.
4 Label the applications of multiplexer. 2 CO2 R
The various applications of multiplexer are
 Data routing.
 Logic function generator.
 Control sequencer.
 d. Parallel-to-serial converter.
5 Show the logic diagram of Full-Adder. 2 CO2 R

6 What are called don’t care conditions? 2 CO2 R

 In some logic circuits certain input conditions never occur, therefore the
corresponding output never appears.
 In such cases the output level is not defined, it can be either high or low.
 These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t
care conditions or incompletely specified functions.
7 What is a prime implicant? 2 CO2 R
A prime implicant is a product term obtained by combining the maximum possible
 number of adjacent squares in the map.
8 What is an essential implicant? 2 CO2 R
If a min term is covered by only one prime implicant, the prime implicant is said to be
essential.
9 Write the design procedure for combinational circuits. 2 CO2 R
 The problem definition
 Determine the number of available input variables & required O/P variables.
 Assigning letter symbols to I/O variables
 Obtain simplified Boolean expression for each O/P.
 Obtain the logic diagram.
10 What is binary decoder? 2 CO2 R
A decoder is a combinational circuit that converts binary information from n input lines to
a maximum of 2n out puts lines.
11 Define Encoder. 2 CO2 R
An encoder has 2n input lines and n output lines. In encoder the output lines generate
thebinary code corresponding to the input value.
12 What is priority Encoder? 2 CO2 R
A priority encoder is an encoder circuit that includes the priority function.
In priority encoder, if 2 or more inputs are equal to 1 at the same time, the input having
the highest prioritywill take precedence.
13 What do you mean by comparator? 2 CO2 R
A comparator is a special combinational circuit designed primarily to compare the
relativemagnitude of two binary numbers.
14 Define half adder and full adder. 2 CO2 R
The logic circuit that performs the addition of two bits is a half adder. The circuit that
Performs the addition of three bits is a full adder.
15 Define multiplexer. 2 CO2 R
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.
16 Define combinational logic. 2 CO2 R
When logic gates are connected together to produce a specified output for certain
specifiedcombinations of input variables, with no storage involved, the resulting circuit
is called combinational logic.
17 What is code converter? 2 CO2 R
 It is a circuit that makes the two systems compatible even though each uses a
different binary code.
 It is a device that converts binary signals from a source code to its output code.
One example is a BCD to excess 3 converter.
18 What is Binary parallel adder? 2 CO2 R
A binary parallel adder is a digital function that produces the arithmetic sum of two
binary numbers in parallel.
19 State the limitations of Half-adder. 2 CO2 R
 In multidigit addition, add two bits along with the carry of previous digit addition.
Effectively such addition requires addition of three bits.
 This is not possible with half adder. Hence, half-adders are not used in practice.
20. State the limitations of Half-Subtractor. 2 CO2 R
 In multidigit subtraction, subtract two bits along with the borrow of previous digit
subtraction.
 Effectively such subtraction requires subtraction of three bits. This is not possible
with half subtractor.
 PART – B

Q.No Questions Marks CO BL

Explain the Logic implementation of BCD adder. (or) Show and implement the
1 16 CO2 U
BCD adder using combinational circuit.
The digital system handles the decimal number in the form of binary
coded decimal numbers (BCD). A BCD adder is a circuit that adds two BCD
bits and producesa sum digit also in BCD.

To implement BCD adder we require:

 4-bit binary adder for initial addition
 Logic circuit to detect sum greater than 9 and
One more 4-bit adder to add 01102 in the sum if the sum is greater
than 9 or carry is 1.

Binary Sum BCD Sum

Decimal
K Z 8 Z 4 Z 2 Z 1 C S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
 Discuss the Encoder and Decoder.(or) Implement the encoder and decoder using
2 16 CO2 U
combinational logic circuit.
An encoder is a digital circuit that performs the inverse operation of a decoder.
Hence, the opposite of the decoding process is called encoding. An encoder is
a combinational circuit that converts binary information from 2n input lines to a
maximum of ‘n‘unique output lines.
Octal-to-Binary Encoder:
It has eight inputs (one for each of the octal digits) and the three
outputs that generate the corresponding binary number. It is assumed that
only one input has a value of 1 at any given time.
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
-----------------(2)

----------------------------(2)
DECODERS
A decoder is a combinational circuit that converts binary information
from ‗n‘ input lines to a maximum of ‗2n‘ unique output lines. The general
structure of decodercircuit is –

-------(2)
 Inputs Outputs -------- -- (2)
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

3 Explain the Magnitude Comparator and Implement the 2-Bit/4 Bit Magnitude
Comparator (or) show the magnitude comparator of two binary numbers using 16 CO2 U
combinational logic circuit.

A magnitude comparator is a combinational circuit that compares

two given numbers (A and B) and determines whether one is equal to, less
than or greater than the other ---- (8)
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0 16 CO2 U
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
 --------(8)

4 Discuss the 2 Bit by 2 Bit Binary Multiplier (or) Implement the 2 bit Binary
multiplier using Combinational Logic Circuit. 16 CO2 U

 Multiplication of binary numbers is performed in the same way as in decimal

numbers.
 The multiplicand is multiplied by each bit of the multiplier starting from the
least significant bit.
 Each such multiplication forms a partial product; such partial products are
shifted one position to the left.
 The final product is obtained from the sumof partial products.

………---(8)
4X4 Binary Multiplier
5 Explain in detail about Multiplexer and Demultiplexer. (or) Enumerate the
details of MUX and DEMUX with combinational logic circuit.
 A multiplexer (MUX) is a digital switch which connects data from one of n sources
to the output. A number of select inputs determine which data source is connected
to the output. 16 CO2 U
 The block diagram of MUX with n data sources of b bits wide and s bits wide
select line is shown in below figure.
 MUX acts like a digitally controlled multi-position switch where the binary code
applied to the select inputs controls the input source that will be switched on to the
output as shown in the figure below.
 At any given point of time only one input gets selected and is connected to output,
based on the select input signal.
 The operation of a multiplexer can be better explained using a mechanical switch
as shown in the figure below. This rotary switch can touch any of the inputs, which
is connected to the output.
2x1 MUX

 A 2 to 1 line multiplexer, each 2 input lines A to B is applied to one input of an

AND gate. Selection lines S are decoded to select a particular AND gate.

DEMULTIPLEXER
 Usually implemented by using n-to-2n binary decoders where the decoder enable
line is used for data input of the de-multiplexer.
 Block diagram which has got s-bits-wide select input, one b-bits-wide data input
and n b-bits- wide outputs.
  The operation of a de-multiplexer can be better explained using a mechanical
switch as shown in the figure below.
 This rotary switch can touch any of the outputs, which is connected to the input.
As you can see at any given point of time only one output gets connected to input.

1-to-4 De-multiplexer

6 Implement the Parity Generator and Checker in detail.

Parity Bit Generator
There are two types of parity bit generators based on the type of parity bit being
generated.
Even Parity Generator
 To implement an even parity generator for a 3-bit binary input, WXY. It generates
an even parity bit, P.
 If odd number of one’s present in the input, then even parity bit, P should be ‘1’ so
that the resultant word contains even number of ones.
 For other combinations of input, even parity bit, P should be ‘0’. The following table
shows the Truth table of even parity generator.
Binary Input WXY Even Parity bit P

000 0

001 1

010 1

011 0

100 1

101 0

110 0
 111 1
From the above Truth table, the Boolean function for even parity bit as
P=W′X′Y+W′XY′+WX′Y′+WXY
P=W′(X′Y+XY′)+W(X′Y′+XY)
P=W′(X⊕Y)+W(X⊕Y)′=W⊕X⊕Y
The following figure shows the circuit diagram of even parity generator.

Odd Parity Generator

 If even number of one’s present in the input, then odd parity bit, P should be ‘1’ so
that the resultant word contains odd number of ones. For other combinations of
input, odd parity bit, P should be ‘0’.
 The circuit diagram of odd parity generator is shown in the following figure.

Parity Checker
There are two types of parity checkers based on the type of parity has to be checked.
Even parity checker
 To implement an even parity checker circuit. Assume a 3-bit binary input, WXY is
transmitted along with an even parity bit, P.
 So, the resultant word data contains 4 bits, which will be received as the input of
even parity checker.
 It generates an even parity check bit, E. This bit will be zero, if the received data
contains an even number of ones.
 That means, there is no error in the received data. This even parity check bit will be
one, if the received data contains an odd number of ones. That means, there is an
error in the received data.
4-bit Received Data Even Parity Check bit E
WXYP

0000 0

0001 1

0010 1

0011 0

0100 1

0101 0
 0110 0

0111 1

1000 1

1001 0

1010 0

1011 1

1100 0

1101 1

1110 1

1111 0
 The Boolean function of even parity check bit is an odd function. Exclusive-OR
function satisfies this condition. Hence, we can directly write the Boolean
function of even parity check bit as
E=W⊕X⊕Y⊕P
The following figure shows the circuit diagram of even parity checker.

Odd Parity Checker

 Assume a 3-bit binary input; WXY is transmitted along with odd parity bit, P. So, the
resultant word contains 4 bits, which will be received as the input of odd parity
checker.
 It generates an odd parity check bit, E. This bit will be zero, if the received data
contains an odd number of ones.
 The circuit diagram of odd parity checker is shown in the following figure.

UNIT III SEQUENTIAL LOGIC CIRCUITS

PART A
Q.No Questions Marks CO BL
1 List the four different types of shift registers. 2 CO3 R

 Serial in Serial out

 Serial in Parallel out
 Parallel in serial out
  Parallel in Parallel out
2 Give the excitation table of JK-flip flop. 2 CO3 R

3 What do you mean by triggering of flip-flop? 2 CO3 R

The state of a Flip-Flop is switched by a momentary change in the input signal. This
momentary change is called a trigger and the transition it causes is said to trigger the Flip-
Flop.
4 Define Latches. 2 CO3 R
 Latch is a simple memory element, which consists of a pair of logic gates with their
inputs and outputs inter connected in a feedback arrangement, which permits a single
bit to be stored.
5 List few types of counter. 2 CO3 R
 2/3/4 Bit Binary Synchronous Counters
 Synchronous UP/DOWN counters.
 4 Bit Binary Decade Counters
 Mod N counters.
6 Give the excitation table of SR-flip flop. 2 CO3 R

7 What is the operation of T flip-flop? 2 CO3 R

T flip-flop is also known as Toggle flip-flop.
 When T=0 there is no change in the output.
 When T=1 the output switch to the complement state (ie) the output toggles.
8 Define fundamental mode sequential circuit. 2 CO3 R
 Input variables changes if the circuit is stable
 Inputs are levels, not pulses
 Only one input can change at a given time
9 Define Pulse mode circuit. 2 CO3 R
 Inputs are pulses
 Widths of pulses are long for circuit to respond to the input
 Pulse width must not be so long that it is still present after the new state is reached
10 List the two steps for the design of asynchronous sequential circuit? 2 CO3 R
 Construction of primitive flow table -reduction of flow table
 State assignment are made -realization of primitive flow table
11 What are races? 2 CO3 R
 When two or more binary state variables change their value in response to a change in
an input variable, race condition occurs in an asynchronous sequential circuit.
 In case of unequaldelays, a race condition may cause the state variables to change in
 an unpredictable manner.
12 Define race around condition. 2 CO3 R
 In JK flip-flop output is fed back to the input. Therefore change in the output results
change in the input.
 Due to this in the positive half of the clock pulse if both J and K are high then output
toggles continuously. This condition is called ‘race around condition’
13 What is edge-triggered flip-flop? 2 CO3 R
 The problem of race around condition can solved by edge triggering flip flop.
 The term edge triggering means that the flip-flop changes state either at the positive
edge or negative edge of the clock pulse and it is sensitive to its inputs only at this
transition of the clock.
14 What is a master-slave flip-flop? 2 CO3 R
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and
the other as a slave.
15 Define rise time. 2 CO3 R
The time required to change the voltage level from 10% to 90% is known as rise time (tr).
16 Define fall time 2 CO3 R
The time required to change the voltage level from 90% to 10% is known as fall time (tf).
17 Define skew and clock skew. 2 CO3 R
The phase shift between the rectangular clock wave forms is referred to as skew and the
time delay between the two clock pulses is called clock skew.
18 .Define setup time. 2 CO3 R
 The setup time is the minimum time required to maintain a constant voltage levels at
the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse
in order for the levels to be reliably clocked into th e flip flop.
 It is denoted as tsetup.
19 Define hold time. 2 CO3 R
 The hold time is the minimum time for which the voltage levels at the excitation inputs
must remain constant after the triggering edge of the clock pulse in order for the levels
to be reliably clocked into the flip flop.
20 Define propagation delay. 2 CO3 R
 A propagation delay is the time required to change the output after the application of
the input.
PART - B
Q.No Questions Marks CO BL
1 Illustrate Master Slave Flip Flop(or) Explain the Master Slave Flip Flop concept using
16 CO3 U
JK FF
A master-slave Flip-Flop is constructed using two separate JK Flip-Flops. The first Flip-
Flop is called the master. It is driven by the positive edge of the clock pulse. The second
Flip-Flop is called the slave.
Race Around Condition In JK Flip-flop:
 For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will
toggle as long as CLK is high, which makes the output of the flip-flop unstable or
uncertain.
 This problem is called race around condition in J-K flip-flop. This problem (Race
Around Condition) can be avoided by ensuring that the clock input is at logic “1” only
for a very short time.
 This introduced the concept of Master Slave JK flip flop.
Working of a master slave flip flop –
 When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the
state of the system. The slave flip-flop is isolated until the CP goes to 0.
 Firstly the master flip flop is positive level triggered and the slave flip flop is negative
level triggered, so the master responds before the slave.
 If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and
the clock forces the slave to reset, thus the slave copies the master.
 If J=1 and K=0, the high Q output of the master goes to the J input of the slave and
the Negative transition of the clock sets the slave, copying the master.
 If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave
toggles on the negative transition of the clock.
 If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
Timing Diagram of a Master flip flop –
  When the Clock pulse is high the output of master is high and remains high till the
clock is low because the state is stored.
 Now the output of master becomes low when the clock pulse becomes high again
and remains low until the clock becomes high again.
 Thus toggling takes place for a clock cycle.
 When the clock pulse is high, the master is operational but not the slave thus the
output of the slave remains low till the clock remains high.
 When the clock is low, the slave becomes operational and remains high until the
clock again becomes low.
 Toggling takes place during the whole process since the output is changing once in a
cycle.
Explain the Parallel in Parallel out and Parallel in Serial Out Shift Register with neat
2 16 CO3 U
diagram.
 The Shift Register is another type of sequential logic circuit that can be used for the
storage or the transfer of binary data.
 A shift register basically consists of several single bit “D-Type Data Latches”, one for
each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain
arrangement so that the output from one data latch becomes the input of the next latch
and so on.
Parallel-in to Serial-out (PISO)
 The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to
parallel-out.
 The data is loaded into the register in a parallel format in which all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register.
 The data is then read out sequentially in the normal shift-right mode from the register
at Q representing the data present at PA to PD.
 This data is outputted one bit at a time on each clock cycle in a serial format.
 It is important to note that with this type of data register a clock pulse is not required to
parallel load the register as it is already present, but four clock pulses are required to
unload the data.
4-bit Parallel-in to Serial-out

 As this type of shift register converts parallel data, such as an 8-bit data word into
serial format
 Iit can be used to multiplex many different input lines into a single serial DATA stream
which can be sent directly to a computer or transmitted over a communications line.
Parallel-in to Parallel-out (PIPO)
 The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of
shift register also acts as a temporary storage device or as a time delay device similar
to the SISO configuration above.
 The data is presented in a parallel format to the parallel input pins P A to PD and then
transferred together directly to their respective output pins QA to QD by the same clock
pulse.
  Then one clock pulse loads and unloads the register. This arrangement for parallel
loading and unloading is shown below.
4-bit Parallel-in to Parallel-out

 The PIPO shift register is the simplest of the four configurations as it has only three
connections , similar to the Serial-in to Serial-out shift register,
 Also, in this type of register there are no interconnections between the individual flip-
flops since no serial shifting of the data is required.
3 Explain Serial in Parallel out and Serial in Serial Out Shift Register (or) Explain the
16 CO3 U
Shift register in synchronous sequential circuit
The Shift Register is another type of sequential logic circuit that can be
used for the storage or the transfer of binary data
Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

 If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the
output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the
other outputs still remaining LOW at logic “0”.
 That the DATA input pin of FFA has returned LOW again to logic “0” giving us one data
pulse or 0-1-0.
 The second clock pulse will change the output of FFA to logic “0” and the output
 of FFB and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA.
 Then the data has been converted from a serial data input signal to a parallel data
output. The truth table and following waveforms show the propagation of the logic “1”
through the register from left to right as follows.

Basic Data Movement through a Shift Register

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

Serial-in to Serial-out (SISO) Shift Register

 This shift register is very similar to the SIPO above, except were before the data was
read directly in a parallel form from the outputs QA to QD, this time the data is allowed
to flow straight through the register and out of the other end.
 Since there is only one output, the DATA leaves the shift register one bit at a time in a
serial pattern, hence the name Serial-in to Serial-Out Shift Register or SISO.
 The SISO shift register is one of the simplest of the four configurations as it has only
three connections, the serial input (SI) which determines what enters the left hand flip-
flop, the serial output (SO) which is taken from the output of the right hand flip-flop and
the sequencing clock signal (Clk).
 4-bit Serial-in to Serial-out Shift Register

Construct any one Synchronous counter and Explain the operation (or)
4 16 CO3 AP
Construct Synchronous up / down counter.
 An up/down counter is a bidirectional counter, capable of progressing in either
direction through a certain sequence.
 A 3-bit binary counter that advances upward through its sequence (0, 1, 2, 3, 4, 5, 6,
7) and then can be reversed so that it goes through the sequence in the opposite
direction (7, 6, 5, 4, 3, 2, 1,0) is an illustration of up/down sequential operation.

Explain the operation and excitation tables of JK Flip Flops.(or) Explain the operation
5 16 CO3 U
and excitation tables of Any one Flip Flops
 JK means Jack Kilby, Texas Instrument (TI) Engineer, who invented
IC in 1958.JK Flip-Flop has two inputs J(set) and K(reset).
 A JK Flip-Flop can be obtained from the clocked SR Flip-Flop by
augmenting two AND gates.

Inputs Output
CLK State
J K Qn+1
 1 0 0 Qn No Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q n’ Toggle

Characteristic table and Characteristic equation

Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
A sequential circuit has two JK Flip-Flops A and B, one input (x) and
one output(y). the Flip-Flop input functions are,
JA= B+ x JB= A’+ x’
KA= 1 KB= 1
6 and the circuit output function, Y= xA’B. 16 CO3 U
a) Draw the logic diagram of the Mealy circuit,
b) Tabulate the state table,
c) Draw the state diagram.
Soln:

Characteristics Equation for JK flip flop: Q = JQ’ + K’Q

QA = JAQ’A + K’AQA = (B+ x) (A’) + 0 = (B+ x)(A’)

QB=JBQ’B + K’BQB = (A’+ x’) (B’) + 0 = (A’+ x’)(B’)

State table:

To obtain the next-state values of a sequential circuit

with JK Flip-Flops, usethe JK Flip-Flop characteristics table.

Present
Input Flip-Flop Inputs Next state Output
state
JA= B+ JB= A’+
KA= 1 KB= 1 A(t+1) B(t+1) Y=
A B x x x’ xA’B
0 0 0 0 1 1 1 0 1 0
0 0 1 1 1 1 1 1 1 0
0 1 0 1 1 1 1 1 0 0
0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 1 1 0 1 0
1 0 1 1 1 0 1 0 0 0
1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 0 1 0 0 0
 Next state Output
Present state
x= 0 x= 1 x= 0 x= 1

A B A B A B y y
0 0 0 1 1 1 0 0
0 1 1 0 1 0 0 1
1 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0
State Diagram:

UNIT IV THE 8086 MICROPROCESSOR

PART- A

Q.No Questions Marks CO BL

1 Show how the clock signal is generated in 8086? What is the maximum internal
2 CO4 R
clock frequency of 8086?
 The 8086 does not have on-chip clock generation circuit. Hence the clock
generator chip, 8284 is connected to the CLK pin of 8086.
 The clock signal supplied by 8284 is divided by three for internal use. The
maximum internal clock frequency of 8086 is 5MHz.
2 List the Features of Von Neumann Architecture. 2 CO4 R
 Instructions and Data are stored in the same memory.
 Instructions and Data share one memory system.
3 List the Features of Harvard Architecture. 2 CO4 R
 Physically separates storage and signal pathway for instructions and data.
 Generally, the bit of Instructions is wider than Data.
 For some computers, the Instruction memory is read-only.
 In cases without caches, the Harvard Architecture is more efficient than von-
Neumann.
4 Define queue? Show How queue is implemented in 8086? 2 CO4 R
 A data structure which can be accessed on the basis of first in first out is called
queue.
 The 8086 has six numbers of 8-bit FIFO registers, which is used for instruction
queue.
5 List the flags of 8086? 2 CO4 R
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

- - - - O D I T S Z - AC - P - CY

The 8086 has nine flags and they are

1. Carry Flag (CF) 6. Overflow Flag (OF)
2. Parity Flag (PF) 7. Trace Flag (TF)
3. Auxiliary carry Flag (AF) 8. Interrupt Flag (IF)
4. Zero Flag (ZF) 9. Direction Flag (DF)
5. Sign Flag (SF)
Describe the difference between the instructions MOV AX, 2437H and MOV
6 2 CO4 R
AX,[2437H]?
Difference between the instructions MOV AX, 2437H and MOV AX,[2437H] are former
instruction takes 2437 as 16-bit data and latter instruction takes 2437 as 16-bit
address.
7 State the function of Direction flag in 8086? 2 CO4 R
 Direction flag is used with string instructions.
 If DF= 0, the string is processed from its beginning with the first element having
the lowest address.
 Otherwise, the string is processed from the high address towards the low address.
Estimate using 8086 processor the code segment contains 4000H and
8 instruction pointer contains 9F20H. Find the memory location addressed by the 2 CO4 R
processor.
Segment address 4000 - 0100 0000 0000 0000
Shifted to left by four bits - 0100 0000 0000 0000 0000
(+) Offset address - 1001 1111 0010 0000
Physical address - - 0100 1001 1111 0010 0000
= 49F20H
 The Calculated Physical address = 49F20H
9 Discuss the functions of the following prefixes: LOCK, ESCAPE 2 CO4 R
LOCK :
 The LOCK prefix allows a microprocessor to make sure that another processor
does not take control of the system bus while it is in the middle of a critical
instruction which uses the system bus.
ESCAPE:
 This instruction is used to pass instructions to a coprocessor such as the 8087
math coprocessor which shares the address and data bus with an 8086.
10 Show the memory representation of 8051. 2 CO4 R
11 List the two hardware interrupts of 8086 2 CO4 R
 The interrupts of 8085 are INTR and NMI.
 The INTR is general maskable interrupt and NMI is non-maskable interrupt.
12 Define pipelined architecture 2 CO4 R
 In pipelined architecture the processor will have number of functional units and
the execution time of functional units is overlapped.
 Each functional unit works independently most of thetime.
13 Difference between segment register and general purpose register 2 CO4 R
 The segment registers are used to store 16 bit segment base address of the four
memory segments.
 The general purpose registers are used as the source or destination register
duringdata transfer and computation, as pointers to memory and as counters.
14 What is queue? How queue is implemented in 8086? 2 CO4 R
 A data structure which can be accessed on the basis of first in first out is called
queue.
 The 8086 has six numbers of 8-bit FIFO registers, which is used for instruction
queue.
15 List few flag manipulation instructions of 8086? 2 CO4 R
 LAHF : Load AH from low byte of flag register.
 SAHF : Store AH to low byte of flag register
 PUSHF : Push content of flag to the stack.
 POPF : Pop content of stack and load it in the flag register.
16 List the purpose of AD0 – AD15 lines 2 CO4 R
 These are the time multiplexed memory 15 address and data lines.
 Address remains on the line during TI state, while data is available on the data
bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and Tw are the clock states of
a machine cycle. Tw is a wait state.
 These lines are active high and float to a tristate during interrupt acknowledge
and local bus hold acknowledge cycles.
17 Define the operation of RD signal 2 CO4 R
Read signal RD when low, indicates the peripherals that the processor is performing
a memory (or) I/O read operation.
18 What is the function of INTR signal? 2 CO4 R
 INTR- Interrupt Request: This is a level triggered input. This is sampled during the
last clock cycle of each instruction to determine the availability of the request, If
any interrupt request is pending, the processor enters the interrupt acknowledge
cycle.
  This can be internally masked by resetting he interrupt enable flag. This signal is
active high and internally synchronized.
19 What is the operation performed when TEST input pin is low? 2 CO4 R
If the TEST input goes low, execution will continue, else, the processor remains in
an idle state.The input is synchronized internally during each clock cycle on leading
edge of clock.
20 Differences between maximum mode and minimum mode 2 CO4 R

PART- B
Q.No Questions Marks CO BL
Explain the architecture of 8086 processor with neat diagram.(or) Enumerate the
1 16 CO4 U
details of 8086 microprocessor with neat diagram of Harvard Architecture.

Intel 8086 was launched in 1978.

 It was the first 16-bit microprocessor.
 This microprocessor had major improvement over the execution speed of 8085.
 It is available as 40-pin Dual-Inline-Package (DIP).
 It is available in three versions:
 a. 8086 (5 MHz)
b. 8086-2 (8 MHz)
c. 8086-1 (10 MHz)
ü It consists of 29,000 transistors.
Bus Interface Unit (BIU):
The function of BIU is to
 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
 Read data from the port.
Instruction Queue:
 To increase the execution speed, BIU fetches as many as six instruction bytes
ahead to time from memory.
 All six bytes are then held in first in first out 6 byte register called instruction queue.
 Then all bytes have to be given to EU one by one.
 This pre fetching operation of BIU may be in parallel with execution operation of EU,
which improves the speed execution of the instruction.
Execution Unit (EU):
The functions of execution unit are
 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions
General Purpose Registers of 8086:
These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to
have AX, BX, CX, and DX.
Segment Registers:
Additional registers called segment registers generate memory address when
combined with other in the microprocessor. In 8086 microprocessor, memory is divided into 4
segments as follow:
 Code Segment (CS)
 Data Segment (DS)
 Extra Segment (ES)
Flag Registers of 8086:

Flags Register determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine the type of the
result, and to determine conditions to transfer control to other parts of the program. 8086 has
9 flags and they are divided into two categories:
Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed. Conditional
flags are as follows:
 Carry Flag (CF)
 Auxiliary Flag (AF)
 Parity Flag (PF)
 Zero Flag (ZF)
 Sign Flag (SF)
 Overflow Flag (OF)
Control Flags:
Control flags are set or reset deliberately to control the operations of the execution unit.
 Control flags are as follows:
 Trap Flag (TP)
 Interrupt Flag (IF)
 Direction Flag (DF)
Summarize the minimum mode configuration of 8086 microprocessor with neat
2 16 CO4 U
sketch. (or) Explain the block description of 8086 microprocessor when MN/MX’ = 1.
The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.
 In minimum mode, 8086 is the only processor in the system which provides all the
control signals which are needed for memory operations and I/O interfacing.
 Here the circuit is simple but it does not support multiprocessing.
8282 (8 bits) latch :
 The latches are buffered D FF. They are used to separate the valid address from the
multiplexed Address/data bus by using the control signal ALE, which is connected to
strobe (STB) of 8282.

bits) transceivers :
8286 (8
 They are bidirectional buffers and also known as data amplifiers.
 They are used to separate the valid data from multiplexed add/data bus.
 Two such transceivers are needed because the data bus is 16 bits long.
 8286 is connected to DT/R’ and DEN’ signals. They are enabled through the DEN
signal.
 The direction of data on the data bus is controlled by the DT/R’ signal. DT/R’ is
connected to T and DEN’ is connected to OE’.
 Direction of data flow
 8284 clock generator is used to provide the clock.
 M/IO’= 1,then I/O transfer is performed over the bus. and when M/IO’ = 0, then I/O
operation is performed.
 The signals RD’ and write WR’ are used to identify whether a read bus cycle or a write
bus cycle is performing. When WR’ = 0 ,then it indicates that valid output data on the
data bus.

INTR and INTA :

 When INTR = 1, then there is an interrupt to 8086 by other devices for their
service. When INTA’= 0, then it indicates that the processor is ready to service
them.
 The bus request is made by other devices using the HOLD signal and the
processor acknowledges them using the HLDA output signal.
Summarize the maximum mode configuration of 8086 microprocessor with neat
3 16 CO4 U
sketch. (or) Explain the block description of 8086 microprocessor when MN/MX = 0.
 It contains 20 bit address bus.
 It contains 16-bit data bus, therefore 8086 is called as 16-bit microprocessor.
8086 has two operating Modes:
1. Minimum mode
2. Maximum mode
Minimum mode:
 In this 8086 is the only processor in the system. In a minimum mode 8086 system.
 8086 is operated in minimum mode when MN/MX’ pin to logic 1.
 In this mode, all the control signals are given out by the 8086 itself.
Maximum mode:
 In this we can connect more processors to 8086 (8087/8089).
 8086 max mode is basically for implementation of allocation of global resources and
passing bus control to other coprocessor (i.e. second processor in the system),
because two processors cannot access system bus at same instant.
 All processors execute their own program.
 The resources which are common to all processors are known as global resources.
 The resources which are allocated to a particular processor are known as local or
private resources.
Circuit explanation:
 When MN/ MX’ = 0, 8086 works in max mode.
  Clock is provided by 8284 clock generator.
8288 bus controller-
 Address form the address bus is latched into 8282 8-bit latch. Three such latches
are required because address bus is 20 bit.
 The ALE (Address latch enable) is connected to STB (Strobe) of the latch. The
ALE for latch is given by 8288 bus controller.
 The data bus is operated through 8286 8-bit transceiver. Two such transceivers
are required, because data bus is 16-bit.
 The transceivers are enabled the DEN signal, while the direction of data is
controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected
to T. Both DEN and DT/ R’ are given by 8288 bus controller.

Control signals for all operations are generated by decoding S’2, S’1 and
S’0 using 8288 bus controller.
  Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0 /GT0 has more
priority than RQ1/GT1.
 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
Show the timing diagram of minimum mode in 8086 microprocessor with detail
4 explanation. (or) Explain the 8086 microprocessor in minimum mode configuration 16 CO4 U
with neat timing diagram.
The working of min mode can be easily understood by timing diagrams.
 All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is given by
processor in the T1 state. It is available on the bus for one T-state.
 In T2, the bus is tristated for changing the direction of the bus ( in the case of a data
read cycle.)
 The data transfer takes place between T3 and T4 .
 If the addressed device is slower, then the wait state is inserted between T3 and T4.

Opcode fetch or read timing diagram

  At T1 state ALE =1, this indicates that a valid address is latched on the address bus
and also M / IO’= 1, which indicates the memory operation is in progress.
 In T2, the address is removed from the local bus and is sent to the addressed device.
Then the bus is tristated.
 When RD’ = 0 , the valid data is present on the data bus.
 During T2 DEN’ =0, which enables transceivers and DT/R’ = 0, which indicates that the
data is received.
 During T3, data is put on the data bus and the processor reads it.
 The output device makes the READY line high. This means the output device has
performed the data transfer process. When the processor makes the read signal to 1,
then the output device will again tristate its bus drivers.

Write memory cycle

 At T1 state ALE =1, this indicates that a valid address is latched on the address bus
and also M / IO’= 1, which indicates the memory operation is in progress.
 In T2, the processor sends the data to be written to the addressed location.
 The data is buffered on the bus until the middle of T4 state.
 The WR’=0 becomes at the beginning of T2.
 The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O word.
 During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1, which indicates that
the data is transferred by the processor to the addressed device.
5 Explain the functions of 8086 microprocessor pin diagram in detail (or) Explain the 16 CO4 U
signal description of 8086 microprocessor in detail
Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V
DC supply for its operation. The 8086 uses 20-line addresses bus. It has a 16-line data
bus.
 AD0-AD15: Address/Data bus. These are low order address bus. They are
multiplexed with data.
 A16-A19: High order addresses bus. These are multiplexed with status signals.
 S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is
 returned to passive state (1,1,1 during T3 or Tw (when ready is inactive).
Pin diagram of 8086 microprocessor is as given below:

S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

 A16/S3, A17/S4, A18/S5, and A19/S6: The specified address lines are multiplexed
with corresponding status signals.

A17/S4 A16/S3 Function

0 0 Extra segment access

 0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

 BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is used to enable data onto
the most significant half of data bus, D8-D15.
 RD’: This is used for read operation. It is an output signal. It is active when low.
 READY : This is the acknowledgement from the memory or slow device that they have
completed the data transfer.
 INTR : Interrupt Request. This is triggered input. This is sampled during the last clock
cycles of each instruction for determining the availability of the request.
 NMI : Non maskable interrupt. This is an edge triggered input which results in a type II
interrupt.
 INTA : Interrupt acknowledge. It is active low (0) during T2, T3 and Tw of each
interrupt acknowledge cycle.
 MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.
 RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used
to force the microprocessor to release the local bus at the end of the microprocessor’s
current bus cycle.
 LOCK’ : Its an active low pin. It indicates that other system bus masters have not
been allowed to gain control of the system bus while LOCK’ is active low(0).
 TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution
will continue, else the processor remains in an idle state.
 CLK : Clock Input. The clock input provides the basic timing for processing operation
and bus control activity. Its an asymmetric square wave with a 33% duty cycle.
 RESET : This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high(1) for at least four clock cycles.
 Vcc : Power Supply( +5V D.C.)
 GND : Ground
 QS1, QS0: Queue Status. These signals indicate the status of the internal 8086
instruction queue according to the table shown below

QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

 DT/R : Data Transmit/Receive. The direction of data flow is controlled through the
transceiver.
  DEN : Data enable. DEN is active low(0) during each memory and input-output access
and for INTA cycles.
 HOLD/HOLDA : HOLD indicates that another master has been requesting a local bus
.This is an active high(1). The microprocessor receiving the HOLD request will issue
HLDA (high) as an acknowledgement in the middle of a T4 or T1 clock cycle.
 ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the
address into the 8282 or 8283 address latch.
6. Show the timing diagram of maximum mode in 8086 microprocessor with detail
explanation. (or) Explain the 8086 microprocessor in maximum mode configuration
with neat timing diagram.
 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
 In this mode, the processor derives the status signal S2, S1, S0.
 Another chip called bus controller derives the control signal using this status information.
 In the maximum mode, there may be more than one microprocessor in the system
configuration. The components in the system are same as in the minimum mode system.
 The basic function of the bus controller chip IC8288 is to derive control signals like RD
and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the
processor on the status lines.
 The bus controller chip has input lines S2, S1, S0 and CLK.
 These inputs to 8288 are driven by CPU. It derives the outputs ALE, DEN, DT/R, MRDC,
MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are especially
useful for multiprocessor systems.
 AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of
the MCE/PDEN output depends upon the status of the IOB pin. INTA pin used to issue
two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.
 IORC, IOWC are I/O read command and I/O write command signals respectively. These
signals enable an IO interface to read or write the data from or to the address port.
 The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
 All these command signals instructs the memory to accept or send data from or to the
bus. Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals.
 R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse
as on the ALE and apply a required signal to its DT / R pin during T1.
 In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4.
 For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is
activated from T3 to T4. The status bit S0 to S2 remains active until T3 and become
passive during T3 and T4. If reader input is not activated before T3, wait state will be
inserted between T3 and T4.
 UNIT V ASSEMBLY LANGUAGE PROGRAMMING AND INTERFACING APPLICATIONS
PART- A
Q.No Questions Marks CO BL
1 Observe the need for a Port. 2 CO5 R
 The I/O devices are generally slow devices and their timing characteristics do not
match withprocessor timings.
 Hence the I/O devices are connected to system bus through the ports.
2 Define the operation of handshake input port. 2 CO5 R
 In handshake input operation, the input device will check whether the port is empty or
not. If the port is empty, then the data is loaded into the port.
 When the port receives the data, it will inform the processor for read operation.
 Once the data have been read by the processor, the port will signal the input device
that it is empty.
 Now the input device can load another data to portand the above process is repeated.
3 List the three operating modes of port -A 8255 2 CO5 R
The port-A of 8255 can be programmed to work in anyone of the following operating
modes asinput or output port.
Mode-0 : Simple 1/0 port. Mode-l: Handshake 1/0 port Mode-2: Bidirectional 1/0 port
4 Classify the different scan modes of 8279 2 CO5 R
The different scan modes of 8279 are Decoded scan and Encoded scan.
 In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
 In encoded scan mode, the output of scan lines will be binary count, and so an
external decodershould be used to convert the binary count to decoded output.
5 Show I/O mode format for 8255 2 CO5 R

6 Define debouncing 2 CO5 R

 When a key is pressed, it bounces after a short time.
 If a key code is generated immediately after sensing a key actuation, then the
processor will generate the same key code a number of times. (A key typically
bounces for 10 to 20 msec).
 Hence the processor has to wait for the key bounces to settle before reading the
keycode. This process is called keyboard debouncing.
7 Show the tasks involved in keyboard interface 2 CO5 R
 The tasks involved in keyboard interfacing are sensing a key actuation, debouncing the
key and generating key codes (Decoding the key).
 These tasks are performed by software if the keyboard is interfaced through ports and
they are performed by hardware if the keyboard is interfaced through 8279.
8 Discuss 2-key lockout and N-key rollover? 2 CO5 R
 2-Key Lockout: When two keys are pressed simultaneously, one key pressed first
will berecognized and code will be generated.
 N-Key Rollover: When a key is pressed continuously, the same key will be
recognized severaltimes, after each debounce.
9 What is scanning in display and what is the scan time? 2 CO5 R
In display devices, the process of sending display codes to 7 –segment LEDs to display
the LEDs one by one is called scanning (or multiplexed display). The scan time is the time
taken to display all the 7-segment LEDs one by one, starting from first LED and coming
back to the first LED again
10 List few functions performed by 8279. 2 CO5 R
 Keyboard scanning.
 Keyboard debouncing.
 Keycode generation.
 Intimating key pressing to CPU through Interrupt.
 Storing display codes.
 Output display codes to LED/LCDs.
 Display refreshing.
11 What are the functions performed by port-C of 8255? 2 CO5 R
 The port-C pins are used for handshake signals.
 Port-C can be used as an 8-bit parallel 1/0 port in mode-0.
 It can be used as two numbers of 4-bit parallel port in mode-0.
 The individual pins of port-C can be set or reset for various control applications.
12 Define programmable peripheral device? 2 CO5 R
 If the functions performed by a peripheral device can be altered or changed by a
program instruction then the peripheral device is called programmable device.
 Usually the programmable devices will have control registers. The device can be
programmed by sending control word inthe prescribed format to the control register.
13 Show the control word format for BSR (Bit Set Reset) Mode. 2 CO5 R

14 Show the addressing mode of MOV AX, 55H (BX) (SI) ? 2 CO5 R
MOV AX, 55H (BX) (SI) – Base Indexed memory addressing mode
15 Write an assembly language program to load the accumulator with a constant value. 2 CO5 U
MACRO invert value
if (value==0)
MOV A, #1
Else clr A
end if
END MAC.
 16 How are constants declared? 2 CO5 R
Constants are declared in the same way as variables, using the format: Const–Label EQU
012h
When the constants label is encountered, the constant numeric value is exchanged for the
string
Write a program to add a data byte located at offset 0500H in 2000H segment to
17 another data byte available at 0600H in the same segment and store the result at 2 CO5 U
0700H in the same segment.
MOV AX, 2000H; initialize DS with value
MOVDS, AX; 2000H
MOV AX, [500H]; Get first data byte from 0500H offset
ADD AX, [600H]; Add this to the second byte from 0600H
MOV [700H], AX; store AX in 0700H
HLT; Stop.
18 List the eight types of addressing modes of 8086 instruction set? 2 CO5 R
The different addressing modes are:
 Immediate
 Direct
 Register
 Register indirect
 Indexed
 Register relative
 Based indexed
 Relative based indexed
19 List the eight types of instructions in 8086 microprocessor? 2 CO5 R
The different types of instructions in 8086 microprocessor are:
 Data copy / transfer instructions
 Arithmetic and logical instructions
 Branch instructions
 Loop instruction
 Machine control instruction
 Flag manipulation instruction
 Shift and rotate instruction
 String instruction
20 What is assembly level programming? 2 CO5 R
 A program called assembler is used to convert the mnemonics of instruction and data
into their equivalent object code modules.
 The object code modules are further converted into executable code using linker and
loader programs.
 This type of programming is called assembly level programming.

PART- B
Q.No Questions Marks CO BL
Explain the addressing modes of 8086 microprocessor in detail (or) Enumerate the
1 16 CO5 U
different types of 8086 addressing modes with examples.
The way of specifying data to be operated by an instruction is known as addressing
modes. This specifies that the given data is an immediate data or an address. It also
specifies whether the given operand is register or register pair.
Types of addressing modes:
 Register mode – In this type of addressing mode both the operands are registers.
Example:
MOV AX, BX
XOR AX, DX
 Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16
bit data. Destination operand can never be immediate data.
Example:
MOV AX, 2000
MOV CL, 0A
 Note that to initialize the value of segment register an register is required.
MOV AX, 2000
MOV CS, AX
 Displacement or direct mode – In this type of addressing mode the effective address
is directly given in the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]
 Register indirect mode – In this addressing mode the effective address is in SI, DI or
BX.
Example: Physical Address = Segment Address + Effective Address
MOV AX, [DI]
ADD AL, [BX]
 Based indexed mode – In this the effective address is sum of base register and index
register.
Base register: BX, BP
Index register: SI, DI
 The physical memory address is calculated according to the base register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]
 Indexed mode – In this type of addressing mode the effective address is sum of index
register and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
 Based mode – In this the effective address is the sum of base register and
displacement.
Example:
MOV AL, [BP+ 0100]
 Based indexed displacement mode – In this type of addressing mode the effective
address is the sum of index register, base register and displacement.
Example:
MOV AL, [SI+BP+2000]
 String mode – This addressing mode is related to string instructions. In this the value
of SI and DI are auto incremented and decremented depending upon the value of
directional flag.
Example:
MOVS B
MOVS W
 Input/Output mode – This addressing mode is related with input output operations.
Example:
IN A, 45
 OUT A, 50
 Relative mode –
In this the effective address is calculated with reference to instruction pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address
Explain the instruction set of 8086 microprocessor in detail (or) Enumerate the
2 16 CO5 U
different types of 8086 instruction set with examples.
The 8086 microprocessor supports 8 types of instructions −
 Data Transfer Instructions
 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions
Data Transfer Instructions
These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group −
Instruction to transfer a word
 MOV − Used to copy the byte or word from the provided source to the provided
destination.
 PPUSH − Used to put a word at the top of the stack.
Instructions for input and output port transfer
 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the provided port.
Instructions to transfer the address
 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
Arithmetic Instructions
These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.
Following is the list of instructions under this group −
Instructions to perform addition
 ADD − Used to add the provided byte to byte/word to word.
 ADC − Used to add with carry.
Instructions to perform subtraction
 SUB − Used to subtract the byte from byte/word from word.
 SBB − Used to perform subtraction with borrow.
Instruction to perform multiplication
 MUL − Used to multiply unsigned byte by byte/word by word.
 IMUL − Used to multiply signed byte by byte/word by word.
Instructions to perform division
 DIV − Used to divide the unsigned word by byte or unsigned double word by word.
 IDIV − Used to divide the signed word by byte or signed double word by word.
Bit Manipulation Instructions
These instructions are used to perform operations where data bits are involved, i.e.
operations like logical, shift, etc.
Following is the list of instructions under this group −
Instructions to perform logical operation
 NOT − Used to invert each bit of a byte or word.
 AND − Used for adding each bit in a byte/word with the corresponding bit in another
 byte/word.
Instructions to perform shift operations
 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential order.
Following is the list of instructions under this group −
 REP − Used to repeat the given instruction till CX ≠ 0.
 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
Program Execution Transfer Instructions (Branch and Loop Instructions)
These instructions are used to transfer/branch the instructions during an execution. It
includes the following instructions −
Instructions to transfer the instruction during an execution without any condition −
 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
Processor Control Instructions
These instructions are used to control the processor action by setting/resetting the flag
values.
Following are the instructions under this group −
 STC − Used to set carry flag CF to 1
 CLC − Used to clear/reset carry flag CF to 0
Iteration Control Instructions
These instructions are used to execute the given instructions for number of times. Following
is the list of instructions under this group −
 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX =
0.
Interrupt Instructions
These instructions are used to call the interrupt during program execution.
 INT − Used to interrupt the program during execution and calling service specified.
 INTO − Used to interrupt the program during execution if OF = 1.
Explain the Keyboard and Display interface of 8086 microprocessor in detail (or)
3 16 CO5 U
Summarize the interfacing of 8279 and microprocessor 8086 with neat diagram
8279 programmable keyboard/display controller is designed by Intel that interfaces a
keyboard with the CPU. The keyboard first scans the keyboard and identifies if any key has
been pressed.
The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt
mode, the processor is requested service only if any key is pressed, otherwise the CPU will
continue with its main task.
 In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether
any key is pressed or not with key pressure.
 The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using
the key-codes. These key-codes are de-bounced and stored in an 8-byte FIFORAM,
which can be accessed by the CPU.
 If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode
else the CPU checks the status in polling to read the entry.
 I/O Control and Data Buffer
 This unit controls the flow of data through the microprocessor.
 It is enabled only when D is low. Its data buffer interfaces the external bus of the system
with the internal bus of the microprocessor.
 The pins A0, RD, and WR are used for command, status or data read/write operations.
Control and Timing Register and Timing Control
  This unit contains registers to store the keyboard, display modes, and other operations
as programmed by the CPU. The timing and control unit handles the timings for the
operation of the circuit.

Architecture and Description

Scan Counter
 It has two modes i.e. Encoded mode and Decoded mode.
 In the encoded mode, the counter provides the binary count that is to be externally
decoded to provide the scan lines for the keyboard and display.
 In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3.
 Return Buffers, Keyboard Debounce, and Control
 This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is
directly transferred to the sensor RAM along with SHIFT & CONTROL key status.
FIFO/Sensor RAM and Status Logic
 This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed
key is entered into the RAM as per their sequence. The status logic generates an
interrupt request after each FIFO read operation till the FIFO gets empty.
 In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is
loaded with the status of their corresponding row of sensors into the matrix. When the
sensor changes its state, the IRQ line changes to high and interrupts the CPU.
Display Address Registers and Display RAM
 This unit consists of display address registers which holds the addresses of the word
currently read/written by the CPU to/from the display RAM.
4 Explain the Programmable Peripheral interface of 8086 microprocessor in detail (or)
Summarize the interfacing of 8255 PPI and microprocessor 8086 with neat diagram 16 CO5 U
PPI 8255 is a general purpose programmable I/O device designed to interface the CPU
with its outside world such as ADC, DAC, keyboard etc.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C.
Block diagram –
 It consists of 40 pins and operates in +5V regulated power supply.
 Port C is further divided into two 4-bit ports i.e. port C lower and port C upper and port
C can work in either BSR (bit set rest) mode or in mode 0 of input-output mode of
8255.
 Port B can work in either mode 0 or in mode 1 of input-output mode. Port A can work
either in mode 0, mode 1 or mode 2 of input-output mode.
 It has two control groups, control group A and control group B. Control group A consist
of port A and port C upper. Control group B consists of port C lower and port B.
CS’ A1 A0 Selection Address

0 0 0 PORT A 80 H

0 0 1 PORT B 81 H

0 1 0 PORT C 82 H

0 1 1 Control Register 83 H

1 X X No Seletion X
Pin diagram –

 PA0 – PA7 – Pins of port A

 PB0 – PB7 – Pins of port B
 PC0 – PC7 – Pins of port C
 D0 – D7 – Data pins for the transfer of data
 RESET – Reset input
 RD’ – Read input
 WR’ – Write input
 CS’ – Chip select
 A1 and A0 – Address pins
Operating modes –
1. Bit set reset (BSR) mode –
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits
are used for set or reset.

2. Input-Output mode –
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided
into three modes:
  Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input
function or simple output function. In this mode there is no interrupt handling
capacity.
 Mode 1 – Handshake I/O mode or strobed I/O mode. In this mode either port A
or port B can work as simple input port or simple output port, and port C bits are
used for handshake signals before actual data transmission.

 Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B
can work either in mode 0 or mode 1. 6 bits port C are used as handshake signals.
It also has interrupt handling capacity.
5 Write a program in ALP to interface stepper motor to 8086 and rotate it in Clockwise
and anti-clockwise direction. 16 CO5 AP
Program:

START : MOV DI, 1200H

Initialize memory location to store the array of number
MOV CX, 0004H
LOOP 1 : MOV AL,[DI]
Initialize array size
OUT 0C0,AL
Copy the first data in AL
MOV DX, 1010H
Send it through port address
L1 : DEC DX
Introduce delay
JNZ L1
Go to next memory location
INC DI
Loop until all the data’s have been sent
LOOP LOOP1
Go to start location for continuous
JMP START
rotation

1200 : 09,05,06,0A - Clock wise rotation - Array of data’s

1200 : 0A,06,05,09 - Anticlock wise rotation - Array of data’s

Clockwise Anti Clockwise
09 0A
04 06
 06 04
0A 09
6 Write a program in ALP to interface 8255 and to perform traffic light Controller. 16 CO5 AP

CONTROL EQU 0FF0FH

PORT A EQU 0FF0CH
PORT B EQU 0FF0DH
PORT C EQU 0FF0EH

START : MOV AL,80H

OUT CNTRL,AL
REPEAT: MOV BX,1073
MOV SI,LABEL
CALL OUT
MOV AL,[SI]
OUT PORTA, AL
CALL DELAY1
INC SI
INC BX
CALL OUT
MOV AL, [SI]
OUT PORTB, AL
CALL DELAY1
INC SI
INC BX
CALL OUT
MOV AL, [SI]
OUT PORTC, AL
CALL DELAY1
INC SI
INC BX
CALL OUT
MOV AL, [SI]
OUT PORTC, AL
INC SI
MOV AL, [SI]
OUT PORTA, AL
CALL DELAY 1
JMP REPEAT

OUT: MOV AL, [BX]

OUT
PORTC, AL
INC BX
R – Remember, U – Understand, AP – Apply, AZ – Analyze, E – Evaluate, C- Create .