Fabricaion of Micro-electro-mechanial systems(MEMS)

Introduction

Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors,

actuators, and electronics on a common silicon substrate through micro fabrication technology.
Microelectronic integrated circuits can be thought of as the "brains" of a system and MEMS
augments this decision-making capability with "eyes" and "arms", to allow microsystems to sense
and control the environment. Sensors gather information from the environment through measuring
mechanical, thermal, biological, chemical, optical, and magnetic phenomena. The electronics then
process the information derived from the sensors and through some decision making capability direct
the actuators to respond by moving, positioning, regulating, pumping, and filtering, thereby
controlling the environment for some desired outcome or purpose. While the electronics are
fabricated using integrated circuit (IC) process sequences, the micromechanical components are
fabricated using compatible "micro machining" processes. Because MEMS devices are manufactured
using batch fabrication techniques similar to those used for integrated circuits, unprecedented levels
of functionality, reliability, and sophistication can be placed on a small silicon chip at a relatively low
cost.
MEMS promises to revolutionize nearly every product category by bringing together silicon-based
microelectronics with micro machining technology, making possible the realization of complete
systems-on-a-chip. MEMS is an enabling technology allowing the development of smart products,
augmenting the computational ability of microelectronics with the perception and control capabilities
of micro sensors and micro actuators and expanding the space of possible designs and applications.

There are numerous possible applications for MEMS . As a breakthrough technology, allowing
unparalleled synergy between previously unrelated fields such as biology and microelectronics, many
new MEMS applications will emerge, expanding beyond that which is currently identified or
known. Some of the areas of applications are as follows:
Biotechnology: MEMS is enabling new discoveries in science and engineering such as the
Polymerize Chain Reaction (PCR) microsystems for DNA amplification and identification,
micromachined Scanning Tunneling Microscopes (STMs), biochips for detection of hazardous
chemical and biological agents, and microsystems for high-throughput drug screening and selection.
Communications: High frequency circuits consisting of inductors, tunable capacitors, switches, etc.,
can be improved significantly compared to their integrated counterparts if they are made using
MEMS. With the integration of such components, improved performance of communication circuits
with minimum total circuit area, power consumption and cost are obtained. The demonstrated
samples of mechanical switches have quality factors much higher than anything previously available.
Reliability and packaging of RF-MEMS components seem to be the two critical issues that need to be
solved before they receive wider acceptance by the market.
Accelerometers: MEMS accelerometers are quickly replacing conventional accelerometers for crash
air-bag deployment systems in automobiles. MEMS have made it possible to integrate the
accelerometer and electronics onto a single silicon chip. These MEMS accelerometers are much
smaller, more functional, lighter, more reliable, and are produced for a fraction of the cost of the
conventional macro scale accelerometer elements.
Fabrication of MEMS

MEMS devices are extremely small. For example, MEMS has made possible electrically driven
motors smaller than the diameter of a human hair. But MEMS is not primarily about size, or making
things out of silicon. Instead the deep insight of MEMS is as a new manufacturing technology, a way
of making complex electromechanical systems using batch fabrication techniques similar to those
used for integrated circuits, and uniting these electromechanical elements together with electronics.
MEMS is an extremely diverse technology ranging from commercial and military products to in-
dwelling blood pressure monitoring, to active suspension systems for automobiles while at the same
time exhibiting better performance and with reduced cost.
Many of the methods used in the fabrication of MEMS are borrowed from the integrated circuit
industry, in addition to a few others developed specifically for silicon micro machining. The use of
process equipments and large number of fabrication processes developed for the semiconductor
industry was sufficient to overcome the massive infrastructure requirement for MEMS industry. A
few specialized processes such as anisotropy chemical wet etching, wafer bonding, deep reactive ion
etchings or sacrificial etching emerged over the years and remained confined to micromachining in
their application.
MEMS technology is based on a number of tools and methodologies, which are used to form small
structures with dimensions in the micrometer scale (one millionth of a meter). Significant parts of the
technology have been adopted from integrated circuit (IC) technology. For instance, almost all
devices are built on wafers of silicon, like ICs. The structures are realized in thin films, which are
patterned using photolithographic methods.
 There are three basic building blocks in MEMS technology: the ability to deposit thin films of
material on a substrate; to apply a patterned mask on top of the films by photolithographic imaging;
and to etch the films selectively to the mask. A MEMS process is usually a structured sequence of
these operations to form actual devices. Epitaxy, sputtering, evaporation, chemical vapor deposition,
and spin-on methods are common techniques used to deposit uniform layers of silicon, metals,
insulators, or polymers. Lithography is a photographic process for printing images onto a layer of
photosensitive polymer (photoresist) that is subsequently used as a protective mask against etching.
Wet and dry etching, including deep reactive ion etching, forms the essential process base to
selectively remove material. The following sections describe the fundamentals of each of the basic
process tools.
Deposition Processes
One of the basic building blocks in MEMS processing is the ability to deposit thin films of
material. In this text we assume a thin film to have a thickness anywhere between a few nanometer to
about 100 micrometer. The film can subsequently be locally etched using processes described in the
Lithography and Etching sections of this guide.
MEMS deposition technology can be classified in two groups:
1. Depositions that happen because of a chemical reaction:
➢ Chemical Vapor Deposition (CVD)
➢ Electrodeposition
➢ Epitaxy
➢ Thermal oxidation
These processes exploit the creation of solid materials directly from chemical reactions in gas and/or
liquid compositions or with the substrate material. The solid material is usually not the only product
formed by the reaction. Byproducts can include gases, liquids and even other solids.
2. Depositions that happen because of a physical reaction:
➢ Physical Vapor Deposition (PVD)
➢ Casting
Common for all these processes are that the material deposited is physically moved on to the
substrate. In other words, there is no chemical reaction, which forms the material on the substrate.
This is not completely correct for casting processes, though it is more convenient to think of them
that way.
Chemical Vapor Deposition (CVD)
Chemical vapor deposition (CVD) works on the principle of initiating a chemical reaction in a
vacuum chamber, resulting in the deposition of a reacted species on a heated substrate. In this
process, the substrate is placed inside a reactor to which a number of gases are supplied. The
fundamental principle of the process is that a chemical reaction takes place between the source gases.
The product of that reaction is a solid material with condenses on all surfaces inside the reactor.
Common thin films deposited by CVD include polysilicon, silicon oxides and nitrides, tungsten,
titanium and tantalum as well as their nitrides, and most recently, copper and low permittivity
dielectric insulators. The latter two are becoming workhorse materials for very high-speed electrical
interconnects in integrated circuits. The deposition of polysilicon, silicon oxides and nitrides is
routine within the MEMS industry. Chemical vapor deposition processes are categorized as
atmospheric pressure (referred to as CVD), low-pressure (LPCVD), and plasma-enhanced (PECVD),
which also encompasses high-density plasma (HDP-CVD).
The LPCVD process (figure 1) produces layers with excellent uniformity of thickness and material
characteristics. The main problems with the process are the high deposition temperature (higher than
600°C) and the relatively slow deposition rate. The PECVD process can operate at lower
temperatures (down to 300° C). The extra energy supplied to the gas molecules by the plasma in the
reactor also assists the deposition process. However, the quality of the films tends to be inferior to
processes running at higher temperatures. Secondly, most PECVD deposition systems can deposit the
material only on one side of the wafers, that too on 1 to 4 wafers at a time. LPCVD systems deposit
films on both sides of at least 25 wafers at a time. A schematic diagram of a typical LPCVD reactor is
shown in the figure below.

Figure 1: Schematic of a typical hot-wall LPCVD reactor.

 CVD processes are ideal for a thin film with good step coverage. A variety of materials can be
deposited with this technology. However, some of them are less popular with fabrication because of
hazardous byproducts formed during processing. The quality of the material varies from process to
process, however a good rule of thumb is that higher process temperature yields a material with
higher quality and less defects.
Electrodeposition
This process is also known as "electroplating" and is typically restricted to electrically conductive
materials. There are basically two technologies for plating: Electroplating and Electroless plating. In
the electroplating process the substrate is placed in a liquid solution (electrolyte). When an electrical
potential is applied between a conducting area on the substrate and a counter electrode (usually
platinum) in the liquid, a chemical redox process takes place resulting in the formation of a layer of
material on the substrate and usually some gas generation at the counter electrode.
In the electroless plating process a more complex chemical solution is used, in which deposition
happens spontaneously on any surface, which forms a sufficiently high electrochemical potential with
the solution. This process is desirable since it does not require any external electrical potential and
contact to the substrate during processing. Unfortunately, it is also more difficult to control with
regards to film thickness and uniformity. A schematic diagram of a typical setup for electroplating is
shown in the figure 2 below.
The electrodeposition process is well suited to make films of metals such as copper, gold and
nickel. The films can be made in any thickness from ~1µm to >100µm. The deposition is best
controlled when used with an external electrical potential, however, it requires electrical contact to
the substrate when immersed in the liquid bath. In any process, the surface of the substrate must have
an electrically conducting coating before the deposition can be done.

Figure 2: Typical setup for electrodeposition.

Epitaxy
This technology is quite similar to what happens in CVD processes, however, if the substrate
is an ordered semiconductor crystal (i.e. silicon, gallium arsenide), it is possible with this process to
continue building on the substrate with the same crystallographic orientation with the substrate acting
as a seed for the deposition. If an amorphous/polycrystalline substrate surface is used, the film will
also be amorphous or polycrystalline. Epitaxy is a common deposition method to grow a crystalline
silicon layer over a silicon wafer, but with a differing dopant type and concentration. The epitaxial
layer is typically 1- 20 μm thick. It exhibits the same crystal orientation as the underlying crystalline
substrate, except when grown over an amorphous material. Epitaxy is a widely used step in the
fabrication of CMOS circuits, and has proven efficient in forming wafer-scale p-n junctions for
controlled electrochemical etching (described later). The growth occurs in a vapor-phase chemical
deposition reactor from the dissociation at high temperature (> 8000 C) of a silicon source gas.
Common silicon sources are silane (SiH4), silicon dichlorosilane (SiH2CI2), or silicon tetrachloride
(SiCI4). Nominal growth rates vary between 0.2 - 1.5 m/min depending on the source gas and the
growth temperature. Impurity dopants are simultaneously incorporated during growth by the
dissociation of a dopant source gas in the same reactor. Arsine (AsH)) and phosphine (PH)), two
extremely toxic gases, are used for arsenic and phosphorous (n-type) doping while diborane (B2H6)is
used for boron (p-type) doping. Epitaxy can be used to grow crystal silicon on other types of
crystalline substrates such as sapphire (AI2O3). The process is called heteroepitaxy to indicate the
difference in materials. Silicon-on-sapphire (SOS) wafers are effective in applications where an
insulating or a transparent substrate is required. The lattice mismatch between the sapphire and
silicon crystals limits the thickness of the silicon to about one-micrometer. Thicker silicon films
suffer from high defect densities and degraded electronic performance.
There are several technologies for creating the conditions inside a reactor needed to support
epitaxial growth, of which the most important is Vapor Phase Epitaxy (VPE). In this process, a
number of gases are introduced in an induction-heated reactor where only the substrate is heated. The
temperature of the substrate typically must be at least 50% of the melting point of the material to be
deposited.
An advantage of epitaxy is the high growth rate of material, which allows the formation of
films with considerable thickness (>100 µm). Epitaxy is a widely used technology for producing
silicon on insulator (SOI) substrates. The technology is primarily used for deposition of silicon. A
schematic diagram of a typical vapor phase epitaxial reactor is shown in the figure 3. The process can
be used to form films of silicon with thickness of ~1µm to >100µm as well as for selective
deposition.
 Figure 3: Typical cold-wall vapor phase epitaxial reactor.

Thermal oxidation
This is one of the most basic deposition technologies. It involves oxidation of the substrate
surface in an oxygen rich atmosphere. The temperature is raised to 800 °C –1100 °C to speed up the
process. This is the only deposition technology which actually consumes some of the substrate as it
proceeds. The growth of the film is spurned by diffusion of oxygen into the substrate, i.e. the film
growth is actually downwards into the substrate. As the thickness of the oxidized layer increases, the
diffusion of oxygen to the substrate becomes more difficult leading to a parabolic relationship
between film thickness and oxidation time for films thicker than ~100nm.
This process is naturally limited to materials that can be oxidized, and it can only form films
that are oxides of that material. This is the classical process used to form silicon dioxide on a silicon
substrate. A schematic diagram of a typical wafer oxidation furnace is shown in the figure 4.
This is a simple process and used to form films that are used for electrical insulation or that are
used for other process purposes later in a process sequence. Thermal oxidation of silicon generates
compressive stress in the silicon dioxide film. There are two reasons for the stress: (i) silicon dioxide
molecules take more volume than silicon atoms, and (ii) there is a mismatch between the coefficients
of thermal expansion of silicon and silicon dioxide. The compressive stress depends on the total
thickness of the silicon dioxide layer, and can reach hundreds of MPa. As a result, thermally grown
oxide films thicker than one micrometer can cause bowing of the underlying substrate. Moreover,
freestanding membranes and suspended cantilevers made of thermally grown silicon oxide tend to
warp or curl.
 Figure 4: Typical wafer oxidation furnace.

Physical Vapor Deposition (PVD)

PVD covers a number of deposition technologies in which material is released from a source and
transferred to the substrate. The two most important technologies are evaporation and sputtering

Evaporation technique
In evaporation the substrate is placed inside a vacuum chamber, in which a block (source) of the
material to be deposited is also located. The source material is then heated to the point where it starts
to boil and evaporate. Nearly any material (e.g., AI, Si, Ti, Mo, glass, AI2O, etc.) including many
high melting point refractory metals (viz: W, Au, Cr, Pd, Pt) can be evaporated provided it has a
vapor pressure above the background pressure (0.1-1 Pa), and that the carrier in which the target is
contained is itself not evaporated. The carrier is usually made of tungsten or molybdenum. The
vacuum is required to allow the molecules to evaporate freely in the chamber, and they subsequently
condense on all surfaces. This principle is the same for all evaporation technologies. However, the
method used to the heat (evaporate) the source material differs. There are two popular evaporation
technologies, each referring to the heating method; (a) the e-beam evaporation and (b) resistive
evaporation. In e-beam evaporation, an electron beam is aimed at the source material causing local
heating and evaporation. Electron beam evaporation, by contrast, can provide better quality films and
higher deposition rates (50-500 nm/min). The deposition system in this method is more complex
requiring water cooling of the target and shielding from x-rays generated when the energetic
electrons strike the target. Furthermore, radiation that penetrates the surface of the silicon substrate
during the deposition process can damage the crystal and degrade the characteristics of electronic
circuits. In resistive evaporation, a tungsten boat, containing the source material, is heated electrically
with a high current to make the material evaporate. Many materials are restrictive in terms of what
evaporation method can be used (i.e. aluminum is quite difficult to evaporate using resistive heating),
which typically relates to the phase transition properties of that material. A schematic diagram of a
typical system for e-beam evaporation is shown in the figure 5.

Figure 5: Typical system for e-beam evaporation of materials.

Sputtering
In sputtering the material is released from the source at much lower temperature than evaporation.
The substrate is placed in a vacuum chamber with the source material, named a target, and an inert
gas (such as argon) is introduced at low pressure. A gas plasma is struck using an RF power source,
causing the gas to become ionized. The ions are accelerated towards the surface of the target, causing
atoms of the source material to break off from the target in vapor form and condense on all surfaces
including the substrate. Sputtering is a favored method in the MEMS community for the deposition at
low temperatures (< 1500 ˚C) of thin metal films such as aluminum, titanium, chromium, platinum,
and palladium, as well as amorphous silicon and insulators including glass and piezoelectric ceramics
(e.g., PZT,ZnO). The deposited film has a very fine granular structure and is frequently under stress
As for evaporation, the basic principle of sputtering is the same for all sputtering technologies. The
differences typically relate to the manor in which the ion bombardment of the target is realized. A
schematic diagram of a typical RF sputtering system is shown in the figure 6.
Casting
This is a simple process to put down layers of dielectric insulators and organic materials. Unlike
the methods described earlier, the equipment is simple requiring a variable speed-spinning table with
appropriate safety screens. A nozzle dispenses the material as a liquid solution in the center of the
wafer. Spinning the substrate at high speeds (500 to 5000 rpm) rapidly spreads the material in a
uniform manner. Photoresist and polyimides are common organic materials that can be spun on a
wafer Casting is a simple technology, which can be used for a variety of materials (mostly polymers).
In this process the material to be deposited is dissolved in liquid form in a solvent. The material

Figure 6: Typical RF sputtering system.

can be applied to the substrate by spraying or spinning. Once the solvent is evaporated, a thin film
of the material remains on the substrate. This is particularly useful for polymer materials, which
may be easily dissolved in organic solvents, and it is the common method used to apply photoresist
to substrates (in photolithography). The thickness that can be cast on a substrate range all the way
from a single monolayer of molecules (adhesion promotion) to tens of micrometers. In recent
years, the casting technology has also been applied to form films of glass materials on substrates.

Figure 7: The spin casting process as used for photoresist in photolithography.

The spin casting process is illustrated in figure 7. The control on film thickness depends on
exact conditions, but can be sustained within +/-10% in a wide range. For photolithography casting
is an integral part of the technology. There are also other interesting materials such as polyimide
and spin-on glass which can be applied by casting.
 Patterning

Lithography: Pattern Transfer

Lithography in the MEMS context is typically the transfer of a pattern to a photosensitive material
by selective exposure to a radiation source such as light. A photosensitive material is a material that
experiences a change in its physical properties when exposed to a radiation source. If we selectively
expose a photosensitive material to radiation (e.g. by masking some of the radiation) the pattern of
the radiation on the material is transferred to the material exposed, as the properties of the exposed
and unexposed regions differs (as shown in figure 8). Lithography involves three sequential steps: (i)
Application of photoresist (or resist) which is a photosensitive emulsion layer; (2) Optical exposure
to print an image of the mask onto the resist; (3) Immersion in an aqueous developer solution to
dissolve the exposed resist and render visible the latent image. The present discussion focus on
optical lithography, which is simply lithography using a radiation source with wavelength(s) in the
visible spectrum.

Figure 8: Transfer of a pattern to a photosensitive material.

The mask itself consists of a patterned opaque chromium layer on a transparent glass substrate. The
pattern layout is generated using a computer-aided design (CAD) tool, and transferred into the thin
chromium layer at a specialized mask-making facility. A complete micro-fabrication process
frequently involves several lithographic operations. In lithography for micromachining, the
photosensitive material used is typically a photoresist (also called resist, other photosensitive
polymers are also used). When resist is exposed to a radiation source of a specific a wavelength, the
chemical resistance of the resist to developer solution changes. If the resist is placed in a developer
solution after selective exposure to a light source, it will etch away one of the two regions (exposed
or unexposed). If the exposed material is etched away by the developer and the unexposed region is
resilient, the material is considered to be a positive resist (shown in figure 9a). If the exposed material
is resilient to the developer and the unexposed region is etched away, it is considered to be a negative
resist (shown in figure 9b).
Lithography is the principal mechanism for pattern definition in micromachining.
Photosensitive compounds are primarily organic, and do not encompass the spectrum of materials
properties of interest to micro-machinists. However, as the technique is capable of producing fine
features in an economic fashion, a photosensitive layer is often used as a temporary mask when
etching an underlying layer, so that the pattern may be transferred to the underlying layer (shown in
figure 10a). Photoresist may also be used as a template for patterning material deposited after
lithography (shown in figure 10b). The resist is subsequently etched away, and the material deposited
on the resist is "lifted off".
The deposition template (lift-off) approach for transferring a pattern from resist to another layer is
less common than using the resist pattern as an etch mask. The reason for this is that resist is
incompatible with most MEMS deposition processes, usually because it cannot withstand high
temperatures and may act as a source of contamination

Figure 9: a) Pattern definition in positive resist, b) Pattern definition in negative resist.

Once the pattern has been transferred to another layer, the resist is usually stripped. This is often
necessary as the resist may be incompatible with further micromachining steps. It also makes the
topography more dramatic, which may hamper further lithography steps.

Figure 10: a) Pattern transfer from patterned photoresist to underlying layer by

etching, b) Pattern transfer from patterned photoresist to overlying layer by lift-off.

Alignment
In order to make useful devices the patterns for different lithography steps that belong to a
single structure must be aligned to one another. The first pattern transferred to a wafer usually
includes a set of alignment marks, which are high precision features that are used as the reference
when positioning subsequent patterns, to the first pattern (as shown in figure 11). Often alignment
marks are included in other patterns, as the original alignment marks may be obliterated as processing
progresses. It is important for each alignment mark on the wafer to be labeled so it may be identified,
and for each pattern to specify the alignment mark (and the location thereof) to which it should be
aligned. By providing the location of the alignment mark it is easy for the operator to locate the
correct feature in a short time. Each pattern layer should have an alignment feature so that it may be
registered to the rest of the layers.
Depending on the lithography equipment used, the feature on the mask used for registration of
the mask may be transferred to the wafer (as shown in figure 12). In this case, it may be important to
locate the alignment marks such that they don't affect subsequent wafer processing or device
performance. For example, the alignment mark shown in figure 13 will cease to exist after a through
the wafer DRIE etch. Pattern transfer of the mask alignment features to the wafer may obliterate the
alignment features on the wafer. In this case the alignment marks should be designed to minimize this
effect, or alternately there should be multiple copies of the alignment marks on the wafer, so there
will be alignment marks remaining for other masks to be registered to.

Figure 11: Use of alignment marks to register Figure12: Transfer of mask registration feature
subsequent layer to substrate during lithography (contact aligner)

Alignment marks may not necessarily be arbitrarily located on the wafer, as the equipment
used to perform alignment may have limited travel and therefore only be able to align to features
located within a certain region on the wafer (as shown in figure 14). The region location geometry
and size may also vary with the type of alignment, so the lithographic equipment and type of
alignment to be used should be considered before locating alignment marks. Typically two alignment
marks are used to align the mask and wafer, one alignment mark is sufficient to align the mask and
wafer in x and y, but it requires two marks (preferably spaced far apart) to correct for fine offset in
rotation.
As there is no pattern on the wafer for the first pattern to align to, the first pattern is typically
aligned to the primary wafer flat (as shown in figure 15). Depending on the lithography equipment
used, this may be done automatically, or by manual alignment to an explicit wafer registration feature
on the mask.

Exposure
The exposure parameters required in order to achieve accurate pattern transfer from the mask
to the photosensitive layer depend primarily on the wavelength of the radiation source and the dose
required to achieve the desired properties change of the photoresist. Different photoresists exhibit
different sensitivities to different wavelengths. The dose required per unit volume of photoresist for
good pattern transfer is somewhat constant; however, the physics of the exposure process may affect
the dose actually received. For example a highly reflective layer under the photoresist may result in
the material experiencing a higher dose than if the underlying layer is absorptive, as the photoresist is
exposed both by the incident radiation as well as the reflected radiation. The dose will also vary with
resist thickness.

Figure 13: Poor alignment mark design for a Figure 14: Restriction of location of
DRIE through the wafer etch (cross hair is alignment marks based on equipment
released and lost). used.

Figure15: Mask alignment to the wafer flat.

There are also higher order effects, such as interference patterns in thick resist films on reflective
substrates, which may affect the pattern transfer quality and sidewall properties. At the edges of
pattern light is scattered and diffracted, so if an image is overexposed, the dose received by
photoresist at the edge that shouldn't be exposed may become significant. If we are using positive
photoresist, this will result in the photoresist image being eroded along the edges, resulting in a
decrease in feature size and a loss of sharpness or corners (as shown in figure 16). If we are using a
negative resist, the photoresist image is dilated, causing the features to be larger than desired, again
accompanied by a loss of sharpness of corners. If an image is severely underexposed, the pattern may
not be transferred at all, and in less sever cases the results will be similar to those for overexposure
with the results reversed for the different polarities of resist.
If the surface being exposed is not flat, the high-resolution image of the mask on the wafer may be
distorted by the loss of focus of the image across the varying topography. This is one of the limiting
factors of MEMS lithography when high aspect ratio features are present. High aspect ratio features
also experience problems with obtaining even resist thickness coating, which further degrades pattern
transfer and complicates the associated processing.

The Lithography Module

Typically lithography is performed as part of a well-characterized module, which includes the
wafer surface preparation, photoresist deposition, alignment of the mask and wafer, exposure,
develop and appropriate resist conditioning. The lithography process steps need to be characterized as
a sequence in order to ensure that the remaining resist at the end of the modules is an optimal image
of the mask, and has the desired sidewall profile.
The standard steps found in a lithography module are (in sequence): dehydration bake, HMDS
prime, resist spin/spray, soft bake, alignment, exposure, post exposure bake, develop hard bake and
descum. Not all lithography modules will contain all the process steps. A brief explanation of the
process steps is included for completeness
.
Dehydration bake - dehydrate the wafer to aid resist adhesion.
HMDS prime - coating of wafer surface with adhesion promoter. Not necessary for all surfaces.
Resist spin/spray - coating of the wafer with resist either by spinning or spraying. Typically desire
a uniform coat.
Soft bake - drive off some of the solvent in the resist, may result in a significant loss of mass of
resist (and thickness). Makes resist more viscous.
Alignment - align pattern on mask to features on wafers.
Exposure - projection of mask image on resist to cause selective chemical property change.
Post exposure bake - baking of resist to drive off further solvent content. Makes resist more
resistant to etchants (other than developer).
Develop - selective removal of resist after exposure (exposed resist if resist is positive, unexposed
resist if resist is positive). Usually a wet process (although dry processes exist).
Hard bake - drive off most of the remaining solvent from the resist.
 Descum - removal of thin layer of resist scum that may occlude open regions in pattern, helps to
open up corners.

In photolithography, a few assumptions are made. Firstly, it is assumed that a well characterized
module exists: prepares the wafer surface, deposits the requisite resist thickness, aligns the mask
perfectly, exposes the wafer with the optimal dosage, develops the resist under the optimal
conditions, and bakes the resist for the appropriate times at the appropriate locations in the sequence.
Unfortunately, even if the module is executed perfectly, the properties of lithography are very feature
and topography dependent. It is therefore necessary for the designer to be aware of certain limitations
of lithography, as well as the information they should provide to the technician performing the
lithography.

Figure 16: Over and under-exposure of positive resist.

The designer influences the lithographic process through their selections of materials, topography
and geometry. The material(s) upon which the resist is to be deposited is important, as it affects the
resist adhesion. The reflectivity and roughness of the layer beneath the photoresist determines the
amount of reflected and dispersed light present during exposure. It is difficult to obtain a nice
uniform resist coat across a surface with high topography, which complicates exposure and
development as the resist has different thickness in different locations. If the surface of the wafer has
many different height features, the limited depth of focus of most lithographic exposure tools will
become an issue (as shown in figure 17).
 Figure 17: Lithography tool depth of focus and surface topology.

The designer should keep all these limitations in mind, and design accordingly. For example, it is
judicious, when possible, to perform very high aspect patterning step (lithography and subsequent
etch/deposition) last, as the topography generated often hampers any further lithography steps. It is
also necessary for the designer to make it clear which focal plane is most important to them (keeping
in mind that features further away in Z from the focal plane will experience the worst focus). The
resolution test structures should be located at this level (as they will be used by the fab to check the
quality of a photo step).

Etching

In order to form a functional MEMS structure on a substrate, it is necessary to etch the thin films
previously deposited and/or the substrate itself. In general, there are two classes of etching processes:
1. Wet etching where the material is dissolved when immersed in a chemical solution
2. Dry etching where the material is sputtered or dissolved using reactive ions or a vapor
phase etchant.

Wet etching

This is the simplest etching technology, especially for the combination of etchant and mask
material to suit the particular application. Wet etching works very well for etching thin films on
substrates and can also be used to etch the substrate itself. All it requires is a container with a liquid
solution that will dissolve the material in question. There are complications since usually a mask is
desired to selectively etch the material. One must find a mask that will not dissolve or at least etches
much slower than the material to be patterned. Secondly, some single crystal materials, such as
silicon, exhibit anisotropic etching in certain chemicals. Anisotropic etching in contrast to isotropic
etching means different etch rates in different directions in the material. The classic example of this is
the <111> crystal plane sidewalls that appear when etching a hole in a <100> silicon wafer in a
chemical such as potassium hydroxide (KOH). The result is a pyramid shaped hole instead of a hole
with rounded sidewalls with a isotropic etchant. The principle of anisotropic and isotropic wet
etching is illustrated in the figure 18. With dry etching it is possible etch almost straight down
without undercutting, which provides much higher resolution.

Figure 18: Difference between anisotropic and isotropic wet etching.

Dry etching
This is expensive to run compared to wet etching. The dry etching technology can split in
three separate classes called reactive ion etching (RIE), sputter etching, and vapor phase etching. In
RIE, the substrate is placed inside a reactor in which several gases are introduced. Plasma is struck in
the gas mixture using an RF power source, breaking the gas molecules into ions. The ions are
accelerated towards, and react at, the surface of the material being etched, forming another gaseous
material. This is known as the chemical part of reactive ion etching. There is also a physical part,
which is similar in nature to the sputtering deposition process. If the ions have high enough energy,
they can knock atoms out of the material to be etched without a chemical reaction. It is a very
complex task to develop dry etch processes that balance chemical and physical etching, since there
are many parameters to adjust. By changing the balance, it is possible to influence the anisotropy of
the etching, since the chemical part is isotropic and the physical part highly anisotropic the
combination can form sidewalls that have shapes from rounded to vertical. A schematic of a typical
reactive ion etching system is shown in figure 19.
Deep reaction ion etching (FRIE) is a technique which is growing rapidly. In this process, etch
depths of hundreds of microns can be achieved with almost vertical sidewalls. The primary
technology consists of two different gas compositions alternated in a reactor. The first gas
composition creates a polymer on the surface of the substrate, and the second gas composition etches
the substrate. The polymer is immediately sputtered away by the physical part of the etching, but only
on the horizontal surfaces and not the sidewalls. Since the polymer only dissolves very slowly in the
chemical part of the etching, it builds up on the sidewalls and protects them from etching. As a result,
etching aspect ratios of 50 to 1 can be achieved. The process can easily be used to etch completely
through a silicon substrate, and etch rates are 3-4 times higher than wet etching. Sputter etching is
essentially RIE without reactive ions. The systems used are very similar in principle to sputtering
deposition systems. The big difference is that substrate is now subjected to the ion bombardment
instead of the material target used in sputter deposition.
Vapor phase etching is another dry etching method, which can be done with simpler equipment
than what RIE requires. The wafer to be etched is placed inside a chamber, in which one or more
gases are introduced. By a chemical reaction with the gas molecules., the material to be etched is
dissolved at the surface The two most common vapor phase etching technologies are silicon dioxide
etching using hydrogen fluoride (HF) and silicon etching using xenon diflouride (XeF2), both of
which are isotropic in nature. Usually, care must be taken in the design of a vapor phase process to
not have biproducts form in the chemical reaction that condense on the surface and interfere with the
etching process.

Figure 19: Typical parallel-plate reactive ion etching system.

Current Challenges
MEMS is currently used in low- or medium-volume applications. Some of the obstacles preventing
its wider adoption are:
a. Limited Options: the limited facility for protyping or manufacturing, available with most of the
companies along with lack of expertise is the main hindrance for large volume applications of
MEMS. The very high capital investment requirement for the manufacturing of MEMS is another
obstacle. There is a need by which affordable access, for smaller organizations, to MEMS fabrication
is essential.
b. Packaging: It has been appreciated by may of the companies that packaging is the single most
expensive and time-consuming task in their overall product development program. The packaging of
MEMS devices and systems will have to go a long way before it can satisfactorily be floated in the
market. MEMS packaging is challenging due to the diversity of MEMS devices since these devices
will have to be in contact with their environment. Development efforts should be focused on new and
specialized packages for each new device. Since most of the physical phenomenon accompanying
MEMS components are not fully understood, more inputs in numerical modeling and simulation tools
for MEMS packaging are required. Approaches, which allow designers to select from a catalog of
existing standardized packages for a new MEMS device without compromising performance, would
be beneficial.
c. Fabrication Knowledge Required: A very high level of fabrication knowledge is required by the
designer of MEMS devices for a successful design. A dedicated research effort to find a suitable
process sequence for the fabrication is also essential.