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Tpa 3128 D 2
Tpa 3128 D 2
TPA3128D2, TPA3129D2
SLOS941C – MAY 2016 – REVISED JANUARY 2018
TPA3128D2, TPA3129D2 2x30-W, 2x15-W Class-D Amplifier With Low Idle Power
Dissipation
1 Features 3 Description
1• Supports Multiple Output Configurations The TPA3128D2 and TPA3129D2 have low idle
power loss and helps to extend the battery life of
– 2 × 30 W Into a 8-Ω BTL Load at 24 V Bluetooth/Wireless speakers and other battery-
(TPA3128D2) powered audio systems. The high efficiency of the
– 2 × 15 W Into a 8-Ω BTL Load at 15 V TPA3128D2 device allows it to do 2 × 30 W without
(TPA3129D2) external heat sink on a dual layer PCB. The high
• Wide Voltage Range: 4.5 V to 26 V efficiency of the TPA3129D2 device allows it to do 2
× 15 W without external heat sink on a dual layer
• Efficient Class-D Operation PCB. This device proposed an efficiency boost Mode,
– Very Low Idle Current: <23 mA for which can dynamically reduced the current ripple of
recommended LC filter configurations the external LC filter and the idle current .
– Greater than 90% Power Efficiency Combined The TPA31xxD2 advanced oscillator/PLL circuit
With Low Idle Loss Greatly Eliminates Need employs a multiple switching frequency option to
for Heat Sink avoid AM interferences, which is achieved together
– Adaptive Modulation Schemes based on with an option of either master or slave option,
Output Power making it possible to synchronize multiple devices.
– Smart Amplifier Drivers to Reduce the The TPA31xxD2 devices are fully protected against
Requirement for RC Snubbers faults with short-circuit protection and thermal
protection as well as overvoltage, undervoltage, and
• Multiple Switching Frequencies DC protection. Faults are reported back to the
– AM Avoidance processor to prevent devices from being damaged
– Master and Slave Synchronization during overload conditions.
– 300-KHz to 1.2-MHz Switching Frequency
Device Information(1)
• Feedback Power-Stage Architecture With High PART NUMBER PACKAGE BODY SIZE (NOM)
PSRR Reduces PSU Requirements
TPA3128D2 DAP (32) 11.00 mm × 6.20 mm
• Programmable Power Limit TPA3129D2 DAP (32) 11.00 mm × 6.20 mm
• Parallel BTL Mode and Mono-Channel Mode
(1) For all available packages, see the orderable addendum at
Support the end of the datasheet.
• Supports Both Single and Dual Power Supply
Modes Simplified Application Circuit
• Integrated Self-Protection Circuits Including TPA3128D2
Overvoltage, Undervoltage, Overtemperature, DC- TPA3129D2
RIGHT MONO
LC
Detect, and Short Circuit With Error Reporting DETECT
Audio TAS5630
• Thermally Enhanced Packages Source LEFT
PBTL
DETECT
And Control LC
– DAP (32-Pin HTSSOP Pad Down for SD
FAULT
Power Supply
2 Applications AM Avoidance Control AM2,1,0
PVCC
4.5V-26V
Power Limit
GAIN/SLV
• LCD/LED TVs
• Home Theaters
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3128D2, TPA3129D2
SLOS941C – MAY 2016 – REVISED JANUARY 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 21
2 Applications ........................................................... 1 8 Applications and Implementation ...................... 22
3 Description ............................................................. 1 8.1 Application Information............................................ 22
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 22
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 25
9.1 Power Supply Mode ................................................ 25
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 10 Layout................................................................... 25
6.2 ESD Ratings ............................................................ 5 10.1 Layout Guidelines ................................................. 25
6.3 Recommended Operating Conditions....................... 5 10.2 Layout Example .................................................... 26
6.4 Thermal Information .................................................. 6 11 Device and Documentation Support ................. 28
6.5 DC Electrical Characteristics .................................... 6 11.1 Documentation Support ....................................... 28
6.6 AC Electrical Characteristics..................................... 6 11.2 Community Resources.......................................... 28
6.7 Typical Characteristics .............................................. 8 11.3 Trademarks ........................................................... 28
7 Detailed Description ............................................ 12 11.4 Electrostatic Discharge Caution ............................ 28
7.1 Overview ................................................................. 12 11.5 Glossary ................................................................ 28
7.2 Functional Block Diagram ....................................... 12 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 13 Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added mA to the Unit value for ICC in the DC Electrical Characteristics table ...................................................................... 6
DAP Package
32-Pin HTSSOP With PowerPAD Down
TPA3128D2, TPA3129D2, Top View
MODSEL 1 32 PVCC
SDZ 2 31 PVCC
FAULTZ 3 30 BSPR
RINP 4 29 OUTPR
RINN 5 28 GND
PLIMIT 6 27 OUTNR
GVDD 7 26 BSNR
GAIN/SLV 8 Thermal 25 GND
GND 9 PAD 24 BSPL
LINP 10 23 OUTPL
LINN 11 22 GND
MUTE 12 21 OUTNL
AM2 13 20 BSNL
AM1 14 19 PVCC
AM0 15 18 PVCC
SYNC 16 17 AVCC
Pin Functions
PIN
TYPE (1) DESCRIPTION
NO. NAME
1 MODSEL I Mode selection logic input (LOW = Ultra Low Idle Loss Mode, HIGH = BD Mode). TTL logic levels with
compliance to AVCC.
2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with
compliance to AVCC.
3 FAULTZ DO General fault reporting including Over-temp, DC Detect. Open drain.
FAULTZ = High, normal operation
FAULTZ = Low, fault condition
4 RINP I Positive audio input for right channel. Connect to GND for MONO mode.
5 RINN I Negative audio input for right channel. Connect to GND for MONO mode.
6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly
to GVDD for no power limit.
7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other
than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider.
9 GND G Ground
10 LINP I Positive audio input for left channel. Connect to GND for PBTL mode.
11 LINN I Negative audio input for left channel. Connect to GND for PBTL mode.
12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic
levels with compliance to AVCC.
13 AM2 I AM Avoidance Frequency Selection
14 AM1 I AM Avoidance Frequency Selection
15 AM0 I AM Avoidance Frequency Selection
16 SYNC DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal.
17 AVCC P Analog Supply
(1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.
Copyright © 2016–2018, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPA3128D2 TPA3129D2
TPA3128D2, TPA3129D2
SLOS941C – MAY 2016 – REVISED JANUARY 2018 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VCC PVCC, AVCC –0.3 30 V
INPL, INNL, INPR, INNR –0.3 6.3 V
Input voltage, VI PLIMIT, GAIN / SLV, SYNC –0.3 GVDD+0.3 V
AM0, AM1, AM2, MUTE, SDZ, MODSEL –0.3 PVCC+0.3 V
(2)
Slew rate, maximum AM0, AM1, AM2, MUTE, SDZ, MODSEL 10 V/ms
Operating free-air temperature, TA –40 85 °C
Operating junction temperature , TJ –40 150 °C
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under absolute maximum ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) 100-kΩ series resistor is required if maximum slew rate is exceeded.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) For the PCB layout, see the TPS3128D2EVM user guide.
30 10
Gain=26dB Gain=26dB P O=1W
TA=25qC PVcc=12V PO =2.5W
RL=4: TA=25qC PO=5W
1 RL=8:
PVDD Idle Current (mA)
20
THD+N(%)
0.1
10
0.01
0 0.001
5 10 15 20 25 20 100 1k 10k 20k
Supply Voltage (V) Frequency (Hz) D005
D001
Figure 1. Idle Current vs PVCC Figure 2. Total Harmonic Distortion + Noise (BTL) vs
Frequency
10 10
Gain=26dB P O=1W Gain=26dB
PVcc=24V PO =5W PVCC=6V
TA=25qC PO=10W TA=25qC
1 RL=8: 1 RL=4:
THD+N (%)
THD+N(%)
0.1 0.1
0.01 0.01
f= 20Hz
f= 1kHz
f= 6KHz
0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10
Frequency (Hz) D006
Output Power (W) D007
Figure 3. Total Harmonic Distortion + Noise (BTL) vs Figure 4. Total Harmonic Distortion + Noise (BTL) vs Output
Frequency Power
10 10
Gain=26dB Gain=26dB
PVCC=12V PVCC=24V
TA=25qC TA=25qC
1 RL=4: 1 RL=4:
THD+N (%)
THD+N (%)
0.1 0.1
0.01 0.01
f= 20Hz f= 20Hz
f= 1kHz f= 1kHz
f= 6KHz f= 6KHz
0.001 0.001
0.01 0.1 1 10 40 0.01 0.1 1 10 100
Output Power (W) D008
Output Power (W) D009
Figure 5. Total Harmonic Distortion + Noise (BTL) vs Output Figure 6. Total Harmonic Distortion + Noise (BTL) vs Output
Power Power
THD+N (%)
THD+N (%)
0.1 0.1
0.01 0.01
f= 20Hz f= 20Hz
f= 1kHz f= 1kHz
f= 6KHz f= 6KHz
0.001 0.001
0.01 0.1 1 10 50 0.01 0.1 1 10 50
Output Power (W) D010
Output Power (W) D011
Figure 7. Total Harmonic Distortion + Noise (BTL) vs Output Figure 8. Total Harmonic Distortion + Noise (BTL) vs Output
Power Power
50 30 300
Gain=26dB
TA=25qC 20 200
40 PVCC=24V
RL=4: 10 100
Output Power (W)
30 0 0
Gain (dB)
Phase (q)
-10 -100
20 -20 -200
35 70
30 60
25 50
20 40
15 30
10 20
5 THD+N=1% 10 THD+N=1%
THD+N=10% THD+N=10%
0 0
4 6 8 10 12 14 16 18 20 22 24 26 4 6 8 10 12 14 16 18 20 22 24 26
Supply Voltage (V) D014
D037
Supply Voltage (V) D015
D037
Figure 11. Maximum Output Power (BTL) vs Supply Voltage Figure 12. Maximum Output Power (BTL) vs Supply Voltage
-60 -60
-80 -80
-100 -100
-40
0.1
-60
0.01
-80
Left Channel
Right Channel
-100 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) D020
Frequency (Hz) D021
Figure 17. Supply Ripple Rejection Ratio (BTL) vs Figure 18. Total Harmonic Distortion + Noise (PBTL) vs
Frequency Frequency
100
0.1
80
60
0.01
40
f= 20Hz
f= 1kHz 20 THD+N=1%
f= 6KHz THD+N=10%
0.001 0
0.01 0.1 1 10 40 4 6 8 10 12 14 16 18 20 22
Output Power (W) D022
Supply Voltage (V) D023
Figure 19. Total Harmonic Distortion + Noise (PBTL) vs Figure 20. Maximum Output Power (PBTL) vs Supply
Output Power Voltage
100 0
Gain=26dB
90 PVCC=12VDC+200mVP-P
80 -20 TA=25qC
RL=2:
Power Efficiency (%)
70
kSVR (dB)
60 -40
50
40 -60
30
20 Gain=26dB PVCC = 6V -80
T =25qC PVCC = 12 V
10 A
RL=2: PVCC = 24 V
0 -100
0 10 20 30 40 50 60 70 20 100 1k 10k 20k
Output Power (W) D024
Frequency (Hz) D025
Figure 21. Power Efficiency (PBTL) vs Output Power Figure 22. Supply Ripple Rejection Ratio (PBTL) vs
Frequency
10 140
Gain=26dB 130 Gain=26dB
120 A=25qC
PVCC=24V T
TA=25qC RL=3:
Maximum Output Power (W)
110
1 RL=3:
100
90
THD+N (%)
80
0.1 70
60
50
40
0.01
30
f= 20Hz
f= 1kHz 20 THD+N=1%
f= 6KHz 10 THD+N=10%
0.001 0
0.01 0.1 1 10 50 100 200 4 6 8 10 12 14 16 18 20 22 24 26
Output Power (W) D026
Supply Voltage (V) D027
Figure 23. Total Harmonic Distortion + Noise (PBTL) vs Figure 24. Maximum Output Power (PBTL) vs Supply
Output Power Voltage
7 Detailed Description
7.1 Overview
The TPA3128D2and TPA3129D2 devices are a highly efficient Class D audio amplifier with extreme low idle
power dissipation. It can support as low as 23-mA idle loss current using standard LC filter configurations. It is
integrated with 90-mΩ MOSFET that allows output currents up to 7.5 A for TPA3128D2 and 5.5 A for
TPA3129D2. The high efficiency allows the amplifier to provide an excellent audio performance without the
requirement for a bulky heat sink.
The device can be configured for either master or slave operation by using the SYNC pin. Configuring using the
SYNC pin helps to prevent audible beats noise.
RINP
– – – GND
Gain + + PWM
Control PLIMIT Logic GVDD
RINN – – PVCC
+ + – BSNR
PVCC
OUTPNR_FB
+ OUTNR_
FAULTZ FB
Gate
Drive OUTNR
Input
Sense
MONO
Select
SC Detect
SYNC GND
GAIN/SLV DC Detect
Ramp Biases and Startup Protection
AM<2:0> Generator References Logic Thermal
Detect
PLIMIT
PLIMIT Reference UVLO/OVLO
PVCC PVCC
GVDD
PVCC
AVDD BSNL
PVCC
LDO
AVCC Regulator
GVDD Gate
Drive OUTNL
GVDD
–
OUTNL_FB OUTNL_
FB
LINP – – +
+ GND
Gain + PWM
Control PLIMIT Logic
– GVDD
LINN + – + PVCC
+ BSPL
PVCC
OUTPL_FB
–
Gate
Drive OUTPL
Input PBTL Modulation and
Sense Select PBTL Select OUTPL_FB
GND
GND
5
INNR
2 1 6
PLIMIT
C5 1 µF 2 1 7 GVDD
2 1 R2 51 k 8
GAIN/SLV
R1 51 k 9
GND
10
In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL
logic levels with compliance to GVDD.
Zf
Ci
Zi
Input IN
Signal
The input capacitors used should be a type with low leakage, such as quality electrolytic, tantalum, or ceramic
capacitors. If a polarized type is used the positive connection should face the input pins which are biased to 3
Vdc.
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output
voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker
impedance.
2
ææ RL ö ö
çç ç ÷ ´ VP ÷÷
è RL + 2 ´ RS ø
POUT = è ø for unclipped power
2 ´ RL
where
• POUT (10%THD) = 1.25 × POUT (unclipped)
• RL is the load resistance.
• RS is the total series resistance including RDS(on), and output filter resistance.
• VP is the peak amplitude, which is limited by "virtual" voltage rail. (2)
(1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms.
> 1.4sec
SDZ
MUTE
mP TPA312xD2
FAULTZ
SDZ
MUTE
FAULTZ
TPA3128D2
Figure 28. MUTE Driven by Inverted FAULTZ Figure 29. Timing Requirement for SDZ
7.3.12.1 BD-Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
OUTP- OUTN 0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN 0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP - OUTN 0V
- PVCC
Speaker 0A
Current
7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier-based on AD modulation requires an output filter is that the
switching waveform results in maximum current flow. This causes more loss in the load, which causes lower
efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is
proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the
time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is required to store
the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The
speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3128D2 and TPA3129D2 modulation schemes have little loss in the load without a filter because the
pulses are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the
pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased
efficiency, but for most applications the filter is not required.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
Figure 31. TPA3128D2 Radiated Emissions-Horizontal Figure 32. TPA3128D2 Radiated Emissions-Vertical
(PVCC=12V, PO=1W) (PVCC=12V, PO=1W)
Ferrite
Chip Bead
OUTP
1 nF 4W-8W
Ferrite
Chip Bead
OUTN
1 nF
Table 6. AM Frequencies
US EUROPEAN
SWITCHING FREQUENCY (kHz) AM2 AM1 AM0
AM FREQUENCY (kHz) AM FREQUENCY (kHz)
522-540
540-917 540-914 500 0 0 1
0 1 0
917-1125 914-1122 600 (or 400)
0 0 0
1125-1375 1122-1373 500 0 0 1
0 1 0
1375-1547 1373-1548 600 (or 400)
0 0 0
LC Filter
OUTPL
Left PBTL OUTNL
Detect
OUTPL LC Filter
Left OUTNL
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
1
PVCC
1
C74 C101 L7 10uH R25
OUT_P_RIGHT
10nF 1 2 1 2 C108 C107 3.3R
GND
1
1nF 100nF 220uF
2
1 2
GND R10 3.3R C47 100nF C77 C112
2
680nF 1nF
GND U3 C114
2
GVDD R28 100k 10nF
1 2 GND GND
2
1 32 +
SDZ GND PVCC
2 31
FAULTZ SDZ PVCC C43 220nF GND GND -
1
C95 1uF 3 30 1 2
FAU LTZ BSPR
OU T_N_RIGH T
2 1 C115
RINP
1
4 29 10nF
2 1 RINP OUTPR C113 C109
RINN
1 2
5 28 680nF 1nF
GND
C121 1uF RINN GND
2
6 27 R26
PLIMIT OUTN R
1
Power Pad
GVDD 3.3R
R27 7 26 1 2 1 2
2
GVDD BSNR
1
100k
C117 8 25 C40 220nF L8 10uH
GND
12
GND BSPL
1
20k
10 23
OUT_P_LEFT
L10 10uH R24
2
1
GND C46 1uF 11 22
GND
1 2
2 1 LINN GND C59 C80
LINP 12 21 680nF 1nF
2 1 MUTE OUTN L C75
LINN
2
13 20 1 2 10nF
C1161uF AM2 BSNL
2
14 19 C111 220nF +
MUTE AM1 PVCC
1
1 2 15 18 GND GND
AM0 PVCC PVCC C79 -
1
R18 100k 16 17 10nF
SY NC AVCC C58 C110
OUT_ N_LEFT
1 2
1
1
SYNC
2
TPA312xD2 1nF 100nF 220uF R23
L9 3.3R
2
2
4.7k 10uH
2
1 2
GND
PVCC DECOUPLI NG
PVCC DECOUPLI NG
47pF PVCC
1
C126
C128 C127
1nF 100nF 220uF
2
U4
GVDD2 R49 100k
1 2 GND GND
1 32
SDZ GND PVCC OUTPUT LC FILTER EMI C-RC SNUBBER
2 31
FAULTZ SDZ PVCC 1 2
C122 220nF
1
C125 1uF 3 30 1 2
2 1 FAU LTZ BSPR L15 10uH R46
OUT_P_SUB
RINP 4 29 3.3R
RINP OUTPR
1
1
2 1
RINN
1 2
5 28 C124 C131
GND
PLIMIT OUTN R
1
Power Pad
GVDD2 10nF
R48 7 26 1 2
2
GVDD BSNR
1
47k +
C135 8 25 C140 220nF
GND
12
GND BSPL
1
75k
10 23 C134
OUT_N_SUB
2
LINP OUTPL
1
10nF
11 22 C132 C129
GND
1 2
13 20 1 2 3.3R
R36 AM2 BSNL 1 2
2
15 18
AM0 PVCC PVCC
16 17
GND SY NC AVCC
1
GND
PVCC DECOUPLI NG
10 140
Gain=26dB 130 Gain=26dB
120 A=25qC
PVCC=24V T
TA=25qC RL=3:
80
0.1 70
60
50
40
0.01
30
f= 20Hz
f= 1kHz 20 THD+N=1%
f= 6KHz 10 THD+N=10%
0.001 0
0.01 0.1 1 10 50 100 200 4 6 8 10 12 14 16 18 20 22 24 26
Output Power (W) D026
Supply Voltage (V) D027
Figure 37. Total Harmonic Distortion + Noise (PBTL) vs Figure 38. Maximum Output Power (PBTL) vs Supply
Output Power Voltage
10 Layout
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPA3128D2DAP ACTIVE HTSSOP DAP 32 46 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3128D2
TPA3128D2DAPR ACTIVE HTSSOP DAP 32 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3128D2
TPA3129D2DAP ACTIVE HTSSOP DAP 32 46 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3129D2
TPA3129D2DAPR ACTIVE HTSSOP DAP 32 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3129D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
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(6)
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TUBE
Pack Materials-Page 3
GENERIC PACKAGE VIEW
TM
DAP 32 PowerPAD TSSOP - 1.2 mm max height
8.1 x 11, 0.65 mm pitch PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225303/A
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