ECE 341

Lecture # 5
Instructor: Zeshan Chishti
zeshan@ece.pdx.edu

October 13, 2014

Portland State University

 Lecture Topics
• Computer Arithmetic
– 2’s Complement Representation
– Addition and subtraction of signed integers
• Binary Addition
• Overflow Conditions
• Ripple-carry Adders
– Design of Fast Adders
• Carry Looakahead Adders (CLA)

• Reference:
– Chapter 9: Sections 9.1, 9.2
 Two’s Complement Representation
• N-bit binary digit can represent
any integer between -2N-1 and
+2N-1-1 -1 +0
• Most significant bit (MSB) -2 1111 0000 +1
indicates sign of the integer -3
1110 0001
+2
• To obtain representation for a 1101 0010
+

signed integer -4 1100 0011 +3 0 100 = + 4

 Invert the bits (1’s
complement) -5 1011 0100 +4 1 100 = - 4
 Add 1 1010 0101
-6 +5 -
E.g., +4 = 0100 1001 0110
-4 = 1011 + 1 = 1100 +6
-7 1000 0111
• To add a +ve number, go
-8 +7
clockwise,
• To add a –ve number, go
anticlockwise
 Addition and Subtraction – 2’s Complement
Addition 0000 Carry-in 1100
• Bit pairs added from LSB to MSB 4 0100 -4 1100
• Each addition takes bit values and +3 0011
carry-in as input, generates sum and + (-3) 1101
carry-out as outputs 7 0111 -7 11001
• Carry-out at any bit position
becomes carry-in for next bit position Sum
0000
Subtraction 4 0100 4 0100
• Take the 2’s complement of =>
-(- 3) 1101 +3 +0011
the second operand
• Add to the first operand 7 0111

Simpler addition/subtraction scheme makes two’s complement the most common

choice for integer number systems
 Overflow in Integer Arithmetic
-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 0010 1101 +2
0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001 +5 1001 +5
0110 0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7
Adding two Adding two
positive integers 5 + 3 = -8 -7 - 2 = +7 negative integers
results in a Should be +8 Should be -9 results in a
negative integer positive integer

When the result of an add/subtract cannot be represented by the same

number of bits as the operands, overflow occurs
 Overflow Conditions
0111 1000
5 0101 -7 1001
3 0011 -2 1100
-8 1000 7 10111
Overflow Overflow

For addition:
 Overflow cannot occur if the sign of two operands is different
 Overflow occurs when the sign of two operands is the same AND the sign of result
is different from the sign of operands

For both addition and subtraction:

 Overflow occurs when the carry-in to MSB is different from the carry-out of MSB
Logic Specification for Binary Addition
x
i
y
i
Carry-in ci Sum si Carry-out ci+1 At the ith stage:
Input:
0 0 0 0 0
0 0 1 1 0
ci is the carry-in
0 1 0 1 0 Output:
0 1 1 0 1 si is the sum
1 0 0 1 0 ci+1 carry-out to (i+1)st stage
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

s = x y c + x y c + x y c + x y c = x  y c
i i i i i i i i i i i i i i i i
c = y c +x c +x y
i +1 i i i i i i
Example:

X 7 0 1 1 1 xi
Carry-out Carry-in
+ Y = +6 = + 0 0 1 1 1 1 0 0 0 yi
ci+1 ci
Z 13 1 1 0 1 si

Legend for stage i

 Addition Logic for a Single Stage
Sum Carry

y
i
c
x i
i
x
y s i c
i i c i +1
i
c
i x
x y i
i i y
i

c Full adder c
i +1 (FA) i

s
i

Full Adder (FA): Symbol for the complete

circuit for a single stage of addition
 n-bit Adder
•Cascade n full-adder (FA) blocks to form a n-bit adder.
•Carries propagate or ripple through this cascade, n-bit ripple carry adder

xn-1 yn-1 x1 y1 x0 y0

cn cn-1 c2 c1
FA ……. FA FA c0

Sn-1 s1 s0

Most significant bit Least significant bit

(MSB) position (LSB) position
 kn-bit Adder
Two numbers each having kn-bits can be added by cascading k n-bit adders
For example, 8 4-bit adders can be cascaded to add two 32-bit numbers
x y x y x y x y x y
kn- 1 kn- 1 2n - 1 2n- 1 n n n- 1 n- 1 0 0

c
n-bit n-bit n n-bit
c c
kn adder adder adder 0

s s s s s s
kn- 1 (k - 1)n 2n- 1 n n- 1 0

Each n-bit adder forms a block

Carries ripple or propagate through blocks, Blocked Ripple Carry Adder
 n-bit Subtractor
• Recall X – Y is equivalent to adding 2’s complement of Y to X.
• 2’s complement is equivalent to 1’s complement + 1.
• X–Y=X+Y+1
• Carry-in c0 into the LSB position is equal to “1” to perform subtraction

_ _ _
xn-1 yn-1 x1 y1 x0 y0

cn cn-1 c2 c1
FA ……. FA FA 1

Sn-1 s1 s0

Most significant bit Least significant bit

(MSB) position (LSB) position
 n-bit Adder/Subtractor
yn- 1 y1 y0
Add/Sub
control

xn- 1 x1 x0

cn n-bit adder
c
0

sn- 1 s1 s0

Add/sub control = 0 implies addition.

Add/sub control = 1 implies subtraction.
 Detecting Overflows
Recall that for addition
• Overflow can occur only when the sign of two operands is the same
• Overflow occurs if the sign of result is different from the sign of operands
• Recall that the MSB represents the sign.
• xn-1, yn-1, sn-1 represent the sign of operand x, operand y and result s respectively
• Circuit to detect overflow in an n-bit adder can be implemented as:
Overflow  xn1 yn1sn1  xn1 yn1sn1

Recall that for both addition/subtraction,

• Overflow occurs when carry-in to MSB is different from carry-out of MSB
• Simpler circuit to detect overflow in an n-bit adder/subtractor is:
Overflow  cn  cn1
 Computing the Add Time
x0 y0
Consider 0th stage:
•c1 is available after 2 gate delays.
c1 FA c0 •s0 is available after 1 gate delay.

s0

Sum Carry
• ci needed to compute si yi
• Carry propagation is xi
c
i

the critical path in a xi

yi si c
ripple-carry adder c
i
i +1

ci
x
i
yi
Computing the Add Time (contd..)
Cascade of 4 Full Adders, or a 4-bit adder
x3 y3 x2 y2 x1 y1 x0 y0

FA FA FA FA c0
c4 c3 c2 c1

s3 s2 s1 s0

• s0 available after 1 gate delays, c1 available after 2 gate delays.

• s1 available after 3 gate delays, c2 available after 4 gate delays.
• s2 available after 5 gate delays, c3 available after 6 gate delays.
• s3 available after 7 gate delays, c4 available after 8 gate delays.

For an n-bit ripple adder, sn-1 is available after 2n-1 gate delays
cn is available after 2n gate delays.
 Fast Addition
Recall the equations:

si  xi  yi  ci
ci 1  xi yi  xi ci  yi ci
Second equation can be written as:

ci 1  xi yi  ( xi  yi )ci
We can write:
ci 1  Gi  Pi ci
where Gi  xi yi and Pi  xi  yi

• Gi is called generate function and Pi is called propagate function

• Gi and Pi computed only from xi and yi and not ci, thus they can be computed
in one gate delay after X and Y are applied to the inputs of an n-bit adder
 Carry Lookahead Adder (CLA)
ci 1  Gi  Pi ci
ci  Gi 1  Pi 1ci 1
 ci1  Gi  Pi (Gi 1  Pi 1ci 1 )
continuing
 ci1  Gi  Pi (Gi 1  Pi 1 (Gi  2  Pi 2 ci 2 ))
until
ci1  Gi  PiGi 1  Pi Pi1 Gi 2  ..  Pi Pi 1 ..P1G0  Pi Pi 1 ...P0 c 0
• ci+1 in the above equation depends only on propagate functions,
generate functions and c0
• Calculation of ci+1 no longer requires calculation of ci, ci-1, ci-2……. etc.
=> all carries can be computed in parallel
• This is called carry lookahead addition (CLA)
 Understanding Carry-Lookahead Addition

• CLA relies on generate (G) and propagate (P) functions

• An n-bit CLA computes Gi and Pi at each of its n stages
Gi = xiyi and Pi = xi+yi
• Gi = 1 implies that stage i generates a carry-out of 1, independent of its carry-in
• Pi = 1 implies that stage i propagates a carry-in of 1 from its input to its output
• The carry-out ci+1 of stage i is equal to 1, if:
Stage i generates a carry-out (i.e., Gi = 1), or
Any stage j, such that j < i, generates a carry-out (i.e., Gj = 1) and all the stages
between j and i, including i, propagate the carry (i.e., Pj+1 = Pj+2 = … = Pi = 1), or
c0 = 1 and all the stages up to and including stage i propagate the carry (i.e., c0 =
P0 = P1 = …….. = Pi = 1)
• Therefore, the general expression for ci+1 in a CLA is:
ci+1 = Gi + PiGi-1 + PiPi-1Gi-2 + …. ………+ PiPi-1….P1G0 + PiPi-1….P0c0
 CLA Example
• The general expression for ci+1 in CLA is:
 ci+1 = Gi + PiGi-1 + PiPi-1Gi-2 + …. ………+ PiPi-1….P1G0 + PiPi-1….P0c0

• Consider 4-bit addition. The carries can be implemented as:

 c1 = G0 + P0c0
 c2 = G1 + P1G0 + P1P0c0
 c3 = G2 + P2G1 + P2P1G0 + P2P1P0c0
 c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0

• Above equations can be used to implement a 4-bit carry-lookahead adder

 4-bit Carry Lookahead adder
x3 y3 x2 y2 x1 y1 x0 y0
.
c4 c3 c2 c1
B cell B cell B cell B cell c0

s3 s2 s1 s0

G3 P3 G2 P2 G1 P1 G0 P0

Carry-lookahead logic

xi yi
.
Pi implemented as XOR
B-cell for a . of xi and yi instead of xi
single stage ci + yi . This is ok because
when xi = 1, yi = 1, Gi is
equal to 1.

Gi Pi si