VIETNAM NATIONLA UNIVERSITY, HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING
---oOo---

DIGITAL SYSTEM DESIGN WITH HDL

CE213.O12.MTCL.2

LAB REPORT 1
VIETNAMESE NAME : HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG
VERILOG TRÊN MODELSIM

ENGLISH NAME: GUIDE TO PRACTICE DESIGNING CIRCUITS USING

VERILOG ON MODELSIM

STUDENT NAME: Trương Duy Đức

STUDENT ID: 21521970
Lecturer: Tạ Trí Đức
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

Contents
1. Content of Lab................................................................................................................................3
1.1 ModelSim ............................................................................................................................................ 3
1.2. Hardware Description Language ........................................................................................................ 3
2. ADDER ...........................................................................................................................................3
2.1 HALF-ADDER........................................................................................................................................ 3
2.2. FULL-ADDER ....................................................................................................................................... 4
3. HDL Code .......................................................................................................................................6
3.1. CLA_3B ............................................................................................................................................... 6
3.2. CLAM_M............................................................................................................................................. 6
3.3. TESTBENCH......................................................................................................................................... 7
3.4. TOP ..................................................................................................................................................... 8
4. Modeling .......................................................................................................................................9
4.1. Structural Model ................................................................................................................................ 9
4.2. Behavioral Model ............................................................................................................................... 9
5. Schematic ......................................................................................................................................9
5.1. CLA_3B ............................................................................................................................................... 9
5.2. CLA_M .............................................................................................................................................. 10
5.3. TOP ................................................................................................................................................... 10
5.3. Difference between CLA_3B and CLA_M ......................................................................................... 10
6. Simulation and Evaluation ............................................................................................................ 11
6.1. Simulation ........................................................................................................................................ 11
6.1.1. Waveform ................................................................................................................................. 11
6.1.2. Transcipt.................................................................................................................................... 11
6.2. EVALUATION ..................................................................................................................................... 12

1
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

Pictures
Figure 1: True table of Half-Adder ............................................................................................................... 4
Figure 2: Schematic Diagram of Half-Adder Circuit.................................................................................... 4
Figure 3:True table of Full-Adder ................................................................................................................. 5
Figure 4: Schematic Diagram of Full-Adder Circuit .................................................................................... 5
Figure 5: Schematic of CLA-3B circuit ........................................................................................................ 9
Figure 6: Schematic of CLA-M circuit ....................................................................................................... 10
Figure 7: Schematic of TOP ........................................................................................................................ 10
Figure 8: waveform form Quartus .............................................................................................................. 11
Figure 9: waveform form Modelsim ........................................................................................................... 11
Figure 10: Transcipt with 100% pass .......................................................................................................... 11

2
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

1. Content of Lab
Learn the basics of Verilog and the "Modelsim" practice tool. Learn basic operations on
modelsim.

1.1 ModelSim
ModelSim is a widely-used simulation and verification tool for digital circuit design,
supporting VHDL and Verilog. Its features include simulation capabilities, a waveform
viewer for result analysis, support for design hierarchy, advanced debugging tools, and
testbench development for comprehensive design testing. With integration options for
other EDA tools, it facilitates a streamlined design process. Available in different
editions, it serves both educational and professional purposes, aiding in the development
and validation of complex digital systems.
1.2. Hardware Description Language
Hardware Description Language (HDL) is a specialized programming language
used for designing electronic circuits and systems. It allows engineers to describe the
behavior and structure of digital hardware, enabling the simulation and synthesis of
complex designs. VHDL and Verilog are the two main types of HDL widely used in the
industry. HDLs provide a way to model both the behavior and structure of digital
systems, from high-level architectural design to low-level circuit representation. They are
essential for designing and implementing integrated circuits, FPGAs, and ASICs. HDLs
play a crucial role in the development of modern electronic systems, providing a
standardized and efficient method for describing and realizing complex hardware designs.
2. ADDER
Adder circuits are useful for performing arithmetic operations in computers,
especially in the arithmetic logic unit (ALU). There are two common types of adder
circuits: half adders and full adders. A half adder can only add two single bits and output
a sum and a carry. A full adder can add three bits, including the carry from the previous
operation, and output a new sum and carry. By connecting multiple full adders together,
we can create a wide adder to add numbers with multiple bits
2.1 HALF-ADDER
Half adder is the simplest of all adder circuits. Half adder is a combinational
arithmetic circuit that adds two numbers and produces a sum bit (s) and carry bit (c) both
as output. The addition of 2 bits is done using a combination circuit called a Half adder.
The input variables are augend and addend bits and output variables are sum & carry bits.
A and B are the two input bits.

3
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

True table:

Figure 1: True table of Half-Adder

Schematic Diagram of Half-Adder Circuit

Figure 2: Schematic Diagram of Half-Adder Circuit

2.2. FULL-ADDER
The full adder is a little more difficult to implement than a half adder. The main
difference between a half adder and a full adder is that the full-adder has three inputs and
two outputs. The two inputs are A and B, and the third input is a carry input CIN. The
output carry is designated as COUT, and the normal output is designated as S.

4
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

True table:

Figure 3:True table of Full-Adder

Schematic Diagram of Full-Adder Circuit :

Figure 4: Schematic Diagram of Full-Adder Circuit

5
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

3. HDL Code
3.1. CLA_3B
module CLA_3b(A,B,Cin,S);
input [2:0] A,B;
input Cin;
wire Cout;
output [3:0] S;
wire [2:0] G,P;
wire [1:0] C;
wire [5:0] W;

and a0(G[0],A[0],B[0]);
xor x0(P[0],A[0],B[0]);
and a1(G[1],A[1],B[1]);
xor x1(P[1],A[1],B[1]);
and a2(G[2],A[2],B[2]);
xor x2(P[2],A[2],B[2]);

and pc0(W[0], P[0],Cin);

or o0(C[0],W[0],G[0]);

and pc1(W[1],W[0],P[1]);
and pc2(W[2],G[0],P[1]);
or o1(C[1],G[1],W[1],W[2]);

and pc3(W[3],W[1],P[2]);
and pc4(W[4],W[2],P[2]);
and pc5(W[5],G[1],P[2]);
or o2(Cout,G[2],W[3],W[4],W[5]);

xor s0(S[0],Cin,P[0]);
xor s1(S[1],C[0],P[1]);
xor s2(S[2],C[1],P[2]);
and s4(S[3],Cout,1);

endmodule
3.2. CLAM_M
module CLA_M(A,B,Cin,S);
input [2:0] A,B;
input Cin;
output [3:0] S;

6
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

assign S=(A+B+Cin);
endmodule
3.3. TESTBENCH
`timescale 1ns/100ps
module CLA_testbench();
reg[2:0] A,B;
reg Cin;
wire [3:0] S,mS;
initial
begin
#640 $stop;
end
initial
begin
Gen();
end
top inst0(.A(A),.B(B),.Cin(Cin),.S(S),.mS(mS));
task Gen;
begin
A<=0;
B<=0;
Cin<=0;
forever begin
#5 A<= (A+1);
if(A==3'b111)
begin
#0 B<=(B+1);
if(B==3'b111)
begin
#0 Cin<=(Cin+1);
end
end
if((S==mS))
#0 $display("Expected result: %d .Simulation result: %d --
>PASS",S,mS);
else
#0 $display("Expected result: %d .Simulation result: %d --
>FAIL",S,mS);
end
end
endtask
endmodule

7
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

3.4. TOP
module top(A,B,Cin,S,mS);
input [2:0] A,B;
input Cin;
output [3:0] mS,S;
CLA_M inst0(.A(A),.B(B),.Cin(Cin),.S(S));
CLA_3b inst1(.A(A),.B(B),.Cin(Cin),.S(mS));
endmodule

8
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

4. Modeling
4.1. Structural Model
The structural model describes a system using basic components such as digital
gates and adders. In structural modeling, the programmer or the designer thinks about the
circuit as a box or a module. It is encapsulated from the outer environment. In other
words, it communicates with the outer environment through inputs and outputs.
4.2. Behavioral Model
The structural model describes a system using basic components such as digital
gates and adders. In structural modeling, the programmer or the designer thinks about the
circuit as a box or a module. It is encapsulated from the outer environment. In other
words, it communicates with the outer environment through inputs and outputs.
5. Schematic
5.1. CLA_3B

Figure 5: Schematic of CLA-3B circuit

9
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

5.2. CLA_M

Figure 6: Schematic of CLA-M circuit

5.3. TOP

Figure 7: Schematic of TOP

5.3. Difference between CLA_3B and CLA_M

Because CLA_3B is a structural model while CLA_M is a behavioral model, we will
notice that the schematic of CLA_3B is intricately constructed using gates, clearly
illustrating the internal circuitry and how it functions.
On the other hand, CLA_M, as a behavioral model, highlights the circuit's functionality
and performance under various conditions, without delving into its internal structure. It
provides valuable insights into the system's response to inputs, aiding in understanding its
operational behavior.

10
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

6. Simulation and Evaluation

6.1. Simulation
6.1.1. Waveform

Figure 8: waveform from Quartus

Figure 9: waveform from Modelsim

The inputs are A, B, and CIN. Here, A and B are 2-bit numbers, and CIN is the carry bit (1 bit). The
circuit's function is to compute A+B+CIN, producing a 3-bit result C.The outputs are S and mS, which
respectively represent the results of CLA_3b and CLA_M.

As observed, both the results of CLA_3b and CLA_M are identical and correct according to the
principles of the addition circuit.

6.1.2. Transcipt

Figure 10: Transcipt with 100% pass

11
LAB 1: HƯỚNG DẪN THỰC HÀNH THIẾT KẾ VI MẠCH DÙNG VERILOG TRÊN MODELSIM

6.2. EVALUATION
Correct completion of lab requirements, circuits and results as predicted.

12