MAHESH HARIDASAN

O DESIGNATION/ROLE
Physical Design Engineer

O TOTAL EXPERIENCE
4 Years

O EMAIL ID
maheshharidasan2013@gmail.com

O PHONE NO
9495996769/8848374391

O HIGHEST EDUCATION
B.Tech ECE

O SKILL SET

O TOOLS
FC, Innovus, PrimeTime, Calibre

O LANGUAGES

TCL, VHDL, Verilog

Education

Degree School/College/ Board/ C.G.P.A / Year of

Institute Universi % passing
ty

B.Tech Vidya Academy of Science and Technology, Calicut 7.38 2017

 Thrissur

12th Paremekkavu Vidya Mandir, CBSE 86.6% 2013

Thrissur

10th Paremekkavu Vidya Mandir, CBSE 8.8 2011

Thrissur

Profile Summary
o Has 4 Years of Experience in Physical Design and has handled blocks with gate count greater
than 1M and frequency 1GHz
o Has worked in 3nm , 7nm, 14nm technologies.
o Experienced in implementation of timing and functional ECOs.
o Well versed in TCL language and its implementation in PD flows.

Projects undertaken

Project 1

Project 3 nm
Role : PnR for 1 block

Location Bangalore

Details 190 - Macros

frequency: 1 GHz
2 functional clocks
970K Standard Cells
777 Ports
Rectilinear shape & 15 Metal layers
2 Modes and 10 Corners
1 – Power domain

Challenges o High Macro count made it challenging to converge the

design for congestion and timing
o Very high number of shorts > 50k were found in the PRO
database near the pins of the macro ,brought it down to

2
 < 100 using routing blockages and cell obstructions on
the hms
o Pins of certain cells were not no track , had to discuss
with standard cells team to find work around to proceed
with flow until a proper standard cell design was
released.
o The initial netlist of these HMs were not optimized . After
discussion with designer an optimized netlist for the HMs
were released and thereby congestion and timing started
to converge.
o IR drop was reported by power team near high activity
macro blocks, dense power mesh had to be created to
address the issue.

Tools Used Innovus , PrimeTime

Project 2

Project 7 nm
Role : PnR for 1 block

Location Bangalore

Details 57 - Macros
frequency: 750MHz
3 functional clocks
970K Standard Cells
777 Ports
Rectilinear shape & 14 Metal layers
2 Modes and 25 Corners
1 – Power domain

Challenges o Floorplan was had to go various changes as instructed from

the top level
o Pin access issues due to dense power mesh led to very high
run times during route and post route stages. Requested
with the power team for slight relaxation of pitch for lower

3
 layer power stripes.
o To meet the timing, bounds had to be created for very
critical hierarchies.
o To meet the hold timing for memory paths clock push had
to be done for certain memory paths having ample setup
margins.

Tools Used FC , PrimeTime

Project 3

Project 14 nm
Role : PnR for 1 block

Location Bangalore

Details 110 - Macros

Max frequency 800 MHz
3 - functional master Clocks, 2 - generated Clocks
390K Standard Cells
122 Ports
rectilinear & 12 Metal layers
2 Modes & 15 Corners
1 – Power domains

Challenges o The High macro count itself was a challenge to get an

optimized floorplan with a given area of 0.1mm2.
o Due to missing acc bit settings in the timing libs of
memories garbage values were found in the timing
report.
o Hierarchical and connectivity based ordering of the
macros were of paramount importance to converge the
congestion and timing.
o Group bounds for certain hierarchies were required to
place the associated cells together to meeting the timing
which otherwise the tool would scatter these cells to

4
 cater the improvement of congestion qor.
o Using PrimeTime and ECO operations the violating paths
were resolved.
o Min cut violations were observed and corrected using
Calibre .

Tools Used Innovus , Calibre , PrimeTime

Project 4

Project 14 nm
Role : PnR for 1 block

Location Bangalore

Details 89 – Macros
Max Frequency 833 MHz
4 - functional master Clocks, 2 - generated Clocks
1.1M Standard Cells
1200 Ports
Rectilinear shape & 12 Metal layers
2 Modes & 35 Corners
1 – Power domains

Challenges o Pins of certain macros were found in locations other than

the edges due to error in pin location coordinates present
in the LEF files corresponding to the macros.
o Found don’t use cells in the netlist during sanity checks
and reported the issue to the synthesis team.
o After CTS, found low strength clock buffers which led to
max transitions violations during initial iterations of the
design
o Reported to synthesis team and resolved the above
problem with updated clock spec file.
o Fixed max cap and max transitions violations in data path

5
 using TCL scripts.
o Electro migration problems were resolved with NDR
routing.

Tools Used ICC2 , PrimeTime , IC Validator

Project 5

Project 28 nm
Role : PnR for 1 block

Location Bangalore

Details 75 – Macros
Max frequency: 625 MHz
5 - functional master Clocks, 4 - generated Clocks
890K Standard Cells, 3.8K Ports, Rectilinear shape & 9 Metal layers
2 Modes & 52 Corners
2 – Power domain

Contribution o LSUP cell shorts were observed ( VDD and VDDH )due to
errors in LEF files during initial power grid DRC checks and
reported the same to the power team.
o Metal spacing violations were found in certain macros
during power grid connectivity checks.
o Reported to the IP team regarding the above issue.
o Manual fixing of shorts/ DRCs.
o Functional and time ECO operations were performed.

Tools Used ICC2 , PrimeTime , IC Validator