Independent University, Bangladesh

Department of Electrical and Electronic Engineering BAETE Accredited

Name: MD.Shybur Rahaman.

ID: 1811099.
Sec: 01.

Course Title : Digital Logic Design Lab

Course Code : EEE 232L / ETE 232L (New); ECR 205L (Old)
Instructor : Md. Tawhid Islam Opu
Experiment No. 04
Experiment Name : Designing and testing of 4-bit even parity generator and even parity
checker circuits using EX-OR gates.

OBJECTIVE:
 To verify the circuit of even parity generator
 To verify the circuit of even parity checker.
APPARATUS:
 IC 7486,
 Connecting wires,
 Digital Trainer board etc.
Thoery:

Parity Method -Scheme used for error detection during the transmission of data

Parity Bit -Additional bit that is attached to each code group so that the total number of 1s
being transmitted is always even (or always odd).
Example:
i) 101101110010100 – signal without p.b.
0101101110010100 – signal with p.b.
ii) 1011101001100 -- signal without p.b.
11011101001100 -- signal with p.b.
Parity Generator:
*Circuit that takes a set of data bits and produces the correct parity bit for the data.

Truth Table:
Pin Diagram:

XOR gate IC
Simulation of Parity Generator:

[(D3,D2,D1,D0= 0,0,0,0) ; (P=0)] [(D3,D2,D1,D0= 0,0,0,1) ; (P=1)]

[(D3,D2,D1,D0= 0,0,1,0) ; (P=1)] [(D3,D2,D1,D0= 0,0,1,1) ; (P=0)]

[(D3,D2,D1,D0= 0,1,0,0) ; (P=1)] [(D3,D2,D1,D0= 0,1,0,1) ; (P=0)]

 [(D3,D2,D1,D0= 0,1,1,0) ; (P=0)] [(D3,D2,D1,D0= 0,1,1,1) ; (P=1)]

[(D3,D2,D1,D0= 1,0,0,0) ; (P=1)] [(D3,D2,D1,D0= 1,0,0,1) ; (P=0)]

[(D3,D2,D1,D0= 1,0,1,0) ; (P=0)] [(D3,D2,D1,D0= 1,0,1,1) ; (P=1)]

[(D3,D2,D1,D0= 1,1,0,0) ; (P=0)] [(D3,D2,D1,D0= 1,1,0,1) ; (P=1)]

[(D3,D2,D1,D0= 1,1,1,0) ; (P=1)] [(D3,D2,D1,D0= 1,1,1,1) ; (P=0)]

Parity Checker:
* Circuit that takes a set of data bits (including the parity bit) and checks to see if it has the
correct parity.

Pin Diagram: Truth Table

XOR gate IC
Simulation of Parity Checker:

[(P,D3,D2,D1,D0 = 0,0,0,0,0) ; (E=0)] [(P,D3,D2,D1,D0 = 0,0,0,0,1) ; (E=1)]

[(P,D3,D2,D1,D0 = 0,0,0,1,0) ; (E=1)] [(P,D3,D2,D1,D0 = 0,0,0,1,1) ; (E=0)]

[(P,D3,D2,D1,D0 = 0,0,1,0,0) ; (E=1)] [(P,D3,D2,D1,D0 = 0,0,1,0,1) ; (E=0)]

 [(P,D3,D2,D1,D0 = 0,0,1,1,0) ; (E=0)] [(P,D3,D2,D1,D0 = 0,0,1,1,1) ; (E=1)]

[(P,D3,D2,D1,D0 = 0,1,0,0,0) ; (E=1)] [(P,D3,D2,D1,D0 = 0,1,0,0,1) ; (E=0)]

[(P,D3,D2,D1,D0 = 0,1,0,1,0) ; (E=0)] [(P,D3,D2,D1,D0 = 0,1,0,1,1) ; (E=1)]

[(P,D3,D2,D1,D0 = 0,1,1,0,0) ; (E=0)] [(P,D3,D2,D1,D0 = 0,1,1,0,1) ; (E=1)]

[(P,D3,D2,D1,D0 = 0,1,1,1,0) ; (E=1)] [(P,D3,D2,D1,D0 = 0,1,1,1,1) ; (E=0)]

[(P,D3,D2,D1,D0 = 1,0,0,0,0) ; (E=1)] [(P,D3,D2,D1,D0 = 1,0,0,0,1) ; (E=0)]

 [(P,D3,D2,D1,D0 = 1,0,0,1,0) ; (E=0)] [(P,D3,D2,D1,D0 = 1,0,0,1,1) ; (E=1)]

[(P,D3,D2,D1,D0 = 1,0,1,0,0) ; (E=0)] [(P,D3,D2,D1,D0 = 1,0,1,0,1) ; (E=1)]

[(P,D3,D2,D1,D0 = 1,0,1,1,0) ; (E=1)] [(P,D3,D2,D1,D0 = 1,0,1,1,1) ; (E=0)]

 [(P,D3,D2,D1,D0 = 1,1,0,0,0) ; (E=0)] [(P,D3,D2,D1,D0 = 1,1,0,0,1) ; (E=1)]

[(P,D3,D2,D1,D0 = 1,1,0,1,0) ; (E=1)] [(P,D3,D2,D1,D0 = 1,1,0,1,1) ; (E=0)]

[(P,D3,D2,D1,D0 = 1,1,1,0,0) ; (E=1)] [(P,D3,D2,D1,D0 = 1,1,1,0,1) ; (E=0)]

 [(P,D3,D2,D1,D0 = 1,1,1,1,0) ; (E=0)] [(P,D3,D2,D1,D0 = 1,1,1,1,1) ; (E=1)]

#Question:

i. What is Even Parity? Describe with Example.

ANS: Even Parity is the total number of bits in the message is made even. If number of
1s is even, parity bit value is 0. If number of 1s is odd, parity bit value is 1.
For example,

Signal (without parity bit): 1001010100110; 001011

Signal (with parity bit): 01001010100110; 1001011

ii. What is Odd Parity? Describe with Example.

ANS: Odd Parity is the total number of bits in the message is made odd. If number of 1s is
odd, parity bit value is 0. If number of 1s is even, parity bit value is 1.
For example,

Signal (without parity bit): 101010100110; 001011

Signal (with parity bit): 1101010100110; 0001011

 iii. Why EX-OR Gate is used to design both Parity Generator & Checker
circuit? Explain with proper logic.

ANS: The basic principle involved in the implementation of parity circuits is

that sum of odd number of 1s is always 1 and sum of even number of 1s is
always 0. Such error detecting and correction can be implemented by using
EX-OR gates. Since EX-OR gate produce 0 output when there are even
number of inputs, and EX-OR gate produce 1 output when there are odd
number of inputs.
For that reason in both case “Parity Generator” and “Parity Checker” used
EX-OR gate.
 LAB REPORT RUBRICS

Student Name MD. Shybur Rahaman. Student ID 1811099.

Course Title Digital Logic Design Lab . Course Code EEE 232L .
Term Spring Summer Autumn Year 2021.
Designing and testing of 4-bit even parity
Experiment Experiment
generator and even parity checker circuits using 04.
Name Number
EX-OR gates.
Submission
27/10/2021. Due Date 28/10/2021.
Date
Tick () on the appropriate box (any one from 1 to 5)
Rubrics (weight) Accomplished Intermediate Developing Intermediate Novice
(5) (4) (3) (2) (1)
Understanding Defined experiment Intermediate Defined Intermediate Defined
experiment’s requirements and between experiment between novice experiment
requirements assume circuit developing requirements and and developing. requirements and
(5%) specifications, if any, and assume circuit assume circuit
properly. accomplished. specifications, if specifications, if
any, moderately. any, poorly.

Building Circuit Conducted Intermediate Conducted Intermediate Conducted

and conducting experiment properly between experiment between novice experiment
experiment (5%) by building developing & moderately by and developing. poorly by
simulation circuit accomplished. building building
using required simulation circuit simulation
specification. using required circuit using
specification. required
specification.

Result and Analyzed and Intermediate The results are Intermediate The results are
analysis (5%) interpreted the results between analyzed to some between novice analyzed poorly
properly using the developing extent according and developing. due to
converter parameters. and to specified incomplete
accomplished. requirements. simulation.

Remarks / Answered the given Intermediate Answered Intermediate Answered the

Answering questions correctly between partially the between novice given questions
Question (5%) and describe the developing given questions and developing. incorrectly and
remarks properly. and and describe the describe the
accomplished. remarks remarks poorly.
moderately.

Sub Total
Deduction for late
submission / any
other issue
Total (20%)
20% of Total