Lap Top Repair Book Chapter 2 Chapter11 Analysis of Wistron OEM Laptop Circuit

Chapter 11
Analysis of Wistron OEM laptop circuit

The circuit and sequence of Wistron are not too many features,it can also be said that its
feature is quite satisfactory.The RTC circuit is similar to those of the Quanta,the battery is usually
not chargeable,the power-on sequence is the Intel standard sequence.This chapter is not much
introduced the RTC circuit and the power-on sequence,mainly to explain the protective isolation
and the standby circuit.Then,as Wistron HBU16-1.2 an example to analyze the protective isolation
and the standby circuit.
Analysis of Wistron HBU16-1.2 protective isolation circuit

Insert the adapter,producing AD_JK,added to the S pole of U1,though the partial pressure of
R2 and R1 produced the low level of 6.3V,control U1 conducted and produced AD+(when
inserted the adapter,because EC is no power,AD_OFF is low level;only when the system program
control forced to discharged the battery,then EC will send the high level of AD_OFF),is shown in
figure 11-1.
Figure 11-1 the screenshot of AD+ production circuit
AD+ produced the small current common point DCBATOUT through U2 body
diode,18.3V,is shown in figure 11-2.
Figure 11-2 the production of the small current common point

第 11 章纬创代工笔记本电脑电路分析
AD+ is added to the G pole of U7,makes it cut off,the battery is isolated,is shown in figure
11-3.
Figure 11-3 the screenshot of the battery isolation circuit
AD+ supplies the power to DCIN of the charge chip U44(MAX8731),and divides into the
voltage to ACIN,is shown in figure 11-4.
Figure 11-4 the screenshot of DCIN and ACIN circuit
When DCIN is power on,U44 outputs 5.4V MAX8731_LDO from LDO pin,is shown in
figure 11-5.
About the figure 11-6,is the relationship between DCIN and LDO of MAX8731 internal
block diagram.
Figure 11-5 LDO output
Figure 11-6 the internal principle diagram of LDO production
In the data manual of MAX8731,the screenshot of the electrical characteristic description
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笔记本电脑维修不是事儿
about DCIN effective value,is shown in figure 11-7,DCIN effective value is 8-26V,the under-
voltage lockout value is 7.4V(typical value).
Figure 11-7 the screenshot of the electrical characteristic description about DCIN threshold value in the data
manual of MAX8731
MAX8731_LDO supplies the power to VCC pin through R204,is shown in figure 11-8.
Figure 11-8 the circuit screenshot of LDO supply power to VCC
When VCC is power on,4.096V reference voltage REF produced by the MAX8731 internal,is
shown in figure 11-9.
The text of ACOK pin definition:：AC Detect Output. This open-drain output is high
impedance when ACIN is greater than REF/2. The ACOK output remains low when the
MAX8731 is powered down. Connect a 10kΩ pull up resistor from VCC to ACOK.
ACIN compared with the half of REF in the internal,when ACIN is greater than
REF/2(2.048V),ACIN open drain output,is shown in figure 11-10.
Figure 11-9 the internal principle diagram of the production of MAX8731 reference voltage
Figure 11-10 the screenshot of ACOK output principle of MAX8731
As long as AD+ voltage is higher than 17.767V,ACIN will be greater than 2.048V,ACOK
will open drain output ACAV_IN,is shown in figure 11-11.The calculation process is shown in
figure 11-12.
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Figure 11-11 the screenshot of ACOK output ACAV_IN
ACAV_IN is divided into the voltage by MAX8731_LDO to be 3.3V high level by

MAX8731_LDO,through Q3 to produce the low level of AD_IN# to EC(as the adapter test signal
of EC),is shown in figure 11-13.
The other path controls 3-4 pin conducted of U3,makes R183 grounded.The small current
common point through R182 and R183 to form partial pressure,and produces about 6V voltage to
send to 4 pin (G pole) of U2,the S pole of U2 is 18.3V,the G pole is 6.1V,U2 channel is fully
opened,AD+ directly flows to the common point,producing the large current common point,is
Figure 11-12 the screenshot of AD+ threshold value calculation
Figure 11-13 the screenshot of the adapter test signal production of EC
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Figure 11-14 the screenshot of the large current common point production circuit
Analysis of Wistron HBU16-1.2 standby circuit

After the common point voltage DCBATOUT producing,input to supply the power to
VIN of the standby chip U30.is shown in figure 11-15.
Figure 11-15 the circuit diagram of VIN supply power to U30
The standby chip is TPS51125,when it got VIN,because EN0 is grounded through 820K
resistance,set the linear voltage opened automatically,but close VCLK,is shown in figure 11-16.
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Figure 11-16 the screenshot of TPS 51125 circuit
According to TPS51125 working principle analyzed in the

9.2.2 section,after TPS51125 getting VIN and EN0,the chip outputs
+3VL,and renamed to be +3VL_KBC,is shown in figure 11-
17.+3VL_KBC is supplied to EC as the standby voltage,is shown in
figure 11-18.
Figure 11-18 the screenshot of EC standby power supply
After EC getting power supply,to supply the voltage to X2,crystal oscillator start,and send to
EC standby clock 32.768kHz,is shown in figure 11-19.
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Figure 11-19 EC standby clock
+3VL_KBC pulled up VCC_POR#,as the standby reset of EC,is shown in figure 11-20.
Figure 11-20 the principle of EC reset production
After the standby condition of EC being satisfied,reads ROM(U25) through SPI bus of
86,87,90,92 pin (shown in figure 11-21),ROM circuit is shown in figure 11-22.the power supply of
U25 is also came from +3VL_KBC.
Figure 11-21 SPI bus pin of EC
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Figure 11-22 the screenshot of U25 circuit
After EC reading the program normally,configured their own pin.Then,EC identifies the
adapter insert test signal AD_IN# of 93 pin,is shown in figure 11-23.
EC detects that the low level of the adapter is inserted an indication signal,then sends
automatically the high level of PWR_S5_EN,is shown in figure 11-24.
Figure 11-23 the adapter test signal of EC
Figure 11-24 E sends PWR_S5_EN
PWR_S5_EN controls Q42 conduction,Q40 and Q41 will cut off,is shown in figure 11-
25.51125_ENTRIP1 and 51125_ENTRIP2 are not grounded directly,it just can be grounded
through R498 and R508.
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Figure 11-25 thescreenshot of the circuit controlled by PWR_S5_EN
51125_ENTRIP1 and 51225_ENTRIP2 connected to 1 pin and 6 pin of TPS51125.According

to the pin definition of TPS51125 in the 9.2.12 section,it can open chip through the resistance
grounded and as an over-current threshold value setting.
TPS51125 outputs two paths of PWM power supply,is shown in figure 11-
27:3D3V_PWR,5V_PWR,through isolation point respectively to rename to be
+3VALW,+5VALW.
Figure 11-26 the screenshot of 1 pin and 6 pin of TPS51125
Figure 11-27 the screenshot of the circuit of 3D3V_PWR and 5V_PWR renamed
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+3VALW and +5VALW supply respectively to VCCSUS3_3 and V5REF_SUS of the South
bridge,as the South bridge standby voltage,is shown in figure 11-28 and figure 11-29.
Figure 11-28 3.3V standby voltage of the South bridge
Figure 11-29 5V standby voltage of the South bridge
EC delayed send PM_RSMRST#,is shown in figure 11-30.
Figure 11-30 EC sends PM_RSMRST#
PM_RSMRST# is converted to be RSMRST#_SB,is shown in figure 11-31.
Figure 11-31 PM_RSMRST# renamed to be RSMRST#_SB
RSMRST#_SB is sent to the South bridge,is shown in figure 11-32.
Figure 11-32 RSMRST#_SB is sent to the South bridge
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Chapter 12
Analysis of Compal OEM laptop circuit
The greatest feature of the motherboard designed by Compal is the protective isolation and
the standby circuit,the power-on sequence and the RTC circuit is almost the standard
sequence.This chapter introduces three kinds of Compal protective isolation circuit.Then explain
one of the Compal standby circuit.
Analysis of Compal LA_5891P protective isolation and the standby circuit
In this section,takes Compal LA_5891P as an example to analyze the protective isolation and
the standby circuit.
Insert the adapter,through the power connects to PJP1,and produces VIN,19V through
PL24,is shown in figure 12-1.The figure of Compal motherboard power interface is shown in 12-2.
Figure 12-1 the production of VIN
Figure 12-2 Compal motherboard power interface
VIN produces VS through the parallel connection of PD2,PR304 and PR305,and produces N1
through PQ42 body diode,changes to be CHGRTCP through PR306,then through PR309 to
produce N2 to supply the power to the pressure regulator,PU14 outputs 3.3V RTCVREF,is shown
in figure 12-3.
Figure 12-3 the production circuit of RTCVREF
VIN compares with RTCVREF after through PR297 and PR301 diving into the voltage,if the
voltage of VIN is higher than 17.24V(make a rough calculation after ignoring the hysteresis
resistance:the results of VIN/ (PR297+PR301) * PR301 is higher than 3.3V),the comparator will
open drain output,is diving into the voltage by VIN and through PD1 steady pressure to produce
the high level of PACIN and ACIN,is shown in figure 12-4.
Figure 12-4 the production circuit of PACIN and ACIN
If we count in the hysteresis resistance,the falling edge of the VIN voltage threshold value is
17.525V,the rising edge is 17.901V,is shown in figure 12-5.
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第 12 章仁宝代工笔记本电脑电路分析
VIN crosses PD14 and four parallel resistance,makes PQ67 conduction,power supply in
advance to B+,is shown in figure 12-6.(when PD14 pressure drop of
1mA,the voltage is about 0.7V,when pressure drop of 10mA,the
voltage is about 1V,you can consult the data manual of LL4148.)If
the value of resistance of B+ grounded is higher than 1.35kΩ(make
a rough calculation:if VIN is 19V,PD12 pressure drop is 1V,(19V-
1V)/(250+RB+)*RB+=15.2V,so RB+=1357Ω),the voltage B+ got is higher than 15.2V.
Figure 12-5 the screenshot of the VIN threshold value voltage
Figure 12-6 power supply in advance B+ production circuit
After the adapter testing,PACIN is high level,makes PQ69 conducted,and makes PR395 and
PR394 to be parallel connection,the value of resistance is 138kΩ after parallel connection,B+
through PR387 and divides into the voltage with the parallel resistance,is shown in figure 12-7.If
the voltage of B+ is higher than 15.2V(ignore the hysteresis resistance PR385),the voltage will
higher than 3.3V after dividing into the voltage,the comparator open drain outputs,and is pulled up
to be a high level by VL,ACON is not pulled low(VL comes from the standby chip,we will
analyze it in the standby circuit).
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Figure 12-7 the screenshot of the ignition loop circuit
If B+ exists short circuit,the value of resistance is less than 1.35kΩ,less the voltage value is
pulled below 15.2V,the voltage got by the resistance dividing into the voltage will be lower than
RTCVREF voltage 3.3V,the comparator 7 pin outputs the low level,then ACON,MAINPWON are
pulled low.This is the power supply in advance circuit,also called ignition loop.
The ignition loop is divided into three cases(ignore the hysteresis resistance).
When PACIN is low,PQ69 is cut off,PR394 is not grounded,does not participate in the partial
pressure circuit,B+ minimum can not be less than 6.6V(the battery mode).
When PACIN is high,but before +5VALW produced,PQ71 is cut off,PQ69 is
conducted,PR394 and PR395 being in parallel,then series partial pressure with PR387,B+
minimum can not be less than 15.2V(when the adapter is
just inserted).
When PACIN is high,+5VALW is produced,PQ71 is
conducted,PQ69 is cut off,PR394 is not grounded,as long
as B+ is not less than 6.6V,then it can make the
comparator open drain output the high level,ACON and
MAINPWON are not pulled low(the adapter mode,the
ignition has been completed).
As the figure 12-8 shown,after adding the hysteresis resistance,the detection threshold value
of B+,the adapter mode is 14.8V-15.9V,the battery mode is 6.2V-7.3V(select the intermediate
value).
About Compal machine,for example,non program controls the correction of the battery
electricity and forces to open the battery discharge,EC always outputs the low level of
ACOFF,PQ65 is cut off,PACIN is high,ACON is not pulled low by the comparator,PQ63 obtains
the G pole voltage with high level,PQ63 is conducted,is shown in figure 12-9.
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Figure 12-8 the text screenshot of B+ threshold value voltage settings in the adapter and battery mode
Figure 12-9 the circuit of PACIN and ACON
VIN produces P2 through the body diode of PQ51,through PR354 and PR361 then through
PQ63 to be grounded,and forms partial pressure,produces about 8V voltage to add to the G pole of
PQ51 and PQ52,make it conducted completely,VIN flows to B+,the common point of the large
current produced,is shown in figure 12-10.
159
Figure 12-10 the production circuit of the large current B+
ACON is high,and makes PQ59 conducted at the same time,PQ58 will be cut off,PQ56 will
also be cut off.
If ACON is low,or PACIN is low,it will make PQ63,PR354 and PR361 not partial
pressure,P2 with 18V through PR354 to pull up the G pole of PQ51.PQ52,two separate tubes are
cut off.
At the same time,PQ59 is cut off,the B pole of PQ58 is pulled up by VIN,PQ58 is
conducted,PQ56 is also conducted,P2 flows to the C pole through the E pole of PQ56,then added
to the G pole of PQ51,PQ52,and make it cut off.
The circuit of the battery isolation and discharge is shown in figure 12-11.
In the figure 12-11,when PACIN is high,PQ61 is conducted,pulls low the positive pole of
PD12,PD12 is cut off;ACOFF is also low,PD9 is cut off;the B pole of the triode PQ57 is pulled
down to be the low level by its own resistance,PQ57 is cut off,VIN through PR352 to pull up the G
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pole of PQ53,PQ53 is cut off,the battery is isolated.

If VIN is no power,the G pole of PQ53 will pulled down to the grounded by PR352,PQ53 is
conducted,the batter discharge.
If VIN is power on,but PACIN is low level,PQ61 is cut off,the positive of PD12 is pulled up
to be high by PR357,PD12 is conducted,PQ57 is also conducted,VIN through PR352 and PR356
divides into the voltage to the G pole of PQ53,PQ53 is conducted,the battery discharge.
Figure 12-11 the battery isolation circuit
If VIN is power on,PACIN is high level,but ACOFF is also high(when the program control
forces to discharge to the battery),PD9 is conducted,PQ57 will also be conducted,VIN through
PR352 and PR356 divides into the voltage to the G pole of PQ53,PQ53 is conducted,the battery
discharge.
Analysis of the production of VA(the adapter mode and the battery mode)
VS production circuit is shown in figure 12-12,look at the following analysis.
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Figure 12-12 VS production circuit
The adapter mode:VIN through PD2,then through PR304 and PR305 to produce VS directly.
The battery mode:BATT+ through PD3 to produce N1,sends it to 3 pin of PQ42,it can not be
conducted to VS.
PQ42 is a P channel,the condition of conduction is:when 51ON# is the low level,PR307 and PR308
forms partial pressure,produces relatively the low level about 2V,at this time,the G pole is 2V,the S pole
is 11V,VG<VS,PQ42 is conducted completely,producing VS.
So,in the battery mode,if VS want to be produced,it must set low 51ON#.
51ON# connects toD12 and Q32,after pressing the switch,ON/OFFBTN# is low,through D12
to pull 51ON# low,then produces VS,is shown in figure 12-13.
At the same time of triggering the switch,it will produce ON/OFF to send to EC,then EC
sends the high level of EC_ON to conduct Q32,and keep 51ON# to be low level.
(before triggered the boot pin of Compal,the voltage is about 17V in the adapter mode,and the
voltage is about 10V in the battery mode.)
Figure 12-13 51ON# circuit
The common point B+ is converted to be ISL6237_B+,supplies to 6 pin VIN of

PU16(RT8206),is shown in figure 12-14.According to the RT8206 data manual,the minimum
working voltage is 6V.
162
Figure 12-14 B+ supplies power to PU16
VS through the voltage stabilizing diode PD7 to reverse breakdown,then divided into pressure to
EN_LDO,is shown in figure 12-15(as long as VS is higher than 7.5V,it will higher than 2.4V after
reverse breakdown PD7,EN_LDO produced after dividing into pressure can be more than the threshold
value 1.6V of 4 pin).
Figure 12-15 EN_LDO production circuit
After PU16 obtaining VIN and EN_LDO,outputs the reference voltage 2VREF_ISL6237 and
the linear voltage,is shown in figure 12-16.
Figure 12-16 PU16 outputs LDO and VREF2
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VL through PR561 to pill up EN1 of RT8206,2VREF_ISL6237 is added to EN2.According to the

pin definition of TR8206,EN2 connects REF,sets that produce +5VALW first then to produce
+3VALW,is shown in figure 12-17.
Figure 12-17 the origin of EN1 and EN2
When MAINPWON is not pulled low by ignition circuit and also not pulled low by
temperature control circuit,EN1 is high level,RT8206 opens PWM1 first to control produce
+5VALWP,after +5VALWP being stable,then RT8206 opens PWM2 to produce +3VALWP(32
pin connects VL,11 pin is grounded,two path of PWM are set respectively fixed output 5V and
3.3V),is shown in figure 12-18.
Figure 12-18 RT8206 outputs two path of PWM
A path of MAINPWON connects the ignition circuit of PD15,the other path is connected to
164
3,4 pin of PU30,is shown in figure 12-19.This is a CPU temperature control circuit,when the
temperature increase,the resistance value of PH1 will decrease(NTC).When reach a certain
temperature,PU30 will pull MAINPWON low.
Figure 12-19 PU30 temperature chip circuit
165
The standby voltage +3VALWP renamed to be +3VALW through the isolation

point,+5VALWP renamed to be +5VALW through the isolation point,is shown in figure 12-20.
Figure 12-20 two voltages renamed
+3VALW supplies the power directly to EC,is shown in figure 12-21.
Figure 12-21 the standby power supply of EC
+3VALW produces +3V through the isolation point J5 to supply the standby voltage( @ next
to U14 indicates that U14 is not installed,J5 is short connected) to the bridge,is shown in figure 12-
22.
Figure 12-22 +3V production circuit
+5VALW renamed to be +5V through R169 to supply to V5REF_SUS of the bridge,is shown
164
in figure 12-23.
After RT8206 producing +3VALWP and +5VALWP normally,open drain outputs SPOK,is
Figure 12-23 the production of +5V
Figure 12-24 RT8206 outputs SPOK
SPOK controls PQ45 conducted after being pulled up to be high level by VL,B+ through
PR325 and PR327 partial pressure to control PQ44 conducted,producing +VSBP,is shown in
figure 12-25.
Figure 12-25 the production of +VSBP
After the standby voltage of EC being normal,the external crystal starts oscillator,is shown in
figure 12-26.
165
Figure 12-26 the standby clock of EC
+3VALW delays supply the reset to 37 pin,is shown in figure 12-27.
Figure 12-27 the standby reset of EC
EC starts to read the data of U31 through SPI bus of 119,120,126,128,configures GPIO pin,is
shown in figure 12-28.The circuit of U31 is shown in figure 12-29,U30 is not installed in the
figure.
Figure 12-28 EC reads the pin of BIOS
Figure 12-29 the screenshot of the place where U31 is
All of the above,this is the standby circuit,then EC will wait users to trigger the switch,and
send RSMRST# and PWRBTN# to the bridge,now we don’t detail.
Analysis of Compal LA-6631P protective isolation circuit
About Compal motherboard,the protective isolation and the ignition circuit of some models
have another way,next,as LA-6631P(GM45 series) an example to explain the protective isolation
principle.Let’s us look at the working principle of the protective isolation circuit,is shown in figure
12-30:VIN crosses four parallel resistance to reach PRECHG,one path of this voltage through PD7
and PQ27 to B+,the other path through PR43 and PR47 partial pressure to send ACSET pin of
PU4(ISL6251).
166
Figure 12-30 the power supply in advance B+
In the mode of the adapter power supply,ACOFF is low,and +5VALW is not produced,PD9
can not make PQ28 conducted,so PQ30 will be conducted,to make PR83 and PR86 partial
pressure to form the low level relatively,the small current B+ is produced.When the program
control the battery to correct the electricity,ACOFF is high,or after +5VALW producing
normally,this circuit will be shut down.
If B+ is short circuit,the voltage is pulled low,then PRECHG will also be pulled low,because
of the clamping action of LL4148,the voltage of PRECHG will be higher than B+ 1V(after
investigation,the voltage of LL4148 drops 1V).PRECHG through partial pressure,is sent to
ACSET of PU4(ISL6251).The indication in the ISL6251 data manual as follows:
ACSET ACSET is an AC adapter detection input. Connect to a resistor divider from the AC
adapter output.
ACPRN Open-drain output signals AC adapter is present. ACPRN pulls low when ACSET
is higher than 1.26V; and pulled high when ACSET is lower than 1.26V.
ACSET is defined to be AC adapter test output pin.
ACPRN is defined to be open drain output pin,when ACSET is higher than 1.26V,ACPRN is
pulled low,when ACSET is less than 1.26V,ACPRN is pulled up.that is to say,the threshold value
of ACSET is 1.26V,by the calculation of partial pressure [1.26/PR47* (PR43+PR47)],it can
conclude that PRECHG can not be less than 18.09V.Since B+ is produced by PRECHG through
PD7,so the minimum voltage of B+ is limited to be 17.09V,is shown in figure 12-31.
167
Figure 12-31 PRECHG partial pressure to ACSET
If B+ is not short circuit,the voltage of PRECHG is normal,ACSET is higher than

1.26V,ACPRN outputs the low level,PQ26 will be cut off,PACIN obtains the high level through
PR72 and PR74 partial pressure,at the same time,the high level of ACIN is sent to EC,is shown in
figure 12-32.
Figure 12-32 the production of PACIN and ACIN
The high level of PACIN through PR63 to make PQ20B conducted,VIN produces P2 through
PQ12 body diode then through PR41 and PR50 partial pressure to be about 8V,PQ12,PQ13 is
conducted,VIN crosses the protective isolation to produce the large current B+,is shown in figure
12-33.
168
Figure 12-33 the production circuit of the large current B+
When the program controls EC to correct the electricity of the battery,ACOFF is high,PQ24
is conducted,and pulls the G pole of PQ20 low,VIN_1 makes PQ17 conducted,then P2 through the
internal resistance of PQ15 partial pressure,PQ15 is PNP tube,the voltage of the B pole is less than
the E pole,E-C is conducted,and conducts P2 to the G pole of PQ12 and PQ13 directly,two P
channel tubes will be closed.VIN and B+ are isolated.
In addition,as shown in figure 12-34,when ACPRN is low level,PQ10 is cut off,VS makes
PQ9 conducted through PR36,pulls the G pole of PQ8 low,PQ8 is cut off,ENTRIP1 and ENTRIP2
are not grounded(note:VS is produced directly just in the adapter mode,and it needs to trigger the
switch in the battery mode,then it will be produced,there is no difference with LA-5891P,not to
explain.If it exists the over-temperature,MAINPWON is low,it will also cut off PQ9）。
ENTRIP1 and ENTRIP2 of RT8205 are not grounded directly,but through the resistance
PR27,PR28 to be grounded,it can produce +3VALW,+5VALW successfully.
ENTRIP1 (Pin 1) Channel 1 enable and Current Limit setting Input. Connect resistor to
GND to set the threshold for channel 1 synchronous RDS(ON) sense. The GND-PHASE1 current-
limit threshold is 1/10th the voltage seen at ENTRIP1 over a 0.5V to 2V range. There is an internal
10µA current source from VREG5 to ENTRIP1. The logic current limit threshold is default to
169
200mV value if ENTRIP1 is higher than VREG5-1V.
Figure 12-34 the enable signal and the control circuit of the standby voltage
Analysis of Compal LA-6751P protective isolation circuit

First,insert the adapter,output VIN,is shown in figure 12-35.
Figure 12-35 the production of VIN
VIN needs to through the circuit to reach the common point B+,is shown in figure 12-36.VIN
through PQ301 body diode to produce P2,a little more than 18V,the conduction of PQ301 and
PQ302 needs that the G pole is the low level respectively.That is to say,there must have the high
level of PACIN,ACON and the low level of ACOFF (BATT_OUT is high level after powering
on,is not involved in the protective isolation control)in this circuit.
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Figure 12-36 the circuit of the common point production
Let’s look at the origin of PACIN,ACON and ACOFF.

The origin of PACIN and ACOFF:as shown in figure 12-37,it must be the low level of
ACPRN input,then PQ316 will be cut off,6251_VDD(ISL6251VDD pin outputs the linear voltage
5.075V) through PR338 and PR342 partial pressure to obtain the high level of PACIN with 3V,and
produce the high level of ACIN at the same time,ACIN is sent to EC.
Figure 12-37 the production of PACIN and ACIN
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ACOFF is the low level sent by EC,only when the system program controls the battery forced
discharge,EC will send the high level of ACOFF.
ACPRN comes from 23 pin of ISL625,is shown in figure 12-38.According to the data manual
of ISL6251,when ACSET pin is higher than 1.26V,ACPRN will output the low level.ACSET
comes from ACSETIN that VIN through PR306 and PQ312 partial pressure to obtain.
Figure 12-38 the production circuit of ACPRN
According to the calculation of the resistance parallel partial pressure,the minimum voltage of
VIN can not be less than 18.09V,if it is less than this voltage,after partial pressure,ACSETIN will
be less than 1.26V,is shown in figure 12-39.
The origin of ACON planned to use the mature ignition loop,but is not used in this
machine(@ means that the component is not installed),is shown in figure 12-40.
Figure 12-39 the calculation of VIN threshold value
Figure 12-40 the ignition loop
The origin of BATT_OUT: as shown in figure 12-42,VMB2 is the battery interface power
supply pin,6251REF comes from the reference voltage 2.39 output of ISL6251.When the voltage
of VMB2 is less than 9.08V,through PR212 and PR215 partial pressure to send to 5 pin of the
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comparator,and it will less than 2.39V of the comparator 6 pin,7 pin outputs the low level,PQ201
is cut off.
Figure 12-41 BATT_OUT control circuit
At the same time,it needs the low level of BATT_LEN# sent by EC,then PQ205 will be cut
off,+3VS through PR211 to pull up BATT_OUT to be the high level.But +3V is the power supply
in the state of the system S0,so this signal can control the protective isolation only in the boot
state,not to analyze at here.
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Chapter 13
Analysis of Invenyec OEM laptop circuit
Inventec is usually OEM for HP.In this chapter,as DosXX Dunkel 1.0(HP_6510b) an
example to explain part of the circuit of Inventec,the circuit of this type is basically completed by
the independent components,EC seldom participated in voltage control.It is very meaningful for
study of the circuit analysis.
Analysis of Inventec DosXX Dunkel 1.0 protective isolation circuit
The voltage +VADP of the adapter interface JACK1 needs through Q507 and Q514 to reach
the common point +VBATR,these two of field-effect tube is controlled by
ADP_EN#,BATCAL#,ACDRV#,is shown in figure 13-1.
In the figure 13-1,Q507 is P channel.It must have two conditions to conduct:ADP_EN# is
low,BATCAL# is high,the origin of them is shown in figure 13-2.
The circuit analysis in the figure 13-2:
LIMIT_SIGNAL is about 7V voltage from the adapter middle pin,+VADP is the adapter
voltage 19V,through R108 and R105,R104 partial pressure,then gets 5.9V of 2 pin,and less than
7V of 3 pin,the comparator outputs the high level ADP_ID,then sends to EC for adapter detection.
VADP through R108,R105 and R104 partial pressure to be 4.8V to send to 5 pin,is less than
7V of 6 pin,the comparator outputs the low level ADP_EN#.
The low level of ADP_EN# makes Q7 cut off,ADP_EN is high,sends to EC,because it’s no
power at this time,SLP_S3_3R is low,Q545 is cut off,BATCAL# is pulled up to get the high level
by the adapter voltage through R9252.
Then,Q507 is conducted successfully,and produces +ADPBL.
In the figure 13-1,if Q514 is conducted completely,it needs the low level of ACDRV# sent by
U5(BQ24703),the specific process is that,+VADPBL in the left side of Q514 through the body
diode between the D pole and S pole and D510 supplies the small current to the common point
+VBATR,is shown in figure 13-3.
+VBATR renamed to be +VBATP after crossing the jumper wire PAD6,supplied to VIN of
the standby power management chip TPS51120,as the main power supply,is shown in figure 13-
4.Because EN3,EN5 of the chip is hung in the air,according to the pin definition of
TPS51120,En3,EN5 being hung in the air will produce automatically VREG3 and
VREG5.VREG5 retraces to supply the power to V5FILT,and produces the reference voltage with
2VREF.
Figure 13-1 the common point production circuit
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第 13 章英业达代工笔记本电脑电路分析
Figure 13-2 the control circuit of Q507
Figure 13-3 the production circuit of the small current common point
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176
Figure 13-4 TPS51120 circuit

As shown in figure 13-5,the small current +VBATR is sent to 22 pin VCC of BQ24703 to be the
power supply,+VADPBL through the resistance R27,R26,R31 series partial pressure,and added to 5 pin
of the comparator U1,to compare with the voltage of 2VREF.If the voltage of +VADPBL is higher than
10.87V,the 7 pin of the comparator U1 will open drain output and the adapter is inserted the detection
signal ADP_PRES,is pulled up to be the high level by +V3AL through R89.ADP_PRES through the
resistance R91 to send to ACDET pin of BQ24703,is higher than the internal threshold value
1.246V,BQ24703 is identified to be the state of the adapter inserted,and outputs the low level of
AC_DRV#,the G pole of Q514 is conducted after getting the low level through the resistance R565 and
R575 partial pressure,the large current common point +VBATR is produced(the comparator also
outputs the charging open signal AC_AND_CHG from 1 pin,sends to ENABLE of BQ24703,as the
charging enable signal).
Figure 13-5 the screenshot of BQ24703 circuit
Analysis of Inventec DosXX Dunkel 1.0 standby circuit

In the figure 13-4,the common point voltage +VBATR is supplied to the VIN pin of the
standby voltage chip TPS51120,because EN3,EN5 is hung in the air,is set to be opened
automatically the internal linear steady pressure VREG3 and VREG5.TPS51120 outputs
+V3AL,+V5AL.+V3AL is supplied to U14(EC,SMC_KBC1070) as its standby power supply,is
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Figure 13-6 the standby power supply of EC
After EC power supply being normal,the external 32.768kHz from 70 pin and 71 pin crystal
oscillated,is shown in figure 13-7.
Figure 13-7 the standby clock of EC
In the figure 13-7,77 pin of EC is the reset signal.The origin is:+V3AL through R123 and
C50 delays sent to the 2 pin high level of U10,U10 is synthetic,it will output the high level of
VCC1_POR#_3 from 4 pin,is shown in figure 13-8.
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Figure 13-8 the reset production circuit of EC
The adapter is inserted the detection signal ADP_PRES to sent to U27,is shown in figure 13-
9,U27 is the OR gate,as long as there is a high level input to 1 pin or 2 pin,it will output the high
level.The high level output by the 4 pin of U27 is sent to EN1,EN2 of U28,U28 produces the
standby voltage +V3A,+V5A,and supplies to VCCSUS3_3,V5REF_SUS of the South bridge
respectively.(KBC_PW_ON is sent by EC after triggering the switch in the battery mode.In the
battery cell mode,there is no ADP_PRES,so there is no +V3A,+V5A standby voltage in standby,it
needs to be opened by KBC_PWR_ON after triggering.)
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180
Figure 13-9 the production of +V3A,+V5A

After the condition of standby being satisfied,its internal procedure configures all of GPIO
signals,output RSMRST# by GPIO07,is shown in figure 13-10.RSMRST# phase with(connected
together) the signal output by 30 pin of TPS51120(as shown in figure 13-9),then to send to
RSMRST# pin of the South bridge,to inform the South bridge that the standby voltage is normal at
this time.
Figure 13-10 EC sends RSMRST#
Next,EC waits users to press the power key,then to complete the subsequent trigger and
power-on action,we will not explain.
Analysis of Inventec feature circuit
There is several more features of Inventec circuit,such as “OCP” circuit and “Big OR
GATE” circuit.OCP circuit is the over-current protection circuit,and the “Big OR GATE” circuit,is
the name called by the author.Let’s look at the working principle of these two circuit.
Analysis of OCP circuit
As Inventec DosXX Dunkel 1.0 an example to explain OCP circuit in this section.In the
figure 13-11,+VBDC is the battery discharging port,through the current sense resistor with
0.015Ωto make a new name +VBDCR,because the resistance value is very small,two of voltage
can be seen as the same.(calculated as 3 core series battery,3*3.7≈11V,takes an integer,is
convenient to calculate.)
In the figure 13-12,U505 is LM358,is the
operational amplifier,+ is the non-inverting input
terminal,- is the inverted input terminal.When V+ >V-,
outputs VCC logic,when V+<V-, outputs GND
logic.Note,GND with 4 pin is not grounded,is
connected to 11V of +VBDCR,that is to say,when
V+<V- ,the output should be 11V.VCC power supply
of 8 pin is from the voltage of MAX_LX5 and +V5S
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lifting pressure,and produces the voltage about 16V on the energy-storage capacitor,is higher than
the GND terminal 11V to 5V,it can satisfy the power supply requirement of the operational
amplifier.+ terminal of 3 pin is 11V of +VBDC.
Figure 13-11 the current sense resistor
Figure 13-12 the screenshot of U505 circuit
It’s worth noting that,the booster circuit is provided by +V5S through Q38,and is controlled
by ADP_PRES through Q39,that is to say,under the case of no power or the adapter inserted,it can
not boost,and the operational amplifier is not working.
The origin of the voltage of MAX_LX5 is the phase pin of +V5A voltage output by the
standby chip U28 in the figure 13-13,the square wave outputs.The voltage of pulse crest value
produced by the Q42 conducted is equal to the voltage of +VBATP,the crest voltage is equal to
11V in the battery mode.
Figure 13-13 the origin of MAX_LX5
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In the figure 13-12,the chip U504 is not 431 output by the ordinary 2.5V,is 431L of 1.24V
(when R and C are connected together,it acts as an voltage-regulator diode,the voltage of R
terminal is always higher then A terminal to 1.24V).The A terminal is also not grounded in the
figure,connects +VBDCR of 11V,so we can know that the R terminal is A+1.24V=12.24V(VCC
pin of the operational amplifier through R516 to supply the electric power),12.24 of REF terminal
through three resistances to reach to A terminal,if there have the differential pressure,then there
have the partial pressure: 100kΩ,691Ω,7.68kΩ series partial pressure,calculated that 2 pin of U505
is 11.095V,the specific calculation is [1.24V/(100kΩ+ 619Ω+7.68kΩ)*(619Ω+7.68kΩ)+11V]。
When the machine is normal,11V of 3 pin is less than 11.095V of 3 pin, V+< V-，1 pin
outputs GND,is 11V,through R517 to supply to the E pole of Q509,the B pole is +VBDCR
11V,the triode is not conducted,the Poweramp is no action.
When the Poweramp is short circuit,+VBDCR is pulled low,the R terminal of 431L is also
lower,then the voltage of 2 pin of the operational amplifier is also low,when the voltage of 2 pin is
less than 11V,the voltage of 3 pin of the operational amplifier will higher than 2 pin,and outputs
VCC,is 16V.16V to the E pole of Q509 is higher than the B pole +VBDCR,then the triode is
conducted.16 will through the D17 conduction to reach to the back comparator.The electric current
calculation 0.095V/0.015=6.3A,is the large current.
As shown in figure 13-14,the voltage of 11 pin of the operational amplifier U2 is that +V5S
through the resistance 133kΩ and 80.6kΩ resistance partial pressure to obtain 1.88V,and through
the voltage of 13 pin and 10 pin to produce a sustaining voltage of 1.88V to 8 pin.16V from D17
enter into 9 pin,9 pin is higher than 8 pin,and outputs a OCP_OC of 3.3V from 14 pin.
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Figure 13-14 the production circuit of OCP_OC#
One path of OCP_OC leads to EC;and another path reaches to the G pole of Q6,Q6 is N
channel field-effect tube,the high level will be conducted,OCP_OC# will be pulled to the
ground,OCP_ON# leads to the South bridge,the South bridge will send STPCLK# to stop the CPU
internal clock after being pulled low,makes CPU break off,and reduces the working current.At this
time,we can clearly feel that the response speed of the system reduces a lot.
At the same time,OCP_OC is also controlled by PWR_GOOD_3,when PWR_GOOD_3 is the
low level,D8 is conducted,pulls OCP_OC low.That is to say,when the power-on sequence is not
completed,OCP circuit is forbidden.
Above is the action process of OCP circuit in the battery mode.
Next,let’s look at OCP circuit in the adapter mode.
In the figure 13-15,when the voltage of LIMIT_SIGNAL becomes higher(not original adapter)
or the voltage of VBIAS reduces a certain extent,when the voltage from Q22 conducted is higher
than 1.88V,one path makes Q21 conducted,pulls the SRSET voltage low,stops charging,and
another path reaches to OCP execution circuit of U2,starts OCP_OC#.
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Figure 13-15 the production circuit of OCP_OC# in the adapter mode
LIMIT_SIGNAL is the current detection voltage of the adapter,the manufacturer set it to be

about 7V.VBIAS is the sampling voltage 5.79V got from the adapter after through the resistance
R108,R105,R104 partial pressure,is shown in figure 13-16.
Figure 13-16 the production circuit of VBIAS
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The whole OCP circuit is shown in figure 13-17.
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Figure 13-17 the whole OCP circuit
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Analysis of Big OR GATE circuit

There have the design of “Big OR GATE” circuit (called by the author) in many Inventec
motherboard.In this section,as S-SERIES(HP_6531s) an example to explain the “Big OR GATE”
circuit.In the figure 13-18,+V3S is not pull-up called usually.
Figure 13-18 the screenshot of the “Big OR GATE” circuit
In fact,it’s a node voltage,+V3S and +V5S through R130 and R131 to connect together,and
through R129 to be grounded.Then these two voltages input side by side,and through the voltage
division circuit output by a resistance,it can calculate by the formula of I1+I2=I3.
参考资料：节点电流定律（基尔霍夫电流定律 KCL） http://baike.baidu.com/view/
3283687.htm。
The reference data:the node current law(Kirchhoff’s Current Law)
http://baike.baidu.com/view/ 3283687.htm。
Calculated by the calculation:if the voltage of 3.3V and 5V is enough,then the voltage is
2.189V after partial pressure,is shown in figure 13-19.
In the figure of circuit,the opposition terminal input of the comparator is 2VREF,thus we can
calculate that +V3S can not be less than 2.727V,the result is shown in figure 13-20.
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Figure 13-19 the computational process of the node voltage
Figure 13-20 the computational process of the threshold value voltage of +V3S
At the same time,we can calculate that +V5S can not be less than 4.141V,is shown in figure
13-21.
So,this circuit is used to detect the voltage value of V3S and V5S,in the figure 13-22,if
VCCP_PG signal is low,it will cause R97 and R129 series,the value of resistance becomes
lower(other signal is in a similar way).
Figure 13-21 the computational process of the threshold value of +V5A
Figure 13-22 the screenshot of VCCP_PG circuit
By calculating, 10kΩand 49.9kΩ are in series,t value of resistance is only 8.33kΩ.Now,even

if the voltage of +V3S and +V5S is enough,the voltage also cannot be higher than 2VREF.The
actual result is 0.674V,is shown in figure 13-23.(in the figure,the value of resistance synchronous
reduced 1000 times)
Figure 13-23 the result of the node voltage when VCC_PG is low level
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Chapter 14
Analysis of Intel PCH sequence(I3/I5/I7)
PCH is the platform controller hub.Intel PCH is the single bridge chipset in the Intel
company,the product of the first generation PCH is Intel 5 series,such as Intel HM55 and so
on,matches the first generation I3/I5/I7 CPU;the second generation and the third generation is Intel
6 and Intel 7 series,matches the second generation and the third generation I3/I5/I7 CPU,these two
of generations is almost the same,CPU is in common used.The newest fourth generation has been
released,is Intel 8 series.PCH chip has all functions of the original ICH,also has the function of
management the engine of the original MCH.It dose not matter to call PCH the North bridge or the
South bridge.In this chapter,we mainly introduce the main feature of Intel 5 series,6 series and 7
series sequence.
About Intel ME and Intel AMT
Intel ME is the Intel Management Engine,is the independent hardware inset the North bridge
or PCH.ME firmware(ME FW) and the BIOS motherboard are usually kept in the same chip,but
they are independent mutually.The architecture of Intel ME and ME firmware is shown in figure
14-1.
Figure 14-1 the architecture figure of Intel ME and ME firmware
Intel starts introduce the management technology called “iAMT” in ICH7.Intel AMT(Intel
Active Management Technology) is the embedded system integrated in the chipset in effect,it does
not depend the specific the operating system,it is the biggest difference between iAMT and the
remote control software.
The embedded operating system of AMT technology integrates in the BIOS chip,the function
is realized by ME.This technology can not to depend the real-time status of the hardware,it can
start up,maintain,shutdown independently and other operation,even if its in the system with
crash,power off or blue screen,even been closed,it can still work,of course,it also can enter into
BIOS to operate.AMT needs to match the special server-side software to work.
Intel AMT technology can appear as a subsystem been independent of existing operating
system,because of the environment independent of the operating system,when the operating
system is broke down,the administrator can remote monitoring and manage client-side.By this
technology,the computer been controlled also can remote manage and detect system when the
operating system is damaged or the system is broke down,or when the system goes wrong,it can
send the warning message ,to detect the software and hardware,remote update BIOS and virus
code and the operating system,even when the system is power off,it can also manage work by the
website,then it has worked out the problem troubled IT manager:users closed the safety and
management software on the PC deliberately or by accident,which leads to unacceptable
management.These features can significantly reduce the administrative cost for the company user.
When the system supported AMT is in the S5 sleeping state,ME module,the clock chip,Intel
PHY LAN,SPI BIOS,MEMORY (CHANNEL0 DIMM0) need to be powered on.
Inter Chipset starts from ICH8M,in the ACPI,dormant logical control signal is added a
SLP_M#. The pin definition screenshot of SLP_M# is shown in figure 14-2.
14-2 the pin definition screenshot of SLP_M#
【Explanation】This signal is used to control the power of Inter AMT subsystem.When the
ME firmware does not exist, the timing step of SLP_M# is consistent with SLP_S3# (while
generating on / off).
ICH8、ICH9 also redefined the functions of SLP_S4#,increased S4_STATE#. the pin
definition screenshot of SLP_S4# of ICH8,ICH9 is shown in figure 14-3.
14-3 the pin definition screenshot of SLP_S4#
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第 14 章 Intel PCH 时序（I3/I5/I7）分析
【Explanation】SLP_S4#: when the system is in the state of S4,S5 sleeping,is used to control
the switch of the voltage controlled by itself.
Comment:when the system opens the AMT function,is used to control the switch of the
memory voltage.In the state of M1(when the main platform is in the state of S3～S5 and the
subsystem of ME is running),SLP_S4# is forced to be pulled up by SLP_M#,is used to open the
memory voltage when the system is in the state of AMT.
The pin definition screenshot of S4_STATE# of ICH8,ICH9 is shown in figure 14-4.
Figure 14-4 the pin definition screenshot of S4_STATE#
【Explanation】the index signal of S4 state:when this signal is low level,it means that the
main platform is in the state of S4 or S5.When ME forced to pull up SLP_S4#,this signal can be
used to inform that the equipment system on-board is in the state before S3.
It added CLPWROK from ICH starting,and renamed to be MEPWROK after 5 series
chipset,the 6 series chipset renamed to be APWROK.The pin definition screenshot of MEPWROK
is shown in figure 14-5.
Figure 14-5 the pin definition screenshot of MEPWROK
【Explanation】ME Power Good:when this signal is effective,it means that ME module

power supply has been stable.
When the AMT function is closed,the sequential relationship of each sleeping control
signal is shown in figure 14-6.After triggering,SLP_S5# is set up to be high first,then SLP_S4#
and S4_STATE# are set up to be high,SLP_S3# is set up to be high at last,the timing sequence
of SLP_M# and SLP_S3# is same.
Figure 14-6 when AMT function is closed,the timing sequence of each sleeping control signal
When AMT function is opened,the timing sequence of each sleeping control signal is shown
in figure 14-7.SLP_M# is set up to be high in advance,SLP_S4# is also set up to be high.After
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receiving triggering or other awakening signal,SLP_S5# is set up to be high first,then S4_STATE#

is set up to be high to replace the original SLP_S4#,SLP_S3# is set up to be high at last.
Figure 14-7 when AMT function is opened,the timing sequence of each sleeping control signal
When AMT function is opened,the logic of each sleeping control signal is shown in the table
14-1.
Tablet 14-1 when AMT function is opened,the logic table of each sleeping control signal
状态
S0 S3 S4 S5
信号
SLP_S3# 1 0 0 0
SLP_S4# 1 1 1 1
SLP_S5# 1 1 1 0
S4_STATE# 1 1 0 0
SLP_M# 1 1 1 1
When AMT function is opened,the system is in the state of S5 sleeping,SLP_S4# is used to

control the reservation of the memory voltage,SLP_M# is used to control the clock chip,part of C-
LINK,the reservation of Intel PHY LAN,SPI BIOS or other voltage.We can open or shield AMT
function in the CMOS settings.
After PCH,SLP_S4# no longer follows SLP_M# to start,and cancel S4_STATE#.When the
chipset of PCH opened AMT function, only ME module,network card,BIOS need to be supplied
power.
The 5 series chipset still retains SLP_M#,the 6 series chipset renamed it to be SLP_A#,but it
still used to control the power supply of ME module.The 5 series and 6 series chipset also add
SLP_LAN#,the pin definition is shown in figure 14-8.
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Figure 14-8 the pin definition screenshot of SLP_LAN#
【Explanation】LAN subsystem sleeping control,when SLP_LAN# is ineffective,the power

of the network card must to be retained;when SLP_LAN# is effective,the power supply of the
network can be closed.When SLP_LAN# is in the state of S0 and SLP_M#/SLP_A# is
ineffective,it keeps to be ineffective all the time.
Added ACPRESENT adapter detection signal and SUS_PWR_DN_ACK signal,is shown in
figure 14-9.
Figure 14-9 the pin definition screenshot of ACPRESENT and SUS_PWR_DN_ACK
【Explanation】ACPRESENT:is used for the mobile system.The signal sent from EC,to
indicate that the power supply origin is alternating current or the system battery.The high level
refers to alternating current power supply.
SUS_PWR_DN_ACK:the signal sent from ME module to EC,the high level means that it
does not need to hang the power.
Analysis of Intel HM55 series chipset timing sequence
The timing sequence of Intel 5 series chipset is shown in figure 14-10,the explanation of the
signal in the figure is below.
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Figure 14-10 the timing sequence of Intel 5 series chipset
VCCRTC:3V power supply sent from the motherboard to PCH bridge,supplies the power to
RTC circuit of the bridge,to save the CMOS parameter.
RTCRST#/SRTCRST#:3V high level sent from the motherboard to the bridge,the reset signal
of RTC circuit.Start from ICH9,there have two resets.
32.768kHz:32.768kHz crystal next to the bridge,the bridge supplies the power to the
crystal,and the crystal supplies the frequency to the bridge.
VCCSUS3_3:the motherboard supplies the power to the bridge,3.3V.
RSMRST#:the motherboard sent the ACPI reset signal with 3.3V high level to the bridge,it
means to inform the bridge that the standby voltage has been normal at this time.
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SUSCLK:the bridge sends 32.768kHz clock.If EC is built-in crystal,SUSCLK is usually sent

to EC,synchronous clock.
PWRBTN#:the bridge receives the falling edge trigger signal,3.3V-0V-3.3V,to inform the
bridge that it can exit the sleep state.
SLP_S5#:after the bridge receiving PWRBTN#,set up SLP_S5# high to be 3.3V,it means that
it exits the shutdown state.
SLP_S4#:the bridge set up SLO_S4# high to be 3.3V,it means that it exits the sleep state.
SLP_S3#:the bridge set up SLP_S3# high to be 3.3V,it means that it exits the standby state
and enter the S0 boot state.
SLP_M#:start from ICH8,added SLP_M#,is sent by the bridge and used to open the control
signal of ME module,3.3V.
If there have ME firmware on the motherboard,when it opens AMT function,this signal will
produce before triggered;when it closes AMT function,this signal timing sequence is consistent
with SLP_S3#.
If there haven’t ME firmware on the motherboard,not support AMT,SLP_M# hung is not to
be used.
SLP_LAN#:LAN subsystem sleep control,controls the power supply of the network card.If
the motherboard not uses Intel integrated network card,this signal is not to be used.If the
motherboard uses Intel integrated network card,and supports network awaken,then this signal is
high in the standby;when it not supports the network awaken,this signal follows SLP_M# or
SLP_S3#.
VCCME:the power supply(power supply to achieve AMT function) of ME module,is
controlled by SLP_M#.When SLP_M# is hung up(there haven’t ME module on the
motherboard),VCCME uses the power supply of S0 state directly,such as the bus power supply
and VCC3_3.
VDIMM:refers to the memory power supply,is controlled by SLP_S4#.
VCC:refers to the voltage in the S0 state of the bridge power supply and the bus power
supply,is controlled by SLP_S3#.
VCC_CPU:the motherboard sends the core power supply to CPU,is also controlled by
SLP_S3#,it will delay.
SYS_PWROK:sent 3.3V high level to the bridge by CPU power management chip,is equal to
VRMPWRGD.
PWROK:the motherboard sends 3.3V high level to the bridge,it means that the voltage of S0
state is normal(the bridge and the bus power supply).
MEPWORK:ME module power good,3.3V.When there have ME firmware,MEPWROK is
controlled by ME module power supply;and when there haven’t ME firmware,MEPWROK
connects together with PWROK.
LAN_RST#:after the network card power supply being normal,the motherboard sent the reset
signal to the network card controller of the bridge,we can understand that it is the power good
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signal of the network card.If the motherboard not uses Intel integrated network card,this signal is
forced to be grounded.
Clock Chip Outputs:the clock chip is opened,and outputs each group of the clock.
PROCPWRGD:the bridge sent PG to CPU,it means that the core voltage of CPU is normal.
DRAMPWROK:the bridge sent PG to CPU,it means that the memory module power supply
of CPU is normal.Open drain outputs,it should be external pulled up.
PLTRST#:the platform reset 3.3V sent by the bridge,as CPU reset by conversing(is usually
series partial pressure).
Analysis of the chipset timing sequence above Intel HM65 series
The timing sequence of Intel 6 series chipset is shown in figure 14-11,the explanation of the
signal in the figure is below.
Figure 14-11 the timing sequence of Intel 6 series chipset
VCCRTC:sent 3V power supply to PCH bridge from the motherboard,supplies the power to RTC
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of the bridge,to save CMOS parameter.

RTCRST#/SRTCRST#:sent 3V high level to the bridge from the motherboard,the reset signal
of RTC circuit.Start from ICH9,there have two resets.
32.768kHz:32.768kHz crystal next to the bridge,the bridge supplies the power to the
crystal,and the crystal provides the frequency to the bridge.
VCCDSW3_3:the motherboard provides the deep sleep well power supply to the
bridge,3.3V.When it not supports the deep sleep,this voltage connects with VCCSUS3_3.
DPWROK:the motherboard sent 3.3V high level to the bridge,refers to the VCCDSW3_3
power good,3.3V.When it not supports the deep sleep,this signal connects with RSMRST#.
SLP_SUS#:deep sleep state indicator signal,it can be used to open the voltage of S5
state,such as VCCSUS3_3.When it not supports the deep sleep,SLP_SUS# is hung up.
VCCSUS3_3:the motherboard sent the standby power supply to the bridge,3.3V.
RSMRST#:the motherboard sent ACPI reset signal of 3.3V high level of the bridge,to inform
the bridge that the standby voltage is ready now.
SUSCLK:the bridge sent 32.768kHz clock,but it not necessarily be adopted by the
motherboard.
PWRBTN#:the bridge received the falling edge trigger signal,3.3V-0V-3.3V,informed the
bridge that it can exit the sleep state.
SLP_S5#:after the bridge receiving PWRBTN#,set up SLP_S5# to be 3.3V,it means that it
exits the shutdown state.
SLP_S4#:the bridge sets up SLP_S4# to be 3.3V,it means that it exits the sleep state.
SLP_S3#:the bridge sets up SLP_S3# to be 3.3V,it means that it exits the standby state,and
enters the S0 boot state.
SLP_A#:the bridge sent the power open signal of the active sleep circuit,used to open ME
module power supply.
If there have ME firmware on the motherboard,when it opens AMT function,this signal will
produce before triggered;when it closes AMT function,this signal timing sequence is consistent
with SLP_S3#.
If there haven’t ME firmware,is not support AMT,SLP_A# hung not uses.
SLP_LAN#:LAN subsystem sleep control,controls the network card power supply.If the
motherboard not uses Intel integrated network card,this signal is not adopted.If the motherboard
uses Intel integrated network card,and supports the network awaken,this signal is high when it is in
standby;when it not supports the network awaken,this signal follows SLP_A# or SLP_S3#.
VCCASW:the power supply of the active sleep circuit,is controlled by SLP_A#.When
SLP_A# is hung up(there haven’t ME firmware on the motherboard),VCCASW adopts the power
supply of S0 state directly.
VDIMM:refers to the memory power supply,is controlled by SLP_S4#.
VCC:refers to the voltage of S0 state or the main power supply or others of the bridge,is
controlled by SLP_S3#.
195
PWROK:the motherboard sent 3.3V high level to the bridge,it means that the voltage of S0
state is ready for the bridge and the bus power supply.
APWROK:ASW power good,when it opens AMT function,APWROK is controlled by AMT
voltage,when it closes AMT function,APWROK is consistent with PWROK.
DRAMPWROK:the bridge sent PG to CPU,informs CPU that memory module power supply
is ready.
25MHz Crystal Osc:6 series chipset has not the clock chip,the bridge added 25MHz
crystal,supplied the reference frequency to the external clock module.
PCH Output Clocks:the bridge outputs each group of clock.
PROCPWRGD:the bridge sent PG to CPU,it means that the non-core voltage of CPU is ready.
CPU SVID:CPU_SVID is a group of signal sent to CPU power supply chip by CPU,it
consists of the standard serial bus consisted of DATA and CLK and ALERT# signal with the
function of reminder,is used to control CPU core voltage and The integrated graphics power
supply.
After PROCPWRGD being effective,CPU sent SVID.
VCCCORE_CPU:the core voltage of CPU.
SYS_PWROK:CPU power supply chip sent 3.3V high level to the bridge,it means that CPU core
voltage is ready.
PLTRST#:the bridge sent the platform reset 3.3V,as CPU reset by conversing.
The timing sequence of Intel 7 series and 8 series is almost consistent with Intel 6 series.We
don’t explanation.
196

Lap Top Repair Book Chapter 2 Chapter11 Analysis of Wistron OEM Laptop Circuit

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Lap Top Repair Book Chapter 2 Chapter11 Analysis of Wistron OEM Laptop Circuit

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Chapter 11

Analysis of Wistron OEM laptop circuit

Analysis of Wistron HBU16-1.2 protective isolation circuit

Figure 11-1 the screenshot of AD+ production circuit

Figure 11-2 the production of the small current common point

Figure 11-3 the screenshot of the battery isolation circuit

Figure 11-4 the screenshot of DCIN and ACIN circuit

Figure 11-5 LDO output

Figure 11-6 the internal principle diagram of LDO production

In the data manual of MAX8731,the screenshot of the electrical characteristic description

Figure 11-8 the circuit screenshot of LDO supply power to VCC

Figure 11-10 the screenshot of ACOK output principle of MAX8731

Figure 11-11 the screenshot of ACOK output ACAV_IN

ACAV_IN is divided into the voltage by MAX8731_LDO to be 3.3V high level by

Figure 11-12 the screenshot of AD+ threshold value calculation

Figure 11-13 the screenshot of the adapter test signal production of EC

Analysis of Wistron HBU16-1.2 standby circuit

Figure 11-15 the circuit diagram of VIN supply power to U30

Figure 11-16 the screenshot of TPS 51125 circuit

According to TPS51125 working principle analyzed in the

Figure 11-18 the screenshot of EC standby power supply

Figure 11-19 EC standby clock

Figure 11-20 the principle of EC reset production

Figure 11-21 SPI bus pin of EC

Figure 11-22 the screenshot of U25 circuit

Figure 11-23 the adapter test signal of EC

Figure 11-24 E sends PWR_S5_EN

Figure 11-25 thescreenshot of the circuit controlled by PWR_S5_EN

51125_ENTRIP1 and 51225_ENTRIP2 connected to 1 pin and 6 pin of TPS51125.According

Figure 11-26 the screenshot of 1 pin and 6 pin of TPS51125

Figure 11-28 3.3V standby voltage of the South bridge

Figure 11-29 5V standby voltage of the South bridge

EC delayed send PM_RSMRST#,is shown in figure 11-30.

Figure 11-30 EC sends PM_RSMRST#

PM_RSMRST# is converted to be RSMRST#_SB,is shown in figure 11-31.

Figure 11-31 PM_RSMRST# renamed to be RSMRST#_SB

RSMRST#_SB is sent to the South bridge,is shown in figure 11-32.

Figure 11-32 RSMRST#_SB is sent to the South bridge

Figure 12-1 the production of VIN

Figure 12-2 Compal motherboard power interface

Figure 12-3 the production circuit of RTCVREF

Figure 12-4 the production circuit of PACIN and ACIN

Figure 12-6 power supply in advance B+ production circuit

Figure 12-7 the screenshot of the ignition loop circuit

Figure 12-9 the circuit of PACIN and ACON

Figure 12-10 the production circuit of the large current B+

pole of PQ53,PQ53 is cut off,the battery is isolated.

Figure 12-11 the battery isolation circuit

Figure 12-12 VS production circuit

Figure 12-13 51ON# circuit

The common point B+ is converted to be ISL6237_B+,supplies to 6 pin VIN of

Figure 12-14 B+ supplies power to PU16

Figure 12-15 EN_LDO production circuit

Figure 12-16 PU16 outputs LDO and VREF2

VL through PR561 to pill up EN1 of RT8206,2VREF_ISL6237 is added to EN2.According to the

Figure 12-17 the origin of EN1 and EN2

Figure 12-18 RT8206 outputs two path of PWM

Figure 12-19 PU30 temperature chip circuit

The standby voltage +3VALWP renamed to be +3VALW through the isolation

Figure 12-20 two voltages renamed

+3VALW supplies the power directly to EC,is shown in figure 12-21.

Figure 12-21 the standby power supply of EC

Figure 12-22 +3V production circuit

Figure 12-23 the production of +5V