CHAPTER Instruction Set of 8085 Microprocessor INTRODUCTION A microprocessor performs a task by executing a program written for that program. Program is a set of instructions written to solve a problem. Instructions are the directions which a microprocessor follows to execute a task or part of a task. The language which a computer can understand is known as computer language. Broadly, computer language can be divided into two parts as high level language and low level language. Low level language is machine specific. It is further divided as machine language and assembly language Machine language is the only language which a machine can understand. Instructions in this language are written in binary bits as a specific bit pattern. The computer interprets this bit pattern as an instruction to perform a particular task. The entire program is a sequence of the binary numbers. There are some basic problems with this machine language. This is a machine friendly language but not user friendly. Debugging is another problem associated with machine language. a To overcome these problems, programmers develop another way in which instructions are written in English alphabets. This new language is known as assembly language. The instructions in this language are termed as mnemonics. As microprocessor can only understand the machine language, so, mnemonics are translated into machine language either manually or by @ program known as assembler. 5960 + Microprocessor 8085 and Its Interfacing Though assembly language is user friendly but it is still machine de i. this problem, a programmer develops another language known as high level langua, Instructions written in this language are called statements. This language is e Maching independent. The examples of such language are C, C++, PASCAL, COBOL, and FOR’ etc. Pendent. To short In this chapter, we will discuss instruction format, addressing modes of microprocesso, 8085, instruction set of microprocessor 8085 and instruction code summary. 4.1 INSTRUCTION FORMAT An instruction is a command to the microprocessor to perform a given task on a specified data Each instruction has two parts: one is task to be performed, called the operation code (opcode), and the second is the data to be operated on, called the operand. The operand (or data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal register, memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is implicit, 41.1 Instruction Word Size ‘The 8085 instruction set is classified into the following three gtoups according to word size: 1. One-word or one-byte instructions 2. Two-word or two-byte instructions 3. Three-word or three-byte instructions In the 8085, byte and word are s) 'ynonymous because it is an 8-bit microprocessor. However, instructions are commonly referred to in terms of bytes rather than words, One-byte instructions A one-byte instruction includes the of me byte. Operand(s) are internal registers and are coded into the instruction, If there is no numeral present in the instruction then that instruction will be of one-byte, for example, MOV C, A, RAL, and ADD B, ete. Table 4.1 shows examples of one-byte instructions, peode and operand in the sa Table 4.1 One-byte Instructions Task Binary code Hex code Copy the contents of the accumulator in MOV GA 0100 1111 4FH the register C. Add the contents of register B to the contents of the accumulator Invert (compliment) each accumulator. Opcode Operand ADD B 1000 0000 80H it in the CMA None 0010 1111 2FHInstruction Set of 8085 Microprocessor 61 ‘These instructions are one-byte instructions performing three different tasks. In the first instruction, both operand Tegisters are specified. In the second instruction, the operand B is specified and the accumulator is assumed, Similarly, in the third instruction, the accumulator is assumed to be the implicit operand. These instructions are stored in 8-bit binary format in memory; each requires one memory location. Two-byte instructions In a two-byte instruction, the first byte specifies the operation code and the second byte specifies the operand. Source operand is a data byte immediately following the opcode. If an 8-bit numeral is present in the instruction then that instruction will be of two-byte. Here, the numeral may be a data or an address. For example, in MVI A, 35H and IN 29H, etc. In a two-byte instruction, the first byte will be the opcode and the second byte will be for the numeral present in the instruction. Table 4.2 shows the example of two-byte instructions. Table 4.2 Two-byte Instructions Task Opcode _Operand _Binary code Hex code Load an 8-bit data byte in MVI A, 35H 0011-1110 3EH First byte the accumulator. 0011 0101 35H Second byte Three-byte instructions In a three-byte instruction, the first byte specifies the opcode, and the following two bytes specify the 16-bit operand. The second byte is the low-order operand and the third byte is the high-order operand, If a 16-bit numeral is present in the instruction then that instruction will be of three-byte. Here, the numeral may be a data or an address, for example, in LXI H,3500H and STA 2500H, etc. Table 4.3 shows example of three-byte instructions. Table 4.3 Three-byte Instructions Task Opcode _Operand Binary code Hex code Transfer the program IMP. 2550H 1100 0011 Cs First byte sequence to the memory location 2085H. 0101 0000 50 Second byte 0010 0101 25 Third byte 4.1.2. Opcode Format In the case of microprocessor, the instruction or operation are specified by using specific bit pattern unique for each instruction. These bit patterns contain all the information about operation, register used, memory to be used. The register and register pair Rp are specified by ¢ shown in Table 4.4. using certain combination of bits. These combinations of bits ar62_+ Microprocessor 8085 and Its Interfacing Table 4.4 Bit Combinations of Registers and Register Pair eu coe Code B 000 00 c 001 1, D 010 i Bi ol 11 H 100 i 101 M 110 A Lit 4.2 ADDRESSING MODES OF MP 8085 Every instruction consists of two parts, i.c., what operation is to be performed (called operation code ot opcode), and on what this operation is to be performed (called operands). For example, in case of A + B, the + sign is the opcode, and A and B are the operands. : Each instruction performs an operation on the specified data called operand, An operand must be specified for an instruction to be executed. The operand may be in the general Purpose register, accumulator or in a memory location. The way in which the operand is specifieg in an instruction is called addressing mode. Various addressing modes used in mictoprocessoy 8085 are: 1. Immediate addressing 2. Register addressing 3. Direct addressing 4. Register indirect addressing 5. Implicit addressing 4.2.1 Immediate Addressing In immediate addressing mode, the operands are specified within the instruction itself. The instruction format of instructions with immediate addressing mode is shown in Figure 4.1 Opcode} 8-bit data JOpcode | Upper 8-bit | Lower 8-bit +t -byte » <—1-byte > +tbyte> <1-byte> <1-byte > +—— 2-bytes —_> ‘3-bytes ——__, Figure 4.1 Instruction format of the instructions with immediate addressing mode. Examples of immediate addressing mode MVI A, 05H_ =: Move 05H in the accumulator. ADI 06H : Add 06H to the contents of the accumulator. LXI H, 2500H : Load HL pair with 2500H.Se instruction Set ‘of 8085 Microprocessor» 63 When microprocessor executes the MVI A,0SH instniction, the processor fetches the first instruction byte and determines that it must fetch one more byte from the next memory . location, Similarly, when microprocessor executes the LXI H, 2500H instruction, the processor fetches the first instruction byte and determines that it must feich two more bytes from the next two memory locations. 4.2.2 Register Addressing ster addressing mode, the operands are in the general purpose registers We specify the fer in our instruction, The instruction format of instructions with immediate addressing mode is shown in Figure 4.2. af In re Opcode | Source register [Destination register] Toyte Figure 4.2 Instucion format ofthe instucions wit register addressing mode. é Most of the instructions that use register addressing deal with'8-bit Values. However, a few of these instructions deal with 16-bit register pairs. For example, the SPHL instruction moves, the contents of the H and L registers to SP. Examples of register addressing mode are as follows: MOV A, B:This instruction moves the contents of register B to register A or accumulator. ADD B_ : Add the contents of register B to accumulator. 4.2.3 Direct Addressing EL Ga, dy > The direct addressing mode is used when the operand is available/required at some memory or an 1 location. In this addressing mode, the address.of;the operand (data) is given in the instruction itself, The instruction format of direct addressing. mode is shown in. Figure.43. ist byte 2nd 3rd byte Opcode wake Figure 4.3 Instruction format of the instructions with direct addressing mode. s F Instructions that include a direct address require three-bytes of storage, one for the instruction code, and two for the 16-bit address in case of memory related operations and require two-bytes, for the instruction code, and other for 8-bit IO address. Examples of direct addressing mode are as follows: = STA 2400H : Store the content of the accumulator to memory location 2400H. IN 02H : Input the data from input port 02H in ‘accumulator.Instruction Set:ot 6085 Microprocessor + 65 modes. This is because both these addressing modes deal directly with the processor’s-hardware or with data already present in the hardware registers. Also in these adGressing modes, the instruction is always of one-byte and is fetched in a single machine cycle. Similarly, register indirect addressing mode is faster than direct addressing mode. As most of the time of the execution of an instruction is wasted in getting a data from the memory or on how many machine cycles are required to execute that instruction. Also the number of machine cycles depends on the number of bytes required to represent that instruction. Hence, as the number of bytes required representing an instruction increases, the execution time will also increase, For example, a three-byte instruction requires more time for execution as compared to a two-byte or a one-byte: instruction. So,iwe ican say that the number of memory accesses required is the most important factor in determining execution timing. For example, the CALL instruction, which is a three-byte instruction ‘onan Tie machine oe three to access the complete instruction and two more to push the contents of the program counter onto the stack. Now the same CALL operation can be performed by one-byte RSTn instruction. This instruction will be executed 'in just three’ memory cycles. 4.4 INSTRUCTION SET CLASSIFICATION An instruction is a binary bit pattern which performs a specific function in a system. The entire group of instructions of a system is called the instruction set. Instruction set determines what functions the microprocessor can perform with a singlé instruction. The ‘instructions in microprocessor 8085 can be classified into five functional, categories: 1. data transfer (copy) operations > AMARA SIR ’ 2. arithmetic operations NE, 4 3. logical operations rag 4. branching operations and 0 5. machine-control_ operations. 4.4.1 Data Transfer (Copy).Operations ‘This group of instructions copy data from a location called a source td another location called a destination, without modifying the contents of the source, In true sense, these instructions are not the data transfer instructions but data copy instruction because the source is not modified. A data can be available at: 1. Immediately available (Im) 2. available at some memory (M) : 3. available in some register (R) t 4, available at some 10 (10). And a data can be required at: 1. some memory 2. in some register 3. at some IO.66 + Microprocessor 8085 and its Interfacing Table 4.5 shows the possible data transfers. Table 45 Possible Data Transfer ata to transfer Tan 45, Posehie Dat TAT Im ba x R M A 10 = a are oe her memory, from memory to an IO, from anotl iagaacees ‘can communicate with accumulator only, A data cannot be transferred from "10 an IO to another IO, and from IO to memo 4.4.2 Arithmetic Operations ae ‘These instructions perform arithmetic operations, such as; addition, subtraction, increment, ang ese instructio1 decrement. or the contents of a register or the contents of a memory ition Any 8-bit number, : ¢ seen can be added to the contents of the accumulator and the sum is stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the contents of register B cannot be added directly to the contents of the register C). 8085 can also perform 16-bit, It can also perform BCD addition. Subtraction Any 8-bit number, or the contents of a register, or the contents of a memory location can be subtracted from the contents of the accumulator and the results stored in the accumulator, The subtraction is performed in 2’s compliment, and the results if negative, are expressed in 2's complement. No two other registers can be subtracted directly. 8085 do not perform 16-bit subtraction ee es ee fe ie ; eae ora memory location can be incremented or decrement by 1. These inererment silane ee cee oat be directly in the source itself, ie, without using ace i ‘ment operations can be performed , Le., ig accumulator. 44.3 Logical Operations These instructions perform v; i i 8085 can ae ee ery peical operations with the contents of the accumulator. (i) AND (ii) oR (iii) Exclusive-oR (iv) NoT (¥) Compare (Vi) Rotate,Instruction Set of 8085 Microprocessor + 67 Any 8-bit number, or the contents of a Tegister, ANDed, ORed, or Exclusive-ORed with the contents in the accumulator. The content of the accumulator or of a memory location can be logically of the accumulator. The results are stored nae can be complimented. Rotate Each bit in the accumulator can be shifted either left or right to the next position, Compare Any. S-bit numberof the contents of a rogigier, arp megnory location can te compared for equality, greater than, or less than, wi . ? Ss than, with th result is reflected by zero and carry flags 1¢ contents of the accumulator. The 4.4.4 Branching Operations This group of instructions transfers the control of microprocessor from one location to another location. 8085 can perform four types of branching operations. These are: 1. Jump within a program IMP 2. Jump from main program to sub-routine CALL 3. Jump from sub-routine to main program RET 4. Jump from main program to ISR RST Jump Conditional jumps are the important aspect of the decision-making process in the programming. These instructions test for a certain conditions (e.g., zero or carry flag), and alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called unconditional jump. Call, return, and restart These instructions change the sequence of a program either by calling a sub-routine or returning from a sub-routine. The conditional call and return instructions also can test condition flags. 4.4.5 Machine-control Operations These instructions control machine functions, such as halt, interrupt, or do nothing. 4.5 DATA TRANSFER INSTRUCTIONS This group contains 16 instructions. The various instructions of this group are as follows: 1, MOV Rd, Rs M, Rs Rd, M_: Copy from source to destination This instruction copies the contents of the source register or the memory into the destination register or in the memory location. The contents of the source will not alter. If one of the operands is a memory location, its location is specified by the contents of the HL registers. It is to be noted that the memory M cannot be replaced by its absolute address. For example, if we have to transfer the content of the memory location 1000H to accumulator, then we cannot write as MOV A, 1000H. The correct instruction will be MOVA, M, but before this instruction, HL pair must be loaded with 1000H. Example MOV A, B or MOV M, B68 * Microprocessor 8085 and Its Interfacing MOV Ra, Rs ___ Addressing mode Register addressing_ Number of bytes i Number of machine cycles 1 Number of T states 4T Flag No flag effected Encoding 0 DDD SSS _ DDD = destination register, SSS = source register MOV R, M MOV M, R ee ec Number of bytes 1 Number of machine cycles 2 Number of T states 7T Flag No flag effected Encoding 01 DDD 110 ‘Addressing mode Register indirect addressing Number of bytes 1 Number of machine cycles 2 Number of T states 7 Flag No flag effected Encoding 01 110 SSS 2. MVI Rd, data M, data: Move immediate 8-bit data to register or memory The 8-bit data is stored in the destination register or memory. If the operand is a memory location, its location is specified by the contents of the HL registers. Example MVI B, F7H or MVI M, SFH MVI R, Data Addressing mode Immediate addressing Number of bytes 2 Number of machine cycles 2 Number of T states 17 Flag No flag effected Encoding 00 DDD 110Instruction Set of 8085 Microprocessor + 69 MVI M, Data ‘Addressing mode Immediate addressing Number of bytes 2 Number of machine cycles 3 Number of T states 10T Flag No flag effected Encoding 01100110 EXAMPLE 4.1 Write a Program to load or store 49H and 35H in the register B and D. Solution The 49H and 35H can be loaded in the B and D register by using MVI instruction as MVI B, 49H MVI D, 35H EXAMPLE 4.2 Write a Program to load or store 49H in the register B and D. Solution The 49H can be transfer to B and D register either by using two MVI instructions or one MVI instruction and one MOV instruction. MVI B, 49H MVI D, 49H It is to be noted here that this program is four-bytes long. Alternatively MVI B, 49H MOVD, B This program consists of only three-bytes. So, here the latter program is preferred over the first program. 3. LXI Register pair, 16-bit data: Load register pair with immediate data sP : Load stack pointer with immediate data The instruction loads 16-bit data in the register pair designated in the operand. This instruction is similar to MVI instruction with one change and that is with MVI only 8-bit immediate data is transferred to any register or memory, whereas, LXI transfer 16-bit immediate data to only register pair or stack pointer (SP). Example LXI H, 2500H Addressing mode Immediate addressing Number of bytes 3 Number of machine cycles 3 Number of T states 10T Flag No flag effected Encoding 00 R, R, 0001 ee th shi OR Ry O0170 + Microprocessor 8085 and Its Interfacing ' EXAMPLE 4.3. Write a Program to load or store 49H and 35H in the memory location 2500H and 2501H. Solution ‘To transfer these two immediate data, we will use the instruction “MVI M, 8-bit immediate data’ and to specify the memory location we have to use HL pair. The Program wily be LXI H, 25001 MVI M, 49H LXI-H, 2501H MVI M, 35H EXAMPLE 4.4 Move the contents of the register pair DE to the memory location 9000H and 9001H. Solution ‘The register pair contents can be transferred by first initializing the HL. register pair with the memory location and then using the MOV instruction as: LXI H, 9000H MOV M, E LXI H, 9001H MOV M, D Here it should be noted that the lower byte (content of the E register) will go to the lower address (9000H here), and the higher byte (Content of D register) will go to the higher memory address (9001H here). 4. LDA 16-bit address: Load accumulator direct The contents of a memory location, specified by a 16-bit address in the operand, are copied to the accumulator. The contents of the source are not altered. For example, consider the example LDA 2500H. In this example, 2500H is the memory location from where the data is to be transferred to the accumulator. Figure 4.6 shows the operation of the LDA 2500H instruction. Memory 3FH | 2500H ae oFH Figure 4.6 Execution of LOA instruction.Instruction Set of 8085 Microprocessor + 71 Direct addressing Number of bytes 3 Number of machine cycles 4 Number of T states 13T Flag No flag effected Encoding 00111010 5. LDAX B/D Register pair: Load accumulator indirect The contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered. For example, if the register pair DE contains 2500H, then to execute the instruction LDAX D, microprocessor transfer the contents of the memory location pointed by DE (i.e., 2500H) to the accumulator as shown in Figure 4.7. D onE 25H | OOH desea Memory 3FH | 2500H + ‘Accumulator 3FH | LDAXD. Figure 4.7 Execution of LDAX instruction, Here it is to be noted that the HL register pair cannot be the operand in LDAX instruction. This is because MOV A, M and LDAX H will exactly be the same. ‘Addressing mode Register indirect addressing Number of bytes 1 Number of machine cycles 2 Number of T states 77 Flag No flag effected Encoding 2AH (LDAX B), 1AH (LDAX D) 2 . STA 16-bit address: Store accumulator direct The contents of the accumulator are copied into the memory location specified by the 16-bit address given in the instruction. This is a three-byte instruction, the second byte Specifies the low-order address and the third-byte specifies the high-order address.72_+ Microprocessor 8085 and Its Interfacing ' For example, to execute the instruction STA 2500H, microprocessor will store contents ef zccumulator in the memory location 2500H as shown in Figure 4g "* Memory (——|_3FH_| 2500H Accumulator 3FH ‘STA 2500H Figure 4.8 Execution of STA instruction. ‘Addressing mode Direct addressing Number of bytes 3 Number of machine cycles 4 Number of T states BT Flag No flag effected 00110010 Encoding 7. STAX B/D Register pair: Store accumulator indirect The contents of the accumulator are copied into the memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered, For example, if the DE register pair contains 2500H, then to execute the STAX D instruction microprocessor will transfer the contents of accumulator to the memory location 2500H (i.e. specified in DE) as shown in Figure 4.9. It is to be noted that the HL register pair cannot be the operand in STAX. De 25H | OOH Memory *| 3FH | 2500H + Accumulator 3FH ‘STAXD Figure 4.9 Execution of STAX D. adInstruction Set of 8085 Microprocessor + 73 Register indirect add 1 “Number of byt Number of machine cycles 2 Number of T states T Flag No flag effected ‘Bian 02H (STAX B), 12H (STAX D) 8. LHLD 16-bit address: Load H and L registers direct ‘The instruction copies the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H, The contents of source memory locations are not altered. This is a three-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Figure 4.10 shows the execution of the instruction LHLD 2S00H. Ho Memory 20H | FH F3H | 2500H 20H | 2501H LHLD 2500H Figure 4.10 Execution of LHLD 2500H. Addressing mode Direct addressing Number of bytes 3 Number of machine cycles 5 Number of T states 16T Flag No flag effected Jaton spe seeeceecrs 00101010 9. SHLD 16-bit address: Store H and L registers direct The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a three-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Figure 4.11 shows the execution of the SHLD 2S00H instruction.74 + Microprocessor 8085 and ts Interacing Ho 29H | FSH 25014 ‘SHLD 2500H Figure 4.11 Execution of SHLD 2500H Direct addressing Addressing mode Number of bytes Number of machine cycles 7 5 16T Number of T states No flag effected Flag Encoding 00100010 10. XCHG: Exchange H and L with D and E The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E. To execute this instruction microprocessor first transfer the content of the L register to the temporary register Z and then the content of E register to L and then content of Z register to £ register. Similarly, the content of H is first transfer to W register, content of D is transferred to H and then W is transferred to D register. In short, we can say that HL is the first transferred to temporary register WZ, then DE to HL and finally WZ to HL. Example XCHG Addressing mode Implicit Number of bytes 1 Number of machine cycles 1 Number of T states 4T Flag No flag effected Encoding 11101011 EXAMPLE 4.5 Write the program of Example 4.4 using the SHLD and XCHG instructions Solution Here first the contents of DE register pair is transferred using exchange instruction to HL register pair. Then HL pair is stored in memory using SHLD instruction. XCHG SHLD 9000H Note that the program in Example 4.4 is 8-bytes long, whereas, this program is only +byts long. ositalia ia cac acuta Instruction Set of 8085 Microprocessor + 75 EXAMPLE 4.6 Write a program to transfer two 16-bit data from the memory location 290082001 and 2002&2003 to DE and HL register pairs respectively. Solution LHLD 2000H XCHG LHLD 2002H Here the first instruction loads the data from memory location 2000H to L register and data from memory 2001H to H register. The second instruction exchange the data of HL register pair and DE register pair (i.e. data from 200082001 is transferred to DE register pair). The third instruction load the data from memory location 2002H &2003H to HL register pair. 11. SPHL: Copy H and L registers to the stack pointer. The instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered. Example SPHL Addressing mode Implicit Number of bytes 1 Number of machine cycles 1 Number of T states or Flag No flag effected Encoding 11111001 12, PCHL: Copy H and L registers to the program counter. The instruction loads the contents of the H and L registers into the program counter register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered. Example PCHL Addressing mode Implicit Number of bytes 1 Number of machine cycles 1 Number of T states oT Flag No flag effected Encoding 11111001 13. XTHL: Exchange H and L with top of stack. The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered. Figure 4.12 shows the execution of XTHL instruction. In this figure, the numbers written in circles show the execution sequence of this instruction.68 * Microprocessor 8085 and Its Interfacing MOV Ra, Rs ___ Addressing mode Register addressing_ Number of bytes i Number of machine cycles 1 Number of T states 4T Flag No flag effected Encoding 0 DDD SSS _ DDD = destination register, SSS = source register MOV R, M MOV M, R ee ec Number of bytes 1 Number of machine cycles 2 Number of T states 7T Flag No flag effected Encoding 01 DDD 110 ‘Addressing mode Register indirect addressing Number of bytes 1 Number of machine cycles 2 Number of T states 7 Flag No flag effected Encoding 01 110 SSS 2. MVI Rd, data M, data: Move immediate 8-bit data to register or memory The 8-bit data is stored in the destination register or memory. If the operand is a memory location, its location is specified by the contents of the HL registers. Example MVI B, F7H or MVI M, SFH MVI R, Data Addressing mode Immediate addressing Number of bytes 2 Number of machine cycles 2 Number of T states 17 Flag No flag effected Encoding 00 DDD 110—_ Instruction Set of 8085 Microprocessor - 69 MVI M, Data ‘Addressing mode Immediate addressing ‘Number of bytes 2 Number of machine cycles 3 Number of T states 10T Flag No flag effected Encoding 01100110 EXAMPLE 4.1 Write a Program to load or store 49H and 35H in the register B and D. Solution The 49H and 35H can be loaded in the B and D register by using MVI instruction as MVI B, 49H MVI D, 35H EXAMPLE 4.2, Write a Program to load or store 49H in the register B and D. Solution The 49H can be transfer to B and D register either by using two MVI instructions or one MVI instruction and one MOV instruction, MVI B, 49H MVI D, 49H It is to be noted here that this program is four-bytes long. Alternatively MVI B, 49H MOVD, B This program consists of only three-bytes. So, here the latter program is preferred over the first program. 3. LXI Register pair, 16-bit data: Load register pair with immediate data SP : Load stack pointer with immediate data The instruction loads 16-bit data in the register pair designated in the operand. This instruction is similar to MVI instruction with one change and that is with MVI only 8-bit immediate data is transferred to any register or memory, whereas, LXI transfer 16-bit immediate data to only register pair or stack pointer (SP). Example LXI H, 2500H Addressing mode Immediate addressing Number of bytes 3 Number of machine cycles 3 Number of T states 10T Flag No flag effected Encoding 00 R, Rp 0001of EXAMPLE 4.3° Write a Program to load or store 49H and 35H in the memory location 2S00H and 2501H. Solution To transfer these two immediate data, we will use the instruction ‘MVI M, 8-bit immediate data’ and to specify the memory location we have to use HI pair. The Program wil] be 70 _+ Microprocessor 6085 and Its interlacing LXI H, 2500H MVI M, 49H LXI H, 2501H MVI M, 35H EXAMPLE 4.4 Move the contents of the register pair DE to the memory location 9000H and 9001H. Solution ‘The register pair contents can be transferred by first initializing the HL register pair with the memory location and then using the MOV instruction as: LXI H, 9000H MOV M, E LXI H, 9001H MOV M, D Here it should be noted that the lower byte (content of the E register) will go to the lower address (9000H here), and the higher byte (Content of D register) will go to the higher memory address (9001H here). 4. LDA 16-bit address: Load accumulator direct The contents of a memory location, specified by a 16-bit address in the operand, are copied to the accumulator. The contents of the source are not altered. For example, consider the example LDA 2500H. In this example, 2500H is the memory location from where the data is to be transferred to the accumulator. Figure 4.6 shows the operation of the LDA 2500H instruction. Memory 3FH | 2500H Accumulator aFH je Figure 4.8 Execution of LDA instructionInstruction Set of 8085 Microprocessor + 71 Direct addressing Number of bytes 3 Number of machine cycles 4 Number of T states 13T Flag No flag effected Encoding 00111010 5. LDAX B/D Register pair: Load accumulator indirect The contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered. For example, if the register pair DE contains 2500H, then to execute the instruction LDAX D, microprocessor transfer the contents of the memory location pointed by DE (i.e., 2500H) to the accumulator as shown in Figure 4.7. D onE 25H | OOH desea Memory 3FH | 2500H + ‘Accumulator 3FH | LDAXD. Figure 4.7 Execution of LDAX instruction, Here it is to be noted that the HL register pair cannot be the operand in LDAX instruction. This is because MOV A, M and LDAX H will exactly be the same. ‘Addressing mode Register indirect addressing Number of bytes 1 Number of machine cycles 2 Number of T states 77 Flag No flag effected Encoding 2AH (LDAX B), 1AH (LDAX D) 2 . STA 16-bit address: Store accumulator direct The contents of the accumulator are copied into the memory location specified by the 16-bit address given in the instruction. This is a three-byte instruction, the second byte Specifies the low-order address and the third-byte specifies the high-order address.72_+ Microprocessor 8085 and Its Interfacing ' For example, to execute the instruction STA 2500H, microprocessor will store contents ef zccumulator in the memory location 2500H as shown in Figure 4g "* Memory (——|_3FH_| 2500H Accumulator 3FH ‘STA 2500H Figure 4.8 Execution of STA instruction. ‘Addressing mode Direct addressing Number of bytes 3 Number of machine cycles 4 Number of T states BT Flag No flag effected 00110010 Encoding 7. STAX B/D Register pair: Store accumulator indirect The contents of the accumulator are copied into the memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered, For example, if the DE register pair contains 2500H, then to execute the STAX D instruction microprocessor will transfer the contents of accumulator to the memory location 2500H (i.e. specified in DE) as shown in Figure 4.9. It is to be noted that the HL register pair cannot be the operand in STAX. De 25H | OOH Memory *| 3FH | 2500H + Accumulator 3FH ‘STAXD Figure 4.9 Execution of STAX D. adInstruction Set ot 8085 Microprocessor + 73 dressing mode Register indirect addressing Number of bytes 1 Number of machine cycles 2 Number of T states T Flag No flag effected Encoding __ ___ 02H (STAX B), 12H (STAX D) 8. LHLD 16-bit address: Load H and L registers direct The instruction copies the contents of the memory location pointed out by the 16-bit address into register Land copies the contents of the next memory location into register H, The contents of source memory locations are not altered. This is a three-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address, Figure 4.10 shows the execution of the instruction LHLD 2S00H. Hie Memory 29H | FH F3H_ | 2500H 29H | 2501H LHLD 2500H Figure 4.10 Execution of LHLD 2500H. ___ Addressing mode Direct addressing 3 Number of bytes Number of machine cycles 5 Number of T states 16T Flag No flag effected Encoding 00101010 9. SHLD 16-bit address: Store H and L registers direct The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a three-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address. Figure 4.11 shows the execution of the SHLD 2S00H instruction.i rr, | 74 + Microprocessor 8085 and Its Interfacing H L Memory 29H | F3H T+] FsH_| 2500H a re om) ‘SHLD 2500H Figure 4.11 Execution of SHLD 2500H. inert addressing ‘Addressing mode Direct addressing Number of bytes 3 Number of machine cycles a Number of T states 1 Flag No flag effected Encoding 00100010 10. XCHG: Exchange H and L with D and E The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E. To execute this instruction microprocessor first transfer the content of the L register to the temporary register Z and then the content of E register to L and then content of Z register woE register. Similarly, the content of H is first transfer to W register, content of D is transferred to H and then W is transferred to D register. In short, we can say that HL is the first transferred to temporary register WZ, then DE to HL and finally WZ to HL Example XCHG ‘Addressing mode Implicit Number of bytes 1 Number of machine cycles 1 Number of T states 4T Flag No flag effected Encoding gt tel oa! op IOI) EXAMPLE 4.5 Write the program of Example 4.4 using the SHLD and XCHG instructions Solution Here first the contents of DE register pair is transferred using exchange instructioa to HL register pair. Then HL pair is stored in memory using SHLD instruction. XCHG SHLD 9000H Note that the program in Example 4.4 is 8-bytes long, whereas, this program is only +by'** long. ddLLL Instruction Set of 8085 Microprocessor + 75 EXAMPLE 4.6 Write a program to transfer two 16-bit data from the memory location 700082001 and 2002&2003 to DE and HL register pairs respectively. Solution LHLD 2000H XCHG LHLD 2002H Here the first instruction loads the data from memory location 2000H to L register and data from memory 2001H to H register. The second instruction exchange the data of HL register pair and DE register pair (i.e. data from 2000&2001 is transferred to DE register pair). The third instruction load the data from memory location 2002H &2003H to HL register pair. 11. SPHL: Copy H and L registers to the stack pointer. The instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered, Example SPHL ‘Addressing mode Implicit Number of bytes 1 Number of machine cycles 1 Number of T states oT Flag No flag effected 11111001 Encoding 12, PCHL: Copy H and L registers to the program counter. 1 The instruction loads the contents of the H and L registers into the program counter register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered. Example PCHL Addressing mode Implicit Number of bytes 1 Number of machine cycles 1 Number of T states 6T Flag No flag effected 11111001 Encoding 13. XTHL: Exchange H and L with top of stack. The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack Pointer register are not altered. Figure 4.12 shows the execution of XTHL instruction. In this figure, the numbers written in circles show the execution sequence of this instruction._ 76. 6 Microprocessor 8085 and Its interfacing 45H DEH Top of stack Top of stack HL Stack mamory ae O\ \eenee 29H | FoH [pen [45x 45H | 2500H ig Pp F3H_ | 2500H 29H _| 2501H De | Ae w{ 29H | F3H |Z OH XxH ® xxH XH Before XTHL © After XTHL Figure 4.12 Execution of XTHL. ‘Addressing mode Implicit Number of bytes 1 Number of machine cycles 5 Number of T states 16T Flag No flag effected Encoding 11100011 14. PUSH Register pair/PSW: Push registers pair or Program Status Word (PSW) onto stack The contents of the register pair designated in the operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the high order register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location. The PSW (A:F) is a combination of the accumulator (as higher byte) and flag register (as lower byte). PUSH B or PUSH PSW Example ‘Addressing mode Register indirect Number of bytes 1 Number of machine cycles 3 Number of T states 127 Flag No flag effected Encoding 11 R,R,0101 EXAMPLE 4.7 Write the sequence of execution of the instruction PUSH D. Solution Microprocessor operates this instruction as follows: 1. Decrement SP 2. Copy the contents of register D to the memory location pointed to by SP 3. Decrement SP 4. Copy the contents of register E to the memory location pointed to by SP.yy 15. POP Register pair/PSW: Pop off stack to register pair or Program Status Word (psw). The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented Instruction Set of 8085 Microprocessor + 7 by 1. Example POP H or POP PSW Register indirect 1 ‘Addressing mode ‘Number of bytes Number of machine cycles 3 Number of T states 10T Flag No flag effected 11 R,R,0001 Encoding EXAMPLE 4.8 Write the sequence of execution of the instruction POP D Solution Microprocessor operates this instruction as follows: 1. Copy the contents of the memory location pointed to by the SP to register E 2. Increment SP 3. Copy the contents of the memory location pointed to by the SP to register D 4. Increment SP. EXAMPLE 4.9 Write a program to clear the flag register. Solution As we cannot move or retrieve anything to/from flag register with the help of MOV instruction. The only instructions which use the flag are PUSH and POP. So, to clear the flag, we will use these two instructions. LXI SP, XXXXH_: Initialize SP LXI B, OOOOH: Clear BC register pair PUSH B : Push BC register pair on stack top POP PSW : POP BC register pair in PSW The POP PSW instruction will load the contents (0000H) of BC register pair to the accumulator and flag register. 16. OUT 8-bit port address: Output data from accumulator to a port with 8-bit address The contents of the accumulator are copied into the YO port specified by the operand. The output port address may be any number from 00H to FFH. The input/output ports can only communicate with accumulator and hence, accumulator is implied in both IN and OUT instructions.ee eee 78 + Microprocessor 8085 and Its Interfacing Example QUT OFH Direct addressing ‘Addressing mode “Number of bytes 3 Number of machine cycles 3 Number of T states 10T No flag effected 11 011011 Flag ‘Encoding 17, IN &bit port address: Input data to accumulator from a port with 8-bit address The contents of the input port designated in the operand are read and loaded into the accumulator. The input port address may be any number from 00H to FFH. Direct addressing. ‘Addressing mode Number of bytes 2 Number of machine cycles 3 Number of T states 10T Flag No flag effected Encoding 11010011 4.5.1 Arithmetic Instructions processor 8085 can perform 8-bit binary and decimal 8085 has 14 arithmetic instructions. Microj addition. It can perform 16-bit binary addition. There are instructions by which 8-bit subtraction can be performed. Microprocessor 8085 cannot perform 16-bit BCD addition and 8-bit BCD subtraction by single instruction. It can perform 8-bit and 16-bit increment and decrement operations. The various instructions of this group are discussed in this section. 1. ADDR M: Add register or memory to accumulator The contents of the operand (register or memory) are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example ADD H or ADD M ADD R Addressing mode Register addressing Number of bytes 1 Number of machine cycles 1 Number of T states 4 Flag All flags effected Encoding 10000SssPe Instruction Set of 8085 Microprocessor + 79 ADD M Re ge Addressing mode __ Indirect addressing Number of bytes 1 Number of machine cycles 2 Number of T states 7T Flag All flags effected Encoding 10000110 :_--.. 1) i eemeea OE EXAMPLE 4.10 Write a program to load register A with 50H and register B with 10H and add the two numbers neglecting the carry. Store the result in register C. Solution To implement this program load the first data in register A and the second data in register B using MVI instruction. Now add the two data using the ADD instruction and store the result in register C using MOV Instruction, MVI A, 50H MVI B, 10H ADD B MOV C, A EXAMPLE 4.11 Write a program to add the content of memory locations 9510 and 9511. Neglect carry. Store the result in memory location 9512. Solution The data from the memory to accumulator or accumulator to memory can be transferred using LDA and STA instructions. LDA will load data into the accumulator from memory address. STA will store the contents of accumulator at the specified memory address. LDA 9510H_— : Load the content of 9510 in A register MOV B, A: Transfer the content of A to B register LDA 9511H__: Load the content of 9511 in A register ADD B : Add the two data (A + B) STA 9512H : Store the result from A to 9512 memory location 2, ADCR M: Add register to accumulator with carry The contents of the operand (register or memory) and the carry flag are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example ADC L or ADC M ADC R Addressing mode Register addre Number of bytes 1 Number of machine cycles 1 Number of T states 4 Flag Alll flags effected Encoding 10001SSSya 80 + Microprocessor 8085 and Its Interfacing ADC M ‘Addressing mode Indirect addressing 1 Number of bytes Number of machine cycles 2 Number of T states Te. Flag All flags effected Encoding 10001110 EXAMPLE 4.12 Write a program to add two 16-bit numbers 2030H and 40S0H using ADD and ADC instructions, neglecting the carry. Store the result in H and L register. Solution f we have to use the ADD and ADC instructions then we have to transfer the numbers to registers and then apply the addition instructions on registers. LXI B, 2030H_ : Load 20H in B and 30H in C LXI D, 4050H : Load 40H in D and 50H in E MOV A, E ; Transfer E to A ADD C : Add C to A MOVL,A : Transfer A to L MOV A, D : Transfer D to A ADC B Add B to A with carry MOV H, A Transfer H to A 3. ADI 8-bit data: Add immediate to accumulator The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition. Example ADI FSH Addressing mode Immediate addressing Number of bytes 2, Number of machine cycles 2 Number of T states IT Flag All flags effected Encoding 11000110 EXAMPLE 4.13 Write a program to load register A with 50H and register B with 10H, and add the two using the ADI instruction neglecting the carry. Store the result in register C. Solution MVI A, 50H ADI 10H MOV C, A 4. ACI 8-bit data: Add immediate to accumulator with carry a ri a ee Eis the carry flag are added to the contents of the accumulator and the result is stored in the accumulator. All flags ere wachin of the addition. 188 are modified to reflect the resultwn ee Example ACI FSH ‘Addressing mode “Number of bytes Number of machine cycles Number of T states Instruction Set of 8085 Microprocessor + 81 Alll flags effected Fi Enooding 11001110 EXAMPLE 4.14 Write a program to add two 16-bit numbers, F378H and 45D0H neglecting the carry. Save the result in HL register pair. Solution Unlike Example 4.12, we can directly add the two numbers usin addressing mode. The steps of this program is shown in Figure 4.13. MVI A, 78H ADI DOH MOV LA MVI A.F3H ACI 45H MOV H, A g the immediate Figure 4.13 Addition of two numbers. 5. DAD Register pair/SP: Add register pair to H and L registers The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are effected. Example DAD D Number of bytes 1 Number of machine cycles 3 Number of T states 10T Flag Only carry flag effected Encoding OR,R,100182_ + Microprocessor 8085 and tts Interfacing EXAMPLE 4.15 Rewrite the program of Example 4.14 using DAD instruction, Solution a. LXI_H, F378H LXI D,4SD0H DAD 6. DAA: Decimal adjust accumulator The contents of the accumulator are changed from a binary value to two 4-bits binary coded decimal (BCD) digits. This is the only instruction that uses the AC flag to perform the binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the operation. If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four-bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the carry flag is set, the instruction adds 6 to the high-order four-bits. : The DAA instruction can convert the binary sum of two BCD numbers in BCD but it cannot convert the binary sum of two binary numbers to BCD. The DAA instruction can only be used after 8-bit addition instruction. Example DAA ‘Addressing mode Implicit addressing Number of bytes i Number of machine cycles 1 Number of T states 4T Flag All flags effected Encoding 00100111 EXAMPLE 4.16 Write a program to add two BCD numbers 45 and 95, neglecting the carry. Solution MVI A, 45 ADI 95 DAA 7. SUBR M: Subtract register or memory from accumulator The contents of the operand (register or memory) are subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction.————e Example SUB D or SUB M SUB R ~ Addressing mode Number of bytes. Number of machine cycles Number of T states Flag Encoding SUB M "Addressing mode Number of bytes Number of machine cycles Number of T states EXAMPLE 4.17 Write a program to subtra Instruction Sot of 8085 Microprocessor + 83 Register addressing I 1 i All flags effected 10010SSS Register indirect addressing _ 1 2 = All flags effected 10010110 ct the contents of memory location 2050H from the contents of memory location 20S1H. Neglect the borrow, if any. Send the result to the output port F3H Solution LXI H, 2050H MOV B, M LDA 2051H SUB B OUT F3H 8. SBB R M: Subtract source and borrow from accumulator The contents of the operand (register or memory) and the borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction. SBB D or SBB M Example SBBR essing mode Number of bytes Number of machine cycles 1 Number of T states at Flag All flags effected Encoding 10011SSS.a, 84 + Microprocessor 8085 and Its Interfacing SBB M ‘Addressing mode Register indirect addressing Number of bytes i Number of machine cycles abe a of T states eee ee = 10011110 9. SUI 8-bit data: Subtract immediate from accumulator i i is the accumulator and th The 8-bit data (operand) is subtracted from the contents of ; result is stored ae plas ‘Alll flags are modified to reflect the result of the subtraction. Example SUI FSH ‘Addressing mode Immediate addressing Number of bytes 2 Number of machine cycles a Number of T states Flag All flags effected 11010110 Encoding EXAMPLE 4.18 Write a program to subtract 50H from FOH, neglect borrow, if any. Store the result in register C. Solution MVI A, FOH SUI 10H MOVC,A 10. SBI 8-bit data: Subtract immediate from accumulator with borrow The 8-bit data (operand) and the borrow flag are subtracted from the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction. Example SBI FSH Addressing mode Register addressing Number of bytes 1 Number of machine cycles 2 Number of T states FT Flag Alll flags effected Encoding 11011110 11. INR R M: Increment register or memory by 1 The contents of the designated register or memory are incremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specifiedeee! Instruction Set of 8085 Microprocessor + 85 a cone oe Its to be noted that the carry flag is not modified increment and addition by 1 oo instructions, and this is the basic difference in INR A the content of — 3 ‘or example, if accumulator contains FFH then after IINR the ADI 01H is cas ae will be 0 and carry flag will be unmodified. If instead cya aaiiee tuted then the content of accumulator will be again OOH but Example INR C or INRM INRR ‘Addressing mode i Register addressi Number of bytes = 7 a Number of machine cycles 1 Number of T states aT Flag eB All flags effected except car Encoding ooDDD100 ane INR M ‘Addressing mode Register indirect addressing Number of bytes 1 Number of machine cycles 3 Number of T states 10T Flag ‘All flags effected except carry Encoding 00110100 pair by 1 ed register pair is increment flag will remain unaffected. he memory pointer HL, especially when 12. INX R,: Increment registe The contents of the designat in the same place. The carry frequently used to increase t locations are consecutive. Example INX D pee ee ‘Addressing mode Register addressing 1 ed by 1 and the result is stored The INX H instruction is very fhe memory Number of bytes Number of machine cycles 1 Number of T states 6T None of the flag effected Fla o OOR,R,0011 Encoding =e pair is 20FFH and that of DE pair is FFFFH. What If the content of the HL EXAMPLE 4.19 will be the contents of these registers after the following program? INX H INX D e contents of HL pair will becomes 2100 H and Solution After the execution of INX H th the contents of DE will be 0000 H. —————86 + Microprocessor 8085 and Its Interfacing 13. DCRR M: Decrement register or memory by 1 ‘The contents of the designated register or memory are decremented by 1 and the is stored in the same place. If the operand is a memory location, its location is spe, by the contents of the HL registers. Example DCR B or DCR M Fesult Cifieg DCRR ‘Addressing mode Register addressing Number of bytes 1 Number of machine cycles 1 Number of T states 4T Flag All flags effected except carry 0ODDD101 Encoding DCR M ‘Addressing mode Register indirect addressing Number of bytes Number of machine cycles 3 Number of T states 10T Flag All flags effected except carry Encoding 00110101 14, DCX R,: Decrement registers pair by 1 ‘The contents of the designated register pair are decremented by 1 and the result is stored in the same place. Example DCX H Addressing mode Register addressing Number of bytes 1 Number of machine cycles 1 Number of T states oT Flag None of the flag effected Encoding : 00R,R,101 pete Fe Wale Program to subtract the 16-bit data stored at memory location : om another 16-bit data stored at 2003:2002H. Neglect i result in memory location 2005:2004H, Seles: Bono df ang Save Ie Solution As we do not have 16-bit subtraction instruction, so, we have to perform this 16-bit subtraction with the help of 8-bit subtraction instructions, First we should initialize HL to a memory location, and then by using MOV R, M we will tr: Ct ansfer the data ssor registers from various memory locations. ata to microprnessyy when MOV E, M instruction is executed HL = 2000, so, the content of 2000 are transferred to register. Then INX H increases HL to 2001, instruction MOV D, M transfer the content of 2001 to D register and so on. Instruction Set of 8085 Microprocessor + 87 Program LXI H, 2000H : Initialize HL MOV E,M_— : Move content of M to E : INX H : Increment HL by I to point next memory location MOV D,M__: Move content of M to D INX H Increment HL by 1 MOV C,M = Move content of M to C INX H : Increment HL by 1 to point next memory location MOV B,M —: Move content of M to B INX H : Increment HL by 1 to point next memory location MOV A, E — : Move content of E to A SUB C : Subtract C from A MOV M, A: Save the result to M : Increment HL by 1 to point next memory location INX H MOV A,D __: Move content of D to A SBB B : Subtract B from A with borrow MOV M, A ___: Save the result to M The same program may be written as: LHLD 2000H XCHG : Data from 2001:2000H transferred to DE LHLD 2002H : Data from 2003:2002H transferred to HL MOV A, L SUB E : Lower byte is subtracted MOV L, A MOV A, H SBB D MOV H, A SHLD 2004H_: Result is saved in memory Upper byte is subtracted with borrow 4.5.2 Logical Instructions Microprocessor 8085 can perform six logical operations. These are NOT, OR, AND, EXOR, Compare and Rotate operations. Except compare operations all the other five operations are performed on bit by bit basis and hence these five operations are also called as bit manipulation operations. The various instructions in this group are discussed in this section. 1, CMP R M: Compare register or memory with accumulator The contents of the operand (register or memory) are compared with the contents of the accumulator, Both contents are preserved. The result of the comparison is shown by setting the flags of the PSW as follows:OY 88. Microprocessor 8085 and Its Interfacing if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset Example CMP C or CMP M CMP R moe ae Da Mg eee —TRtiessing mode “Restor atresia 1 Number of bytes Number of machine cycles 1 Number of T states ay Flag All flags effected 10111SSS Encoding CMP M Register indirect addressing ‘Addressing mode Number of bytes 1 Number of machine cycles 2 Number of T states TE Flag All flags effected Encoding 10111110 2. CPI 8-bit data: Compare immediate with accumulator The second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows: if (A) < data: carry flag is set if (A) = data: zero flag is set if (A) > data: carry and zero flags are reset Example CPI 98H ‘Addressing mode Immediate addressing Number of bytes Number of machine cycles 2 Number of T states 77 Flag é All flags effected Encoding 11111110 3. ANA R/M: Logical AND register or memory with accumulator The contents of the accumulator are logically ANDed with the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is # memory location, its address is specified by the contents of HL registers. S, Z, P modified to reflect the result of the operation. CY is reset. AC is set. 27. Example ANA C or ANAM ANA R ~~ Addressing mode 4. ANI 8-bit dat operation. CY is reset. AC is set Example ANI 69H Instruction Set of 8085 Microprocessor + 89 : Register addressing Number of bytes 1 Number of machine cycles 1 Number of T states 4T Flag S, Z, P are modified . C=0,AC=1 Encoding ae 10100SSS ANA M ; sing mode ier indirect addressing _ Number of bytes 1 Number of machine cycles 2 Number of T states 77 Flag S, Z, P are modified C=0,AC=1 _Encoding 10100110 : Logical AND immediate with accumulator The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the result is placed in the accumulator. $, Z, P are modified to reflect the result of the Addressing mode Immediate addressing Number of bytes 2 Number of machine cycles 2 Number of T states 7T Flag S, Z, P are modified 0, AC =1 Encoding 10100110 xclusive OR register or memory with accumulator The contents of the (register or memory), cumulator are Exclusive ORed with the contents of the operand ind the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. $, Z, P are modified to reflect the result of the operation. CY and AC are reset.90 + Microprocessor 8085 and Its Intortacing Example XRA B or XRA M XRAR ie s, Z, P are modified a c=0,AC=1 _101018SS Encoding _ eo CORAM oe » ‘Addressing mode Register indirect addressing Number of byt 1 Number of machine cycles 2 Number of T states 17 Flag S, Z, P are modified C=0,AC=1 Encoding 10101110 6. XRI 8-bit data: Exclusive OR immediate with accumulator Exclusive ORed with the 8-bit data (operand) and The contents of the accumulator are the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset Example XRI FEH ‘Addressing mode Immediate addressing 2 Number of bytes Number of machine cycles 2 Number of T states 77 Flag S, Z, P are modified Cc=0,AC=1 Encoding 11101110 7. ORA R M: Logical OR register or memory with accumulator The contents of the accumulator are logically ORed with the contents of the (register or memory), and the result is placed in the accumulator. If the operand is # memory location, its address is specified by the contents of HL registers. S, Z, P a modified to reflect the result of the operation. CY and AC are reset. operand . ddee ‘Example ORA B or ORAM ORA A ‘Addressing mode Number of bytes Number of machine cycles Number of T states Flag Encoding ORAM ‘Addressing mode Number of bytes Number of machine cycles Number of T states Flag Encoding Instruction Set of 8085 Microprocessor + 91 Register addressing 1 1 4T S, Z, P are modified C=0,AC=1 10110SSS Register indirect addressing 1 2 om S, Z, P are modified C=0,AC=1 10110110 8. ORI 8-bit data: Logical OR immediate with accumulator The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example ORI 86H ‘Addressing mode Number of bytes 9. CMA: Complement accumulator Addressing mode Encoding Immediate addressing Number of machine cycles 2 Number of T states aT: Flag S, Z, P are modified C=0,AC=1 Encoding 11110110 The contents of the accumulator are complemented. No flags are affected. Implicit addressing Number of bytes 1 Number of machine cycles 1 Number of T states 4T Flag No flags are modified 00101111> 4 the number stored at memory location 20004, ry location 20011. 92 + Microprocessor 8085 and Its Interfac EXAMPLE 4.21 Find the I’s complement © and store the complemented number at memo Solution LDA 2000H —: Get the number CMA : Complement number STA 2001H — : Store the result he number stored at memory location 2000 complement of # ‘memory location 2001H. EXAMPLE 4.22 Find the 2’s © and store the complemented number at Solution LDA 2000H —: Get the number CMA : Complement the number ADI, 01H: Add one in the number STA 2001H _ : Store the result 10, RLC: Rotate accumulator left ‘cach binary bit of the accumulator is rotated Te the position of Dy as well as in the carry flag. CY is S, Z, P, AC are not affected. The rotation of the content ft by one position. Bit D7 is placed in ‘modified according to bit D;. of accumulator is shown in Figure 4.14. —_e ooo Le Te TO Tok Figure 4.14 Picoral representation of RLC. Example RLC ‘Addressing mode Implicit addressing Number of bytes 1 Number of machine cycles 1 Number of T states 4 Only carry flag is modified Flag EXAMPLE 4.23 Write an assembly program to multiply a 0SH_ by 8 using shift instructions and send the result to the output port 29H. — If we shift a number towards left by 1 position then the number is multiplied by ase of that number system. For example, if the binary number 101 is shifted 1-bit position towards left, i¢., (1010), = (10)1o, then it will be multiplied by 2 (base of binary number). gdMVI A, OSH —; OSH = 00000101 RLC ; After first shift 00001010 = (10), RIC 3 After second shift 00010100 = (20)i9 RLC 3 After third shift 00101000 = (40),y oUuT 29H 11. RRC: Rotate accumulator right (Figure 4.15) Each binary bit of the accumulator is rotated right by one position. Bit Dy is placed in the position of D7 as well as in the carry flag. CY is modified according to bit Do. S, Z, P, AC are not affec cy ro, [% [0 [.[0,] 0, [0] 0, Figure 4.15 Pictorial representation of RRC. Example RRC __ Addressing mode Number of bytes Number of machine cycles 1 Number of T states 4 Flag Only carry flag is modified Encoding _ 00001111 EXAMPLE 4.24 Write a program to shift an eight-bit data four bits right. Assume data is in register B Solution MOV A, B RRC RRC RRC RRC MOV C,B 12. RAL: Rotate accumulator left through carry (Figure 4.16) Each binary bit of the accumulator is rotated left by one position through the carry flag. Bit D, is placed in the carry flag, and the Carry flag is placed in the least significant position Dy. CY is modified according to bit Dy. S, Z, P, AC are not affected, +[cy D, [Ds] Os] | | 22 [ 0, | % fH Figure 4.16 Pictorial representation of RAL.Le 94 © Ao Meroprocessor 8086 and Its Interfacing : Byample RAL Addres Number of bytes Number of machine cycles i N er 0 states: i lumber of T states Only carry flag. is modified OOOLOLLL ing mode Implicit addressing aa 1 13, RAR: Rotate accumulator right through carry (Figure 4.17) Each binary bit of the accumulator is rotated right Py one position through the cary flag, Bit Dp is placed in the carry flag, and the carry fg a as in the mogt significant position Dy. CY is ‘modified according to bit Do. S, Z, P, AC a affected. Example Number of bytes Number of machine cycles 1 Number of T states 4T 0) Flag Only carry flag is modified Encoding Kt _O00LLILL ata, 1-bit right. Assume that data is in EXAMPLE 4.25 Write a program to shift a 16-bit BC register pair. Solution MOV A, B RAR MOV B, A MOV A, C RAR MOV C,A 14, CMC: Complement carry The Carry flag is complemented. No other flags are affected Example CMC Implicit addressing 1 1 4T Only carry flag is modified 00111111 . Number of byt Number of machine cycles Number of T states Flag Encodingee 15, STC: Set Carry The carry flag is set to 1. No other flags are affected. Instruction Set of 8085 Microprocessor + 95 Example STC Addressing mode Implicit addressing Number of bytes 1 Number of machine cycles 1 Number of T states 4T Flag Only carry flag is modified Encoding 00110111 EXAMPLE 4.26 Write a program to reset the carry flag. Solution First we have to confirm that the carry flag is set and then we will compliment it. sTC cuc EXAMPLE 4.27 Pack the two unpacked BCD numbers stored in memory locations 2000H and 2001H and store result in memory location 2003H. Assume the most significant digit is stored at 2000H and least significant digit is stored at 2001H. Solution If there are two BCD digits in a number (e.g. 48) and they are stored in an 8-bit register, then that BCD number is called a packed BCD number. If the same two digit BCD number is stored as 04 and 08 in two 8-bit register then this number is called as unpacked BCD number. In this program, first we load the most significant digit (for example 04) in accumulator and then rotate it four times towards left to make it 40. Then add the least significant digit (ie. 08) to 40 to make it 48. LXI H 2000H_— : Initialize HL pair as memory pointer MOV A.M: Get the most significant BCD digit RLC RLC RLC RLC Adjust the position of the second digit (09 is changed to 90) ANI FOH : Make least significant BCD digit zero MOV C,A store the partial result INX H Increment the memory pointer MOV A, M Get the lower BCD digit ADD C Add lower BCD digit INX H Increment the memory pointer MOV M, A: Store the result EXAMPLE 4.28 A packed BCD number is stored in memory location 2000H. Unpack the BCD number and store the two digits in memory locations 2001H and 2002H such that memory location 2001H will have lower BCD digit.96 + Microprocessor 8085 and Its interfacing Solution LXI H 2000H — : Initialize HL pair as memory pointer MOV A, M Get the packed BCD number MOV B.A: Save the number in B register ANI FOH Mask lower nibble RRC RRC RRC 2 RRC + Adjust higher BCD digit as a lower digit INX H z INX H + Increment HL twice to point to 2002H MOV M, A __; Store the partial result MOV A,B: Get the original BCD number ANI OFH + Mask higher nibble DCX H + Decrement HL by 1 to point to 2001H MOV M, A: Store the result 4.5.3 Branching Instructions ‘These instructions are also called as control transfer instruction because with these instructions the control of operation is transferred from one location to another location. This section discussed the instructions by whicl 1. another location within the same program (JUMP), 2. another program called sub-routine (CALL) 3, from sub-routine program to main program (RET) This control transfer may be unconditional as well as conditional. The conditional control transfer instruction uses the sign, zero, parity and carry flag bits to put up the conditions. On the basis of setting or resetting of these four flag bits we can have eight different data conditions. ‘h the control is transferred to 1. JMP 16-bit address: Jump unconditionally The program sequence is transfered to the memory location specified by the 16-bit address given in the operand. Example JMP 2034H or JMP XYZ Addressing mode Immediate addressing Number of bytes 3 Number of machine cycles 3 Number of T states 10T Flag i No flag is modified Encoding 11000011 "= Instruction Set of 8085 Microprocessor + 97 2, Jump conditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. All these instructions have same addressing modes, same number of bytes, and same flag conditions as that of unconditional JMP. But the number of machine cycles will be different when the condition is true (3 machine cycles and 10T states) and when the condition is not true (2 machine cycles and 7 T states). JC 16-bit address Jump on carry CY = 1 DAH INC 16-bit address Jump on no carry CY = 0 D2H JP 16-bit address Jump on positive § = 0 CAH JM 16-bit address Jump on minus § = 1 QH JZ 16-bit address Jump on zero Z = 1 F2H INZ 16-bit address Jump on no zero Z = 0 FAH IPE 16-bit address Jump on parity even P = 1 EAH IPO 16-bit address Jump on parity odd P = 0 E2H 3. CALL 16-bit address: Unconditional sub-routine call The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack. Figure 4.18 shows the sequence of operation for the CALL instructions. 20004 . 2001 . 2002H CALL 2500H Top of stack 2003H . Stack memory 2006H : mI @ Pros | [SPI }-* 20H [SP+1] XH XXH 2500H See 2501H ee | enn : service : routine «| fer, Figure 4.18 Sequence of operations in CALL.SS 98 + Mictoprocessor 8085 and Its interlacing CALL 2034H or CALL XYZ Example ‘Addressing Immediate addressing Number of bytes 3 Number of machine cycles 5 Number of T states 18T Flag No flag is modified Encoding 11001101 4. Call conditionally The program sequence is transferred to the memory location specified by the 16. address given in the operand based on the specified flag of the PSW as described below, Before the transfer, the address of the next instruction after the call (the contents of the program counter) is pushed onto the stack. Alll these instructions have same addressing Prodes, same number of bytes, and same flag conditions as that of unconditional JMP But the number of machine cycles will be different when the condition is true (5 machine cycles and 18T states), and when the condition is not true (2 machine cycles and 9T states). Example CZ 2034H or CZ XYZ CC 16-bit address Call on carry CY = 1 DCH CNC 16-bit address Call on no carry CY = 0 D4H CP 16-bit address Call on positive S = 0 CCH CM 16-bit address Call on minus S = 1 C4H CZ 16-bit address Call on zero Z = 1 F4H CNZ 16-bit address Call on no zero Z = 0 FCH CPE 16-bit address Call on parity even P = 1 ECH CPO 16-bit address Call on parity odd P = 0 E4H 5, RET: Return from sub-routine unconditionally ¢ calling program. The m sequence is transferred from the sub-routine to th ‘om the top of the stack are copied into the program counter, and program The prograt 19 shows the sequence of operations in two bytes fr execution begins at the new address, Figure 4 Return Instruction Example: RET Number of bytes Number of machine cycles Number of T states Flag 3 10T No flag is modified 11001001Instruction Set of 8085 Microprocessor + 99 2000H . 2001H . 2002H CALL oa LL 2500H Top of stack 2006H . ‘Stack memory © + 03H | [SP] ~ 20H | [SPI] XXH XXH 2500H _ 2501H : interrupt : ence : routine ° RET Figure 4.19 Sequence of operations in return instruction 6. Return from subroutine conditionally The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. All these instructions have same addressing modes, same number of bytes, and same flag conditions as that of unconditional JMP. But the number of machine cycles will be different when the condition is true (3 machine cycles and 10T states) and when the condition is not true (1 machine cycle and 6T states). Example RZ RC none Return on carry CY = 1 D8H RNC none Return on no carry CY = 0 DOH RP none Return on positive $ = 0 8H RM none Return on minus S = 1 COH RZ none Return on zero Z = 1 FOH RNZ none Return on no zero Z = 0 FSH RPE none Return on parity even P = 1 E0H RPO none Return on parity odd P = 0 ESH w PCHL: Load program counter with HL contents The contents of registers H and L are copied into the program counter. The contents of H are placed as the high-order byte and the contents of L as the low-order byte. This instruction is equal to a one-byte unconditional jump instruction. A program sequence can be changed to any location by simply loading the H and L registers with address and by using this instruction.100 + Microprocessor 8085 and its Interfacing ’ Example PCHL a ra Number of bytes 1 Number of machine cycles 1 Number of T states 6T Flag No flag is modified Encoding 11101001 8. RST 0-7: Restart The RST instruction is eq! locations depending upon t with interrupts and inserte software instructions in a locations. The addresses are: ivalent to a one-byte call instruction to one of eight memo, ‘he number. The instructions are generally used in conjunctic, d using external hardware. However, these can be used a, program to transfer program execution to one of the eighy Instruction restart address RST 0 0000H RST 1 0008H RST 2 0010H RST 3 0018H RST 4 0020H RST 5 0028H RST 6 0030H RST 7 0038H The 8085 has four additional interrupts and these interrupts generate RST instructions internally and, thus, do not require any external hardware. These instructions and their Restart addresses are: Interrupt restart address TRAP 0024H RST 5.5 002CH RST 6.5 00341 RST 7.5 003CH Addressing mode Implicit addressing Number of bytes i Number of machine cycles 3 Number of T states ar Flag No flag is modifi ' g is modified ac ee oe AASInstruction Set of 8065 Microprocessor + 101 ' 45.4 Machine Control Instructions ‘this section of instruction controls the operation of the microprocessor. 1. NOP: No operation No operation is performed. The instruction is fetched and decoded. However no operation is executed. This instruction is used for small (4T) delay. Example NOP Number of bytes 1 ' Number of machine cycles 1 4 Number of T states No flag is modified 00000000 2, HLT: Halt and enter wait state The CPU finishes executing the current instruction and halts any further execution. The address and data bus is placed into high impedance state. The contents of the registers are not modified during this state, An interrupt or reset is necessary to exit from the halt state. Example HLT __ Addressing mode None Number of bytes 1 Number of machine cycles 2 Number of T states 5 or more T Flag No flag is modified 01110110 Encoding _ 3. DI: Disable interrupts The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. This instruction is used when the users do not want that system must not be interrupted. Example Di None 1 Number of machine cycles 1 47 Number of T states No flag is modified 11110011102 - Neroprocessor 8085 and Its Intertacing 4. El: a nable interrupts he interrupt enable flip-flop is set and interrupts are enabled, No flags are aff Atte ; mi a system reset or the acknowledgement of an interrupt, the interrupt Snaatt ip-flop is reset, thus, disabling the interrupts. This instruction is necessary to Pie able the interrupts (except TRAP) Example ¥1 Addressing mode : None 3 Number of bytes 1 Number of machine cycles = Number of T states 4 Flag No flag is modified Encoding ne peat bas togmmna ARON oni 5. RIM: Read interrupt mask This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 ang tod serial data input bit, The instruction loads eight bits in the accumulator with the interpretations as shown in Figure 4.20. D, De Ds Dy Dy Oz Di Do (Soli Lie Tis Te [7s 165156 T ‘Serial input data bit a a Te interrupt masked if bit = 1 Interrupts pending if bit = Interrupt enable flip-lop is set if bit Figure 4.20 Format of RIM instruction ‘There are many instructions in the instruction set of 8085, like MOV, LXI, STA and SHLD. etc, for parallel data communication but RIM and SIM are the only two instructions by which microprocessor performs its serial communication via its two pins SID (Serial Input Data) and SOD (Serial Output Data). Non : i Number of machine cycles 1 Number of T states 4T Flag No flag is modified “Encoding 2 00100000 Suppose the SID line.of the microprocessor is connected to logic high, i-e., to Vee and if RIM instruction is executed, then the accumulator's MSB bit will be loaded with a Logic 1 and the content of the accumulator will become 1 = 80H Similarly, if the SID line is connected with OV (GND) and RIM instruction is executed: then the accumulator's MSB bit will be loaded with a Logic 0 and the content of the accumulator will become 2 = 00H es oeer > Instruction Set of 8085 Microprocessor + 103 “ Here it should be noted that the Dg ~ Dp bits of the accumulator will always be zero and \ the Dr bit will have a value 0 or 1 depending on whether the SID line is connected to GND I or Vee before the execution of RIM instruction. 6. SIM: Set interrupt mask ‘This is a multipurpose instruction and used to implement the 8085 interrupts 75, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as shown in Figure 4.21 DO O%& 0, & OD, OD, DB Dy ‘SOD | SDE T Xxx R75] MSE | M7.5] M657 M5.5 , Serial output wal Reset R7.5. Masks interrupts D,=1 itbits = 1 Serial data enable Mask set 4 = Enable enable if 0 = Disable D,=1 Figure 4.21 Format of SIM instruction. Addressing mode None Number of bytes 1 Number of machine cycles 1 Number of T states aT Flag No flag is modified Encoding 00110000 EXAMPLE 4.29 Write a program to transmit logic 0 through the SOD line. Solution The serial data is transmitted through the SOD line with the help of SIM instruction. Here we will prepare a control word and load it to accumulator and then give the instruction SIM. The execution of the program is shown in Figure 4.22. For serial communication the Do to Ds bit of the SIM control word will not be cared as these bits are used for Interrupt related operations. The program will be MVIA, 40H SIM SOD pin t For serial communication | ar t[x[x[x[x[x[* DATA SOE ‘Accumulator o}]1}/ofo]o]o}o|o]=40H DATA SOE ‘Accumulator Figure 4.22 Pictorial representation of serial output data.CHAPTER Instruction Timing and Operation of 8085 Microprocessor INTRODUCTION In general, microprocessor performs two operations, viz., instruction fetch operation and instruction execution operation. In 8-bit microprocessor, these operations are performed separately. In pipelined microprocessor, these operations are performed, simultaneously. The instruction cycle, (also called fetch-and-execute cycle and_fetch-decode-execute cycle (FDX), can refer to either the time period during which one instruction iS fetched from memory and executed when a computer receives a machine language instruction; or the sequence of actions that a MPU performs to execute each machine code instruction in a program. The name is quite literal. The instruction, along with any data to be worked on, must be fetched from the main memory and then executed by the MPU. In this chapter, we will discuss fetch and execute cycle, T-state, machine cycle and instruction cycle, basic state diagram, timing diagram of opcode fetch cycle, memory read cycle, memory write cycle, IO read cycle, IO write cycle and idle machine cycle. Instruction cycles of all the 8085 instructions are also part of this chapter. 5.1 INSTRUCTION CYCLE Instruction cycle is defined as the time taken by the processor to execute an instruction. Each processor has different cycles based on different instruction sets. Typically all the process! utilizes the following five stage cycles: 112 ad