Comparative Study Of The

Different Types 74-SERIES

Microcontrollers

‫ صفاء محمد أبوكثير مفتاح‬:‫األسم‬

211101
2 ‫اتصاالت م‬
 74LS Series
74LS series is characterized by its TTL technology, 5-volt operation,
fast switching speeds, and the use of Schottky transistors. It has been
a reliable choice for digital logic applications and is still used in various
scenarios, especially where compatibility with existing systems is a
consideration.
 Bipolar-Transistor Based (TTL Technology)
The 74LS series is based on TTL (Transistor-Transistor Logic)
technology. TTL uses bipolar junction transistors (BJTs) in its design.
Each gate in the 74LS IC typically consists of several transistors,
resistors, and diodes, providing a robust and well-established
technology.
 5-Volt Operation
The 74LS series operates on a 5-volt power supply. This voltage level
is common in many digital systems, especially those designed around
the TTL logic family.
 15nS Switching Speed
The 74LS series is known for its relatively fast switching speeds,
typically around 15 nanoseconds (15nS). This speed makes it suitable
for a variety of digital applications where rapid signal processing is
required.
 8mA Sink Capacity
The 74LS series has a sink capacity of 8mA. This refers to its ability to
sink current (provide a low output) when connected to a load. It
indicates the maximum current that can be drawn from an output
without causing a significant voltage drop.
 Transistor to Transistor Logic (TTL)
 TTL is a type of digital circuit design that uses transistors as the main
building blocks. The 74LS series, being TTL-based, employs bipolar
transistors for its logic gates. The use of Schottky transistors within
TTL helps reduce the stored charge and enhances switching speeds.
 Schottky Transistors for Faster Switching Speeds
Schottky transistors used in the 74LS series play a crucial role in
improving the switching speed of the logic gates. The Schottky diodes
associated with the transistors reduce the propagation delay,
contributing to faster overall performance.
 Default Open Inputs to HIGH in TTL
In TTL logic, when an input is left unconnected (floating), it tends to
default to a HIGH logic level. This is a characteristic behavior of TTL
circuits, including the 74LS series. It simplifies the design by providing
a default state when an input is not actively driven to a specific logic
level.
 Legacy and Common Use
The 74LS series has been widely used in the past and has become
somewhat of a legacy technology. While newer technologies like
CMOS (e.g., 74HC) offer advantages in terms of power efficiency and
noise immunity, the 74LS series is still relevant in certain applications,
and many existing systems may still rely on it.
Here I will be focusing on 74LS138, 74LS139, 74LS244 and 74LS245
1:- Description:

74LS138 3 to 8 Decoder/Demultiplexer

74LS139 2 to 4 Decoder/Demultiplexer

74LS244 Octal Driver Tri-State

74LS245 Octal Bus Transceiver Tri-State

2:- Detailed Component Analisis:

74138: This IC has 16 pins, including three binary inputs (A, B, C), eight outputs (Y0 to
Y7), three enable inputs (G1, G2A, G2B), and two ground pins (VCC and GND). The IC
decodes the binary inputs into one of eight outputs, which are active low. The
enable inputs can be used to disable or enable the outputs, depending on the logic
level. The IC can be used for memory address decoding, data routing, and
demultiplexing applications

74139: This IC has 16 pins, including four binary inputs (A1, B1, A2, B2), eight outputs
(Y1 to Y4, Y5 to Y8), two enable inputs (G1A, G1B), and two ground pins (VCC and
GND). The IC contains two independent decoders, each with two inputs and four
outputs. The outputs are active low, and the enable inputs can be used to disable or
enable the outputs, depending on the logic level. The IC can perform the same
functions as the 74138, but with half the number of inputs and outputs per decoder

74244: This IC has 20 pins, including eight data inputs (A1 to A8), eight data outputs
(Y1 to Y8), two enable inputs (G1, G2), and two ground pins (VCC and GND). The IC is
an octal buffer with noninverted three-state outputs. The outputs can be isolated
from the bus by the enable inputs, depending on the logic level. The IC can be used
for memory address drivers, clock drivers, and bus-oriented transmitters/receivers.

74245: This IC has 24 pins, including two sets of eight data inputs and outputs (A1 to
A8, B1 to B8), two direction control inputs (DIR1, DIR2), two output enable inputs
(G1, G2), and two ground pins (VCC and GND). The IC is a 3-state octal bus
transceiver. The data inputs and outputs can be connected or disconnected from the
bus by the control inputs, depending on the logic level. The IC can be used for
bidirectional data transfer between two buses
SN74LS138

1-of-8 Decoder/
Demultiplexer
The LSTTL / MSI SN74LS138 is a high speed 1-of-8 Decoder /
Demultiplexer. This device is ideally suited for high speed bipolar
memory chip select address decoding. The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just three LS138 http://onsemi.com
devices or to a 1-of-32 decoder using four LS138s and one inverter.
The LS138 is fabricated with the Schottky barrier diode process for LOW
high speed and is completely compatible with all ON Semiconductor POWER
TTL families.
• Demultiplexing Capability SCHOTTKY
• Multiple Input Enable for Easy Expansion
• Typical Power Dissipation of 32 mW
• Active Low Mutually Exclusive Outputs
• Input Clamp Diodes Limit High Speed Termination Effects

GUARANTEED OPERATING RANGES 16

Symbol Parameter Min Typ Max Unit 1

VCC Supply Voltage 4.75 5.0 5.25 V PLASTIC

N SUFFIX
TA Operating Ambient 0 25 70 °C
CASE 648
Temperature Range
IOH Output Current – High – 0.4 mA
IOL Output Current – Low 8.0 mA

16
1

SOIC
D SUFFIX
CASE 751B

ORDERING INFORMATION

Device Package Shipping

SN74LS138N 16 Pin DIP 2000 Units/Box

SN74LS138D 16 Pin 2500/Tape & Reel

 Semiconductor Components Industries, LLC, 1999 1 Publication Order Number:

December, 1999 – Rev. 6 SN74LS138/D
 SN74LS138

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC O0 O1 O2 O3 O4 O5 O6
16 15 14 13 12 11 10 9

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.

1 2 3 4 5 6 7 8
A0 A1 A2 E1 E2 E3 O7 GND

LOADING (Note a)
PIN NAMES HIGH LOW
A0 – A2 Address Inputs 0.5 U.L. 0.25 U.L.
E1, E2 Enable (Active LOW) Inputs 0.5 U.L. 0.25 U.L.
E3 Enable (Active HIGH) Input 0.5 U.L. 0.25 U.L.
O0 – O7 Active LOW Outputs 10 U.L. 5 U.L.

NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL
1 2 3 456

1 23

A0 A1 A2 E

O0 O1 O2 O3 O4 O5 O6 O7

15 14 13 12 11 10 9 7

VCC = PIN 16
GND = PIN 8

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 SN74LS138

LOGIC DIAGRAM

A2 A1 A0 E1 E2 E3
3 2 1 4 5 6 VCC = PIN 16
GND = PIN 8
= Pin Numbers

7 9 10 11 12 13 14 15
O7 O6 O5 O4 O3 O2 O1 O0

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 SN74LS138

FUNCTIONAL DESCRIPTION
The LS138 is a high speed 1-of-8 Decoder/Demultiplexer
fabricated with the low power Schottky barrier diode
process. The decoder accepts three binary weighted inputs
(A0, A1, A2) and when enabled provides eight mutually
exclusive active LOW Outputs (O0 – O7). The LS138
features three Enable inputs, two active LOW (E1, E2) and
one active HIGH (E3). All outputs will be HIGH unless E1
and E2 are LOW and E3 is HIGH. This multiple enable
function allows easy parallel expansion of the device to a
1-of-32 (5 lines to 32 lines) decoder with just four LS138s
and one inverter. (See Figure a.)
The LS138 can be used as an 8-output demultiplexer by
using one of the active LOW Enable inputs as the data input
and the other Enable inputs as strobes. The Enable inputs
which are not used must be permanently tied to their
appropriate active HIGH or active LOW state.

TRUTH TABLE
INPUTS OUTPUTS
E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

A0
A1
A2
LS04
A3

A4
H

123 123 123 123

A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E A0 A1 A2 E

LS138 LS138 LS138 LS138

O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7 O0 O1 O2 O3 O4 O5 O6 O7

O0 O31

Figure a

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 SN74LS138

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol Parameter Min Typ Max Unit Test Conditions
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
0.8 Guaranteed Input LOW Voltage for
VIL Input LOW Voltage V
All Inputs
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
VOH Output HIGH Voltage
or VIL per Truth Table

0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL
O Output LOW Voltage VIN = VIL or VIH
0.35 0.5 V IOL = 8.0 mA per Truth Table

20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current – 0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) – 20 –100 mA VCC = MAX
ICC Power Supply Current 10 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

Levels of Limits
Symbol Parameter Delay Min Typ Max Unit Test Conditions
tPLH Propagation Delay 2 13 20
ns
tPHL Address to Output 2 27 41
tPLH Propagation Delay 3 18 27
ns
tPHL Address to Output 3 26 39 VCC = 5.0 V
tPLH Propagation Delay E1 or E2 2 12 18 CL = 15 pF
ns
tPHL Enable to Output 2 21 32
tPLH Propagation Delay E3 3 17 26
ns
tPHL Enable to Output 3 25 38

AC WAVEFORMS

1.3 V 1.3 V VIN

VIN 1.3 V 1.3 V

tPHL tPLH tPHL tPLH

VOUT
1.3 V 1.3 V VOUT 1.3 V 1.3 V

Figure 1. Figure 2.

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 SN74LS138

PACKAGE DIMENSIONS

N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

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 SN74LS138

PACKAGE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

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 SN74LS138

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http://onsemi.com SN74LS138/D
8
 Unit: mm
19.20
20.00 Max
16 9

7.40 Max
6.30
1 8
1.3

1.11 Max
7.62

2.54 Min 5.06 Max

0.51 Min
+ 0.13
2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05

0° – 15°
Hitachi Code DP-16
JEDEC Conforms
EIAJ Conforms
Weight (reference value) 1.07 g
 Unit: mm

10.06
10.5 Max
16 9

5.5
1 8

*0.22 ± 0.05
0.20 ± 0.04
7.80 +– 0.30
0.20

2.20 Max
0.80 Max 1.15

0° – 8°

0.10 ± 0.10
1.27 0.70 ± 0.20

*0.42 ± 0.08
0.40 ± 0.06
0.15

0.12 M
Hitachi Code FP-16DA
JEDEC —
*Dimension including the plating thickness EIAJ Conforms
Base material dimension Weight (reference value) 0.24 g
 Unit: mm

9.9
10.3 Max
16 9

3.95
1 8

1.75 Max
1.27

*0.22 ± 0.03
0.20 ± 0.03
6.10 +– 0.30
0.10

0.11
0.14 +– 0.04
0.635 Max 1.08

0° – 8°
0.60 +– 0.20
0.67
*0.42 ± 0.08 0.15
0.40 ± 0.06
0.25 M

Hitachi Code FP-16DN

JEDEC Conforms
*Dimension including the plating thickness EIAJ Conforms
Base material dimension Weight (reference value) 0.15 g
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
 DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
August 1986
Revised March 2000

DM74LS244
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description Features
These buffers/line drivers are designed to improve both the ■ 3-STATE outputs drive bus lines directly
performance and PC board density of 3-STATE buffers/ ■ PNP inputs reduce DC loading on bus lines
drivers employed as memory-address drivers, clock driv-
■ Hysteresis at data inputs improves noise margins
ers, and bus-oriented transmitters/receivers. Featuring 400
mV of hysteresis at each low current PNP data line input, ■ Typical IOL (sink current) 24 mA
they provide improved noise rejection and high fanout out- ■ Typical IOH (source current) −15 mA
puts and can be used to drive terminated lines down to
■ Typical propagation delay times
133Ω.
Inverting 10.5 ns
Noninverting 12 ns
■ Typical enable/disable time 18 ns
■ Typical power dissipation (enabled)
Inverting 130 mW
Noninverting 135 mW

Ordering Code:
Order Number Package Number Package Description
DM74LS244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Inputs Output
G A Y
L L L
L H H
H X Z
L = LOW Logic Level
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
Z = High Impedance

© 2000 Fairchild Semiconductor Corporation DS008442 www.fairchildsemi.com

DM74LS244
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 7V Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −15 mA
IOL LOW Level Output Current 24 mA
TA Free Air Operating Temperature 0 70 °C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Min Typ Max
Symbol Parameter Conditions Units
(Note 2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
HYS Hysteresis (VT+ − VT−) VCC = Min 0.2 0.4 V
Data Inputs Only
VOH HIGH Level Output Voltage VCC = Min, VIH = Min
2.7
VIL = Max, IOH = −1 mA
VCC = Min, VIH = Min
2.4 3.4 V
VIL = Max, IOH = −3 mA
VCC = Min, VIH = Min
2
VIL = 0.5V, IOH = Max
VOL LOW Level Output Voltage VCC = Min IOL = 12 mA 0.4
VIL = Max IOL = Max 0.5 V
VIH = Min
IOZH Off-State Output Current, VCC = Max VO = 2.7V 20 µA
HIGH Level Voltage Applied VIL = Max
IOZL Off-State Output Current, VIH = Min VO = 0.4V −20 µA
LOW Level Voltage Applied
II Input Current at Maximum VCC = Max VI = 7V 0.1 mA
Input Voltage
IIH HIGH Level Input Current VCC = Max VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max V I = 0.4V −0.5 −200 µA
IOS Short Circuit Output Current VCC = Max (Note 3) −40 −225 mA
ICC Supply Current VCC = Max, Outputs HIGH 13 23
Outputs Open Outputs LOW 27 46 mA
Outputs Disabled 32 54
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

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 DM74LS244
Switching Characteristics
at VCC = 5V, TA = 25°C
Symbol Parameter Conditions Max Units

tPLH Propagation Delay Time CL = 45 pF

18 ns
LOW-to-HIGH Level Output RL = 667Ω
tPHL Propagation Delay Time CL = 45 pF
18 ns
HIGH-to-LOW Level Output RL = 667Ω
tPZL Output Enable Time to CL = 45 pF
30 ns
LOW Level RL = 667Ω
tPZH Output Enable Time to CL = 45 pF
23 ns
HIGH Level RL = 667Ω
tPLZ Output Disable Time CL = 5 pF
25 ns
from LOW Level RL = 667Ω
tPHZ Output Disable Time CL = 5 pF
18 ns
from HIGH Level RL = 667Ω
tPLH Propagation Delay Time CL = 150 pF
21 ns
LOW-to-HIGH Level Output RL = 667Ω
tPHL Propagation Delay Time CL = 150 pF
22 ns
HIGH-to-LOW Level Output RL = 667Ω
tPZL Output Enable Time to CL = 150 pF
33 ns
LOW Level RL = 667Ω
tPZH Output Enable Time to CL = 150 pF
26 ns
HIGH Level RL = 667Ω

3 www.fairchildsemi.com
DM74LS244
Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B

www.fairchildsemi.com 4
 DM74LS244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D

5 www.fairchildsemi.com
DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

www.fairchildsemi.com 6
 DM74LS245 3-STATE Octal Bus Transceiver
August 1986
Revised March 2000

DM74LS245
3-STATE Octal Bus Transceiver
General Description Features
These octal bus transceivers are designed for asynchro- ■ Bi-Directional bus transceiver in a high-density 20-pin
nous two-way communication between data buses. The package
control function implementation minimizes external timing ■ 3-STATE outputs drive bus lines directly
requirements.
■ PNP inputs reduce DC loading on bus lines
The device allows data transmission from the A Bus to the
■ Hysteresis at bus inputs improve noise margins
B Bus or from the B Bus to the A Bus depending upon the
logic level at the direction control (DIR) input. The enable ■ Typical propagation delay times, port-to-port 8 ns
input (G) can be used to disable the device so that the ■ Typical enable/disable times 17 ns
buses are effectively isolated. ■ IOL (sink current)
24 mA
■ IOH (source current)
−15 mA

Ordering Code:
Order Number Package Number Package Description
DM74LS245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Enable Direction Operation
G Control
DIR
L L B Data to A Bus
L H A Data to B Bus
H X Isolation
H = HIGH Level
L = LOW Level
X = Irrelevant

© 2000 Fairchild Semiconductor Corporation DS006413 www.fairchildsemi.com

DM74LS245
Absolute Maximum Ratings(Note 1)
Supply Voltage 7V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
Input Voltage the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
DIR or G 7V
Characteristics tables are not guaranteed at the absolute maximum ratings.
A or B 5.5V The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −15 mA
IOL LOW Level Output Current 24 mA
TA Free Air Operating Temperature 0 70 °C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
HYS Hysteresis (VT+ − VT−) VCC = Min 0.2 0.4 V
VOH HIGH Level VCC = Min, VIH = Min
2.7
Output Voltage VIL = Max, IOH = −1 mA
VCC = Min, VIL = Min
2.4 3.4 V
VIL = Max, IOH = −3 mA
VCC = Min, VIH = Min
2
VIL = 0.5V, IOH = Max
VOL LOW Level VCC = Min IOL = 12 mA 0.4
Output Voltage VIL = Max V
IOL = Max 0.5
VIH = Min
IOZH Off-State Output Current, VCC = Max
VO = 2.7V 20 µA
HIGH Level Voltage Applied VIL = Max
IOZL Off-State Output Current, VIH = Min
VO = 0.4V −200 µA
LOW Level Voltage Applied
II Input Current at Maximum VCC = Max A or B VI = 5.5V 0.1
mA
Input Voltage DIR or G VI = 7V 0.1
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.2 mA
IOS Short Circuit Output Current VCC = Max (Note 3) −40 −225 mA
ICC Supply Current Outputs HIGH 48 70
Outputs LOW VCC = Max 62 90 mA
Outputs at Hi-Z 64 95
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, not to exceed one second duration

www.fairchildsemi.com 2
 DM74LS245
Switching Characteristics
VCC = 5V, TA = 25°C
Symbol Parameter Conditions Min Max Units
tPLH Propagation Delay Time, CL = 45 pF
12 ns
LOW-to-HIGH Level Output RL = 667Ω
tPHL Propagation Delay Time,
12 ns
HIGH-to-LOW Level Output
tPZL Output Enable Time
40 ns
to LOW Level
tPZH Output Enable Time
40 ns
to HIGH Level
tPLZ Output Disable Time CL = 5 pF
25 ns
from LOW Level RL = 667Ω
tPHZ Output Disable Time
25 ns
from HIGH Level
tPLH Propagation Delay Time, CL = 150 pF
16 ns
LOW-to-HIGH Level Output RL = 667Ω
tPHL Propagation Delay Time,
17 ns
HIGH-to-LOW Level Output
tPZL Output Enable Time
45 ns
to LOW Level
tPZH Output Enable Time
45 ns
to HIGH Level

3 www.fairchildsemi.com
DM74LS245
Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B

www.fairchildsemi.com 4
 DM74LS245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D

5 www.fairchildsemi.com
DM74LS245 3-STATE Octal Bus Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

www.fairchildsemi.com 6