a Programmable

Oscillator
AD2S99
FEATURES FUNCTIONAL BLOCK DIAGRAM
Programmable Sinusoidal Oscillator
Synthesized Synchronous Reference Output
Programmable Output Frequency Range: 2 kHz–20 kHz PUSH/ EXC
PULL TO
“Loss-of-Signal” Indicator O/P STAGE
TRANSDUCER
EXC
20-Pin PLCC Package
Low Cost FBIAS

SEL1 FREQUENCY SINE WAVE

APPLICATIONS SELECT GENERATOR
Excitation Source for: SEL2

Resolvers SYNREF
SYNCHRONOUS
PHASE
Synchros DETECT
REFERENCE
LVDTs AD2S99 LOGIC LOS
RVDTs
Pressure Transducers SIN COS
Load Cells
AC Bridges FROM
TRANSDUCER

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD2S99 programmable sinusoidal oscillator provides sine
wave excitation for resolvers and a wide variety of ac transduc-
ers. The AD2S99 also provides a synchronous reference output
signal (3 V p-p square wave) that is phase locked to its SIN and
COS inputs. In an application, the SIN and COS inputs are
connected to the transducer’s secondary windings.
The synchronous reference output compensates for temperature
and cabling dependent phase shifts and eliminates the need for
external preset phase compensation circuits. The synchronous
reference output can be used as a zero crossing reference for
resolver-to-digital converters such as Analog Devices’ AD2S80A,
AD2S82A, AD2S83 and AD2S90.
The AD2S99 is packaged in a 20-pin PLCC and operates over
–40°C to +85°C.
Dynamic Phase Compensation
The AD2S99 dynamically compensates for any phase variation
in a transducer by phase locking its synchronous reference out-
put to the transducer’s secondary windings.
Programmable Excitation Frequency
The excitation frequency is easily programmed to 2 kHz, 5 kHz,
10 kHz, or 20 kHz by using the frequency select pins. Interme-
diate frequencies are available by adding an external resistor.
Signal Loss Detection
The AD2S99 has the ability to detect if both the transducer sec-
ondary winding connections become disconnected from its SIN
and COS inputs. The “LOS” output pin pulls high when a sig-
nal loss is detected.
Integration
The AD2S99 integrates the transducer excitation, synchronous
reference, and loss of signal detection functions into a small,
cost effective package.

REV. B
Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD2S99–SPECIFICATIONS (V = 64.75 V to 65.25 V @ –408C to +858C unless otherwise noted)
S

Parameter Min Typ Max Units Test Conditions

FREQUENCY OUTPUT RANGE SEL1 SEL2
2 kHz 2000 Hz VSS VSS
5 kHz 5000 Hz VSS GND
10 kHz 10000 Hz GND VSS
20 kHz 20000 Hz GND GND
ACCURACY
Frequency ± 10 % AP Grade @ +25°C
± 20 % AP Grade –40°C to +85°C
±5 % BP Grade @ +25°C
± 10 % BP Grade –40°C to +85°C

Amplitude ±3 ± 10 % AP Grade @ +25°C

± 20 % AP Grade –40°C to +85°C
±3 ±5 % BP Grade @ +25°C
± 10 % BP Grade –40°C to +85°C
Power Supply Rejection Ratio 0.002 V p-p/V Output Variation as Function of
Change in Power Supply Voltage
ANALOG OUTPUTS
Amplitude
EXC, EXC 2 V rms EXC to GND, EXC to GND
SYNREF ±3 V p-p Square Wave
SYNREF OFFSET ± 200 mV
Current Drive Capability
EXC, EXC VS = ± 5 V 8 mA rms RLOAD = 500 Ω EXC to EXC
CLOAD = 1000 pF
Capacitive Drive 1000 pF
Total Harmonic Distortion
EXC, EXC –25 dB
ANALOG INPUTS SIN, COS
Amplitude 1.8 2.0 2.2 V rms
Phase Lock Range –45 +45 Degrees
Additional Phase Delay
± 10 Degrees AP Grade
± 10 Degrees BP Grade
FREQUENCY SELECT INPUTS
SEL1, SEL21 VSS AGND V dc
LOS OUTPUT
Output Low Voltage 0.7 V dc IOL = 400 µA
Output High Voltage VDD V dc 50 kΩ Pull Up to VDD (Open
Drain Output)
SIN, COS LOS Threshold 0.5 0.6 0.8 V rms
POWER SUPPLIES
VDD +4.75 +5.25 V dc
VSS –4.75 –5.25 V dc
Quiescent Current IDD, ISS ±8 ± 15 mA No Load
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –65 +150 °C
NOTES
1
Frequency select pins SEL1 and SEL2 must be connected to appropriate voltage levels before power is applied.
Specifications subject to change without notice.

–2– REV. B
 AD2S99
ABSOLUTE MAXIMUM RATINGS* PIN DESIGNATIONS
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V Pin
Operating Temperature . . . . . . . . . . . . . . . . . . –40°C to +85°C No. Mnemonic Description
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C 1 SEL2 Frequency Select 2
Analog Input Voltages (SIN and COS) . . . . . . . . . VSS – 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to VDD + 0.3 V 2 SEL1 Frequency Select 1
Frequency Select (SEL1, SEL2) . . . . . . . . . . . . . . VSS – 0.4 V 3 FBIAS External Frequency Adjust Pin
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND + 0.4 V 5 SIN Resolver Output SIN
*Stresses above those listed under “Absolute Maximum Ratings” may cause 61 DGND Digital Ground
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the 7 COS Resolver Output COS
operational section of this specification is not implied. Exposure to absolute 10 SYNREF Synthesized Reference Output
maximum rating conditions for extended periods may affect device reliability.
11 LOS Indicates When Both the SIN and
COS Are Below the Threshold.
RECOMMENDED OPERATING CONDITIONS 12 VDD Positive Power Supply
Power Supply Voltage (VDD to VSS) . . . . . . ± 4.75 V to ± 5.25 V 161 AGND Analog Ground
Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ± 10%
17 EXC Resolver Reference One
Frequency Select (SEL1 and SEL2) . . . . . . . . . VSS to AGND
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C 18 EXC Resolver Reference Two3
192 VSS Negative Power Supply
202 VSS Negative Power Supply
ORDERING GUIDE NOTES
1
Pins 6 and 16 must be connected together.
Model Temperature Range Package Option* 2
Pins 19 and 20 must be connected together.
3
Resolver Reference two (EXC) is 180° phase advanced with respect to Resolver
AD2S99AP –40°C to +85°C P-20A Reference one (EXC).
AD2S99BP –40°C to +85°C P-20A
PIN CONFIGURATION
*P = PLCC.

FBIAS
SEL1

SEL2

VSS
VSS
3 2 1 20 19

NC 4 18 EXC
SIN 5 17 EXC
AD2S99
DGND 6 TOP VIEW 16 AGND
(Not to Scale)
COS 7 15 NC
NC 8 14 NC

9 10 11 12 13
SYNREF

LOS

NC
NC

VDD

NC = NO CONNECT

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD2S99 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B –3–
AD2S99
CONNECTING THE AD2S99 OSCILLATOR 20
Refer to Figure 1. Positive supply voltage VDD should be con- 18
nected to Pin 12 and negative supply voltage VSS should be con-
16
nected to both Pins 19 and 20. Reversal of these power supplies will
destroy the device. The appropriate voltage level for the power 14

FREQUENCY – kHz
supplies is ± 5 V dc ± 5%. Both VSS Pins (19 and 20) must be 12
connected together, and Digital Ground (Pin 6) must be con-
10
nected to Analog Ground (Pin 16) locally at the AD2S99.
8

VSS 6
4.7µF 0.1µF
4
FBIAS

SEL2
SEL1

2
VSS
VSS

3 2 1 20 19 RESOLVER
0
0 4 8 12 16 20 24 28
NC EXC ADDITIONAL RESISTANCE – kΩ
4 18
REF SIN RESISTOR PULLUP TO VDD FROM FBIAS
SIN EXC
5 17
DGND
6 AD2S99 16
AGND Figure 2. Typical Added Resistance Value
COS
7 15 NC
NC 8 14 NC
COS AD2S99 OSCILLATOR OUTPUT STAGE
The output of the AD2S99 oscillator consists of two sinusoidal
9 10 11 12 13
.. signals, EXC, and EXC. EXC is 180° phase advanced with re-
. RX *
NC
NC
SYNREF
LOS
VDD

spect to EXC. The excitation winding of a transducer should be

50kΩ
VDD
0.1µF 4.7µF
NC = NO CONNECT
*RX IS ONLY REQUIRED FOR INTERMEDIATE FREQUENCIES.
FIXED FREQUENCIES ONLY REQUIRE A LINK.
Figure 1. Typical Configuration
It is recommended that decoupling capacitors are connected in
parallel between VDD and Analog Ground and VSS and Analog
Ground in close proximity to the AD2S99. The recommended
values for the decoupling capacitors are 100 nF (ceramic) and
4.7 µF (tantalum). When multiple AD2S99s are used, separate
decoupling capacitors should be used for each AD2S99.
FREQUENCY ADJUSTMENT
The output frequency of the AD2S99 is programmable to four
standard frequencies (2, 5, 10, or 20 kHz) using the SEL1 and
SEL2 pins. The output can also be adjusted to provide interme-
diate frequencies by connecting a resistor from the FBIAS pin to
the positive supply VDD. The FBIAS pin is connected directly to
VDD during normal operation. A graph showing the typical
added resistance values for various intermediate frequencies is
provided in Figure 2. The procedure for obtaining an intermedi-
ate frequency is:
1. Set the output frequency via the SEL1, SEL2 pins to the fre-
quency immediately above the required intermediate frequency.
2. Connect the frequency adjust pin FBIAS to VDD via an exter-
nal resistor.
For example: to obtain an output frequency of 8 kHz, set the
nominal output frequency to 10 kHz by connecting SEL1 to
GND and SEL2 to VSS. Connect FBIAS to VDD via a 6 kΩ
resistor (refer to Figure 2).
100nF
TO AD2S80/ connected across EXC (Pin 17) and EXC (Pin 18).
AD2S90 REF INPUT
100kΩ With low impedance transducers, it may be necessary to in-
crease the output current drive of the AD2S99. In such an in-
SEL2 = GND ]
–5kHz MODE stance, an external buffer amplifier can be used to provide gain
SEL1 = V SS ]
INCREASE RX TO LOWER (as needed), and additional current drive for the excitation out-
OUTPUT FREQUENCY put (either EXC or EXC) of the AD2S99, providing a single
(SEE GRAPH)
ended drive to the transducer. Refer to Figures 6, 7 and 8 for
sample buffer configurations.
The amplitude modulated SIN and COS output signals from a re-
solver should be connected as feedback signals to the AD2S99.
The SYNREF output compensates for any primary to secondary
phase errors in the resolver. These errors can degrade the accuracy
of a Resolver-to-Digital Converter (R/D Converter).
SIN, from the resolver, should be connected to the AD2S99 SIN
input and COS should be connected to the AD2S99 COS input.
The SIN Lo, COS Lo (resolver signal returns) should be con-
nected to AGND and the R/D Converter as applicable.
The synthesized reference (SYNREF) from the AD2S99 should
be connected to the reference input pin of the R/D Converter.
The SYNREF signal is a square wave at the oscillator frequency
of amplitude ± 3 V p-p and is phase coherent with the SIN and
COS inputs. If this signal is used to drive the reference input of
the AD2S90 R/D Converter, a coupling capacitor and resistor to
GND must be connected between the SYNREF output of the
AD2S99 and the REF input of the R/D Converter (see Figure
3). Please read the appropriate R/D Converter data sheets for
further clarification.
LOSS OF SIGNAL
During normal operation when both the SIN and COS signals
on the resolver secondary windings are connected to the
AD2S99, the LOS output pin of the AD2S99 (Pin 11) is at a
Logic Lo (<0.7 V). If both the SIN and COS signals on the re-
solver secondary windings fall below the LOS threshold level of
the AD2S99, the LOS pin of the AD2S99 will pull up to a
Logic Hi (VDD) level.

–4– REV. B

AD2S99/AD2S90 TYPICAL CONFIGURATION
Figure 3 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S90 Resolver-to-Digital Converter. The
maximum level of the SIN and COS input signals to the
AD2S90 should be 2 V rms ± 10%. All the analog ground sig-
nals should be star connected to the AD2S90 AGND pin. If
shielded twisted pair cables are used for the resolver signals, the
AD2S99
shields should also be terminated at the AD2S90 AGND pin.
The SYNREF output of the AD2S99 should be connected to
the REF input pin of the AD2S90 via a 0.1 µF capacitor with a
100 kΩ resistor to GND. This is to block out any dc offset in
the SYNREF signal. For more detailed information please refer
to the AD2S90 data sheet.

VDD VSS
0.1µF 4.7µF

FBIAS

SEL2
SEL1

VSS
VSS
NC = NO CONNECT 3 2 1 20 19

EXC
NC 4 18
SIN EXC
5 17
DGND AD2S99 AGND
6 TOP VIEW 16
SEL2 = GND COS (Not to Scale)
SEL1 = VSS 7 15 NC
FOUT = 5kHz NC 8 14 NC

9 10 11 12 13

LOS
VDD

NC
SYNREF
NC
VDD
50kΩ
0.1µF 4.7µF

0.1µF 100kΩ

18 17 16 15 14 VDD
0.1µF 4.7µF
S4 REF VDD
19 COS LO VDD 13
0.1µF 4.7µF
20 COS VSS 12 VSS
S2
1 AGND DGND 11
S2 COS S4 S3
2 SIN AD2S90 10
R2 S3
3 SIN LO TOP VIEW 9
(Not to Scale)
REF SIN
S1 4 5 6 7 8
R4
RESOLVER S1 POWER
RETURN

Figure 3. AD2S99 and AD2S90 Example Configuration

REV. B –5–
AD2S99
AD2S99/AD2S82A TYPICAL CONFIGURATION
Figure 4 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S82A Resolver-to-Digital Converter.
The maximum level of the SIN and COS input signals to the
AD2S82A should be 2 V rms ± 10%. All the analog ground sig-
nals should be star connected to the AD2S82A AGND pin. If
shielded twisted pair cables are used for the resolver signals, the
shields should also be terminated at the AD2S82A AGND pin.
Coupling capacitor C3, and resistor to GND R3, between the
SYNREF output of the AD2S99 and the REF input pin of the
AD2S82A are optional. For additional information on selecting
component values for the AD2S82A, please refer to the
AD2S82A data sheet or the application note “Passive Compo-
nent Selection and Dynamic Modeling for the AD2S80 Series
Resolver-to-Digital Converters” (AN-266).

R3, C3 OPTIONAL VELOCITY

SYNREF C3 OUTPUT
C5
COS R5
R3
COS
R2
C4
REF SIN C1 C2
–5V

4.7µF R1 AGND
RESOLVER R4 0V
SIN R6

AGND 6 5 4 3 2 1 44 43 42 41 40 0.1µF 10µF

SIN
0.1µF I/P –VS

INTEGRATOR O/P
A GND

DEMOD O/P

INTEGRATOR I/P

VCO I/P
AC ERROR O/P

VCO O/P
COS I/P

DEMOD I/P
REFERENCE I/P
SIG GND
3 2 1 20 19 10µF 7 39
0.1µF +VS –12V
8 38 RC
SEL1
FBIAS

EXC
SEL2
FBIAS

VSS
VSS

NC 4 18 +12V
SIN EXC NC 9 37 DIR
5 17 MSB DB1
AD2S99 AGND 10 36 BUSY
DGND TOP VIEW
6 16
COS (Not to Scale) DB2 11 35 DATA LOAD
7 15 NC
SYNREF

DB3 12 34 COMP
NC 8 14 NC AD2S82A
LOS

VDD
NC

NC

DB4 13 TOP VIEW 33 SC2

(Not to Scale)
9 10 11 12 13 DB5 14 32 SC1
DIGITAL GND
DB6 15 31
0.1µF LSB DB16
4.7µF

ENABLE
50k DB7 16 30 INHIBIT

SELECT
+5V

BYTE
DB13

DB15
DB10
DB11
DB12

DB14

DB8 17 29 NC
DB9

+VL

NC = NO CONNECT
LOS
DIGITAL 18 19 20 21 22 23 24 25 26 27 28
OUTPUT
DATA +5V
SEL1 = GND
SEL2 = VSS 0.1µF 10µF
DGND
FOUT = 10kHz

Figure 4. AD2S99 and AD2S82A Example Configuration

–6– REV. B

AD2S99/AD2S93 TYPICAL CONFIGURATION
Figure 5 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S93 LVDT-to-Digital Converter. The
maximum level of the A and B transducer input signals to the
AD2S93 should be 1 V rms ± 20%. All the analog ground sig-
nals should be star connected to the AD2S93 AGND pin. If
shielded twisted pair cables are used for the LVDT signals, the
AD2S99
shields should also be terminated at the AD2S93 AGND pin.
The SYNREF output of the AD2S99 cannot be used as the
REF input signal for the AD2S93. The zero crossing reference
for the AD2S93 should be taken from the primary winding of
the LVDT through a phase lead or lag network. The phase com-
pensation network ensures that the REF input is phase coherent
with the A and B input signals to the AD2S93.

VDD VSS
0.1µF 4.7µF

FBIAS
SEL1

SEL2
VSS
VSS
NC = NO CONNECT 3 2 1 20 19

EXC
NC 4 18
SIN EXC
5 AD2S99 17
DGND AGND
6 TOP VIEW 16
COS (Not to Scale)
7 15 NC
NC 8 14 NC
SEL2 = GND
SEL1 = VSS
FOUT = 5kHz 9 10 11 12 13

VDD
LOS
SYNREF
NC

NC
VDD
50kΩ
0.1µF 4.7µF
LOS

C1 C4

R2 C2 R6 C3

R5
PHASE
COMP
25 24 23 22 21 20 19 R7
REF

VEL
NC

DMODIN
ACERROR
INTIN

VGAIN

26 18
NC DMODOUT
27 B VDD 17 VDD
B 0.1µF 4.7µF
PRI 28 A VSS 16
AD2S93
0.1µF 4.7µF
SEC 1 AGND TOP VIEW DGND 15
(Not to Scale) VSS
2 DIFF DIR 14
A
3 GAIN NULL 13
LVDT
4 LOS OVR 12

5 6 7 8 9 10 11
NC
CLKOUT
NC
DATA

CS
SCLK

UNR

NC = NO CONNECT

Figure 5. AD2S99 and AD2S93 Example Configuration

REV. B –7–
AD2S99

FBIAS
FBIAS

SEL1
SEL2
SEL1
SEL2
+VS

VSS

VSS
VSS

VSS
VOUT = 2VRMS
3 2 1 20 19 3 2 1 20 19

VOUT NC 4 18 EXC *
NC 4 18 EXC
EXC 6
SIN 5 EXC SIN 5 AD2S99 17 4 7
AD2S99 17 REF SIN AGND 8
DGND 6 TOP VIEW 16 SSM2142
DGND 6 TOP VIEW 16 AGND (Not to Scale) 1

C1978b–10–6/95
(Not to Scale) COS 7 15 NC 3 2
COS 7 15 NC 5 RESOLVER
COS
NC 8 14 NC
NC 8 14 NC
*
9 10 11 12 13
9 10 11 12 13

VDD
SYNREF
LOS
NC

NC
VDD
SYNREF
LOS
NC

NC

NC = NO CONNECT –VS
NC = NO CONNECT
*OPTIONAL; CONSULT APPROPRIATE
ANALOG DEVICES DATA SHEET.
Figure 6. Sample Buffer Configuration
Figure 8. The SSM2142 as a Single Ended to Differential
R2 Driver
VIN R1
PIN 17 VOUT
EXC

OUTLINE DIMENSIONS
PIN 16
AGND RESOLVER Dimensions shown in inches and (mm).
R2
(
VOUT = 2VRMS x – –––
R1
)
PLCC (P-20A)
R2

VIN R1 OP279 0.048 (1.21) 0.180 (4.57)

PIN 18 VOUT 0.165 (4.19)
0.042 (1.07)
EXC 0.056 (1.42)
0.025 (0.63)
0.042 (1.07)
0.015 (0.38)
0.048 (1.21)
PIN 16 3 19
0.042 (1.07) 0.021 (0.53)
AGND OP279 4 PIN 1 18
0.013 (0.33)
IDENTIFIER
RESOLVER 0.330 (8.38)
EXC R1
0.050 TOP VIEW 0.290 (7.37)
PIN 17
(1.27) 0.032 (0.81)
R2
BSC 0.026 (0.66)
8 14
R2
VOUT = 2VRMS x 2 x – –––
R1
( ) 0.020
9 13
0.040 (1.01)
(0.50) 0.356 (9.04)
A SUITABLE AMPLIFIER FOR ABOVE IS THE OP279 SQ 0.025 (0.64)
R 0.350 (8.89)
0.110 (2.79)
0.395 (10.02)
SQ 0.085 (2.16)
0.385 (9.78)
Figure 7. Sample Buffer Configurations

PRINTED IN U.S.A.

–8– REV. B
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