DDMP Unit 5 Final

Microprocessors and
Interfacing
Dr V S M Srinivasavarma
1 November 2023 Dr VSMS 1

Outline
◆8086 Architecture
◆Instruction Set
◆Assembly Language Programming
◼ Programming Assignments
◆8086 Interfacing
◼ Interfacing Hardware designs and its programming
◆Applications
1 November 2023 Dr. VSMS 2

8086 Microprocessor
◆Two parts
◆Bus Interface Unit (BIU)
◼ Hardware functions
◼ Generation of the memory and I/O addresses for the
transfer of data between the outside world and vice-versa
◆Execution Unit (EU)
◼ Receives the program instruction codes and data from BIU
◼ Executes these instructions, and stores the results in the
general registers.
◼ By passing the data back to BIU, data can also be stored in
a memory location or written to an output device.

Internal Block Diagram of 8086
Address bus Data bus
I
n
Arithmetic
Address generation t Logic Unit
and bus control e Flags
r
6 5 4 3 2 1
n
∑ a General Purpose Registers
l
AH AL AX
BH BL BX
D
a CH CL CX
CS
t DH DL DX
ES
a BP
SS
DI
DS B
SI
Instruction Pointer u
s SP
Bus Interface Unit (BIU)

Execution Unit (EU)

Fetch and Execution
◆ The BIU outputs the contents of the instruction pointer register
(IP) onto the address bus, causing the selected byte or word to
be read into the BIU.
◆ Register IP is incremented by 1 to prepare for the next
instruction fetch
◆ Once inside the BIU, the instruction is passed to the queue.
This first-in, first-out storage register sometimes likened to a
‘pipeline’
◆ Assuming the queue is initially empty. The EU immediately
draws this instruction from the queue and begins execution
◆ While EU is executing this instruction, the BIU proceeds to
fetch a new instruction.
◆ Depending on the execution of the first instruction, the BIU
may fill the queue with several new instructions before the EU
is ready to draw its next instruction
Programming Model
AX AH AL Accumulator
BH BL Base Status and
BX FlagsH FlagsL Control Flags
CX CH CL Count
DX DH DL Data
SP Stack Pointer
ES Extra Segment
BP Base Pointer
CS Code Segment
SI Source Index
DS Data Segment
DI Destination Index
SS Stack Segment
IP Instruction Pointer

Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Bit Name Function

Position
0 CF Set on high-order bit carry or barrow; cleared otherwise
2 PF Set if low-order 8 bits of result contain an even number of 1-bits; cleared otherwise
4 AF Set on carry from or borrow to the low-order 4-bits of AL; cleared otherwise
6 ZF Set if result is zero; cleared otherwise
7 SF Set equal to high-order bit of result (0 is positive, 1 if negative)
8 TF Once set, a single-step interrupt occurs after the next instruction executes; TF is cleared by
the single step interrupt
9 IF When set, maskable interrupts will cause the CPU to transfer control to an interrupt vector
specified location
10 DF Causes string instructions to auto decrement the appropriate index register when set;
clearing DF causes auto increment
11 OF Set if the signed result cannot be expressed within the number of bits in the destination
operand; cleared otherwise

Segmented Memory
◆8086 microprocessor has 20-bit address lines
◼ 220 Address locations can be accessed
◼ Each memory location store 1 byte (8-bits) of information
◆It has 16-bit data lines
◼ Two memory locations hold 1 word of information
◼ It means it will have lower byte and higher byte
◼ All lower bytes can be stored in even locations
◼ Called EVEN bank
◼ All the higher bytes can be stored in even locations

◼ Called ODD Bank

Memory Banks
Byte 1048575
Word 524287
Byte 1048574
Even Bank Odd Bank
1048574 1048574
Byte 7
Byte 6 Word
Read 2
starting
Read 1 Byte 5
at an odd
Byte 4 address
8 9
6 7
4 5
2 3
Byte 5 0 1
Word 2
Byte 4
Byte 3
Word 1 If a 16 bit word begins at an odd
Byte 2 address, the 8086 will require
two memory read or write cycles
Byte 1 16 bit data word to 8086
Word 0
Byte 0

Memory Map
◆RAM – 00000H to 3FFFFH
◆ROM – FF000H to FFFFFH
◆Reserved – FFFFBH to FFFFFH
◼ System Interrupts and reset function
◆Dedicated – FFFF0H to FFFFAH
◼ OS Calls

Segment Registers
◆1MB memory space of 8086 defines four 64KB
memory blocks
◼ Code Segment
◼ Holds program instruction codes
◼ Data Segment
◼ Stores data for program
◼ Stack Segment
◼ Store interrupt and subroutine return addresses
◼ Extra Segment
◼ Extra data segment (often used for shared data)
◆ 8085 – Program instructions, data and subroutine

stack all have to share the same memory.
Segmented Memory
FFFFFH
Data Segment EFFFFH
E000 Data Segment
E0000H
Code Segment
C3FEFH
B3FF Code Segment
B3FF0H
Stack Segment
5D27
6D26FH
Extra Segment Stack
6288FH
Segment
Extra
52B9 5D270H Segment
52B90H
00000H

8086 Instruction Set

Data Transfer Instructions
MOV Destination, Source Example
MOV Register, Register MOV AX, BX; (AX  BX)
MOV AH, BL (AH  BL)
MOV Memory, Register MOV MEMWDS, BX ;[1000H]BL; [1001H]BH
MOV MEMBDS, BL ;[1002H]BL
MOV Register, Memory MOV AX, MEMWDS ;AL  [1000H]; AH  [1001H]
MOV AL, MEMBDS ; AL  [1002H]
MOV Memory, Immediate Data MOV MEMWDS, 1234H ; [1000H] 34H; [1001H]12H
MOV MEMBDS, 56H ;[1002H]  56H
MOV Register, Immediate Data MOV BL,18H ; BL  18H
MOV CX, 5678H ; CL  78H, CH  56H
MOV AX/AL, Memory MOV AL,28H ; AL  28H
MOV AX, 5678H ; AL  78H, AH  56H
MOV Memory, AX/AL MOV MEMWDS, AX ;[1000H]AL; [1001H]AH
MOV MEMBDS, AL ;[1002H]AL
MOV SegRegister, Memory16 MOV ES, MEMWDS ;ES  [1001H:1000H]
MOV SegRegister , Register16 MOV DS, AX ; DS  AX
MOV Memory16, SegRegister MOV MEMWDS, CS ;[1001H:1000H]  CS
MOV Register16, SegRegister MOV DX, ES ; DX  ES

Data Transfer Instructions
XCHG Operand1 Operand 2 Example
XCHG Register, Memory XCHG BX, [SI] ; BL ↔ [SI]; BH ↔ [SI+1]
XCHG Register, Register XCHG AX, BX ; AX ↔ BX

XCHG AL, BH ; AL ↔ BH
XCHG Memory Register XCHG [SI], DX ; [SI] ↔ DL; [SI+1] ↔ DH
Opcode Destination Source Example

IN Accumulator, Port IN AL, 26H ; AL  port 26H
IN AX, 26H ; AL  port 26H; AH  port 27H
OUT Port Accumulator OUT 26H, AL ; port 26H  AL
OUT 26H, AX ; port 26H  AL; port 27H  AH
LEA Destination Source LEA BX, MEMBDS ; BL  00H; BH  10H`
; Effective address of the source operand is transferred to the
destination operand
XLAT No Operands AL  [BX + AL] ; Replace the byte in AL with a byte from the
256-byte table beginning at [BX]; Use AL as an offset into this
table
LAHF No Operands AH  FlagsL ; Copy the lower order flag byte into AH
SAHF No Operands FlagsL  AH ; Copy AH into the low-order flag byte

Logical Instructions
Opcode Destination, Source Example
NOT Register -- NOT BX ; BX  ~BX
NOT Memory -- NOT [SI] ; [SI]  ~[SI]
AND Destination Source

OR Destination Source
XOR Destination Source
TEST Destination Source TEST CX, DX ; Performs a bit-by-bit AND of the source and
destination byte or word operands;
•The operands remains unchanged
•All flags get updated except AF
Usage:
AND Register Register AND CX, DX
AND Memory Register AND [SI}, AX
AND Register Memory AND AX, [SI]
AND Register Immediate Data AND BX, 8000H
AND Memory Immediate Data AND [SI], FF00H

Shift and Rotate Instructions
Opcode Destination, Count Example
SHL Register 1 Logical Left Shift by 1
SHL Memory 1 Logical Left Shift by 1
SHL Register Immediate Logical Left Shift by the value of Immediate
SHL Memory Immediate Logical Left Shift by the value of Immediate
SHL Register CL Logical Left Shift by the content of CL register
SHL Memory CL Logical Left Shift by the content of CL register
SAL Destination, Count Arithmetic Left Shift - leaving Sign Bit
SAR Destination, Count Arithmetic Right Shift - leaving Sign Bit
SHR Destination, Count Logical Right Shift
RCL Destination, Count Rotate through Carry Left
RCR Destination, Count Rotate through Carry Right
ROL Destination, Count Rotate Left
ROR Destination, Count Rotate Right

Shift and Rotate Instructions
Bit 7/15 Bit 0
CF DATA 0 Logical Left Shift SHL
Bit 7/15 Bit 0

0 DATA CF Logical Right Shift SHR
SAR
DATA CF Arithmetic Right Shift
SAL
CF SF DATA 0
Arithmetic Left Shift

Rotate Instructions
RCL
CF DATA Rotate Through Carry Left
RCR
DATA CF Rotate Through Carry Right
ROL
CF DATA Rotate Left
ROR
DATA CF Rotate Right

Arithmetic Instructions
Opcode Destination, Source Expression
ADD Dest Src Dest = Dest + Src
ADC Dest Src Dest = Dest + Src + C
SUB Dest Src Dest = Dest – Src
SBB Dest Src Dest = Dest – Src – C
CMP Dest Src Dest - Src (and set flags)
; Operands Remained Unchanged
INC Dest Dest = Dest + 1
DEC Dest Dest = Dest – 1
NEG Dest Dest = – Dest ;(2’s complement of Dest)
MUL Src [DX][AX]  [AX] * [Dest]
[AX]  [AL] * [Dest]
IMUL Src [DX][AX]  [AX] * [Dest]
[AX]  [AL] * [Dest]
Signed Multiplication

Arithmetic Instructions
Opcode Destination, Source Expression
DIV Src DIV BL; AX  AL/ BL
DIV CX; DX:AX  AX/ CX
IDIV Src IDIV BL; AX  AL/ BL (Signed)
IDIV CX; DX:AX  AX/ CX (Signed)
Quotient in AX and Remainder in DX
DAA -- If AL . 0F> 9 or AF = 1, then AL  AL + 6; AF  1
If AL > 9F or CF = 1, then AL  AL + 60H; CF  1
DAS -- If AL . 0F> 9 or AF = 1, then AL  AL – 6 ; AF  1
If AL > 9F or CF = 1, then AL  AL – 60H ; CF  1

Transfer Control Instructions
Opcode Traget Expression
JMP disp8 ;direct intrasegment, 8 bit displacement
JMP F8H ; IP  F8H
JMP disp16 ;direct intrasegment, 16 bit displacement
JMP FF09H ;IP  FF09H
JMP Memory16 ;indirect intrasegment, 16 bit memory operand
JMP [BX]
JMP Register16 ;register indirect intrasegment
JMP AX ; IP  AX
LOOP Address CX  CX – 1; if CX ≠ 0, then IP  Address
LOOPE/ Target CX  CX – 1;
LOOPZ If (CX ≠ 0). (ZF=1) then IP Target
LOOPNE/ Target CX  CX – 1;
LOOPNZ If (CX ≠ 0). (ZF=0) then IP Target

Conditional Jump Instructions
JG/JNLE Address Greater/not less nor equal ((SF ^OF )+ ZF) = 0
JGE/JNL Address Greater or equal/ not less (SF ^ OF) = 0
JL/JNGE Address Less/ not greater nor equal (SF ^ OF) = 1
JLE/JNG Address Less or equal/ not greater ((SF ^ OF) + ZF) = 1
JO Address Overflow (OF = 1)
JS Address Sign (SF = 1)
JNO Address Not Overflow (OF = 0)
JNS Address Not Sign (SF = 0)
JA/JNBE Address Above/not below nor equal (CF ^ ZF) = 0
JAE/JNB Address Above or Equal/ not Below (CF = 0)
JB/JNAE Address Below/ not above nor equal (CF = 1)
JBE/JNA Address Below or equal/ not above (CF ^ ZF) = 1

Conditional Jump Instructions
JC Address Carry (CF = 1)
JE/JZ Address Equal/ Zero (ZF = 1)
JP/ JPE Address Parity/ Parity Even (PF = 1)
JNC Address Not Carry (CF = 0)
JNE/JNZ Address Not Equal/ Not Zero (ZF = 0)
JNP/JPO Address Not Parity/ Parity Odd (PF = 0)

PUSH and POP Instructions
PUSH Source PUSH CX ;SP  SP – 2; [SP+1]  CH; [SP]  CL

POP Destination POP CX ;CL  [SP]; CH [SP+1]; SP  SP + 2
PUSHF -- SP  SP – 2; [SP+1 : SP]  Flags
POPF -- Flags  [SP+1 : SP]; SP  SP + 2
CALL Near Target CALL MEM ; SP  SP – 2; [SP+1 : SP]  IP; IP  MEM
CALL Far Target SP  SP – 2; [SP+1 : SP]  CS CS  New CS
SP  SP – 2 ; [SP+1 : SP]  IP IP  1000
RET Near Target IP  [SP+1 : SP]; SP  SP + 2

RET Far Target IP  [SP+1 : SP]; SP  SP + 2
CS  [SP+1 : SP]; SP  SP + 2

Process Control Instructions
Opcode Traget Expression Description
STC -- CF  1 Set Carry Flag
CLC -- CF  0 Clear Carry Flag
CMC -- CF  ~CF Complement Carry Flag
STD -- DF  1 Set Direction Flag (Auto Decrement for String
Instructions)
CLD -- DF 0 Clear Direction Flag (Auto Increment for string
instructions
STI -- IF  1 Set Interrupt Flag (Enabling Interrupts on the INTR line)
CLI -- IF  0 Clear Interrupt Flag (Disabling the interrupt on the
INTR Line)
HLT -- -- Halt
WAIT -- -- Enter Wait state if ~TEST line = 1
NOP -- -- No Operation

8086 Instruction Format

Assembly Language to Machine Instructions
Opcode D W MOD REG R/M
6 1 1 2 3 2
◆ An instruction can be coded with 1 to 6 bytes
◆ Byte 1 contains three kinds of information
◼ Opcode field is 6-bits specifies the operation such as add, subtract or
move
◼ Register Direction Bit (D-bit)
◼ Tells the register operand in REG field in byte 2 is source or destination
operand
◼ 1: Data flow to the REG field from R/M
◼ 0: Data flow from the REG to the R/M
◼ Data Size Bit (W bit)

◼ Specifies whether the operation will be performed on 8-bit or 16-
bit data
◼ 0: 8 – bits
◼ 1: 16-bits

◆ Byte 2 has Two Fields
◼ Mode field (MOD) – 2 bits
◼ Register field (REG) – 3 bits
◼ Register/ memory field (R/M field) – 2 bits
◆ REG field is used to identify the register for the first operand
REG W=0 W=1
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

◆ 2-bit MOD Field and 3-bit R/M field together specify the second operand
MOD Description
00 Memory Mode, No displacement follows*
* Except When R/M = 100,
01 Memory Mode, 8-bit displacement follows then 16-bit displacement
follows
10 Memory Mode, 16-bit displacement follows
11 Register Mode (no displacement)

MOD = 11 Effective Address Calculation

R/M W=0 W=1 R/M MOD=00 MOD=01 MOD=10
000 AL AX 000 [BX] + [SI] [BX] + [SI] + D8 [BX] + [SI] + D16
001 CL CX 001 [BX] + [DI] [BX] + [DI] + D8 [BX] + [DI] + D16
010 DL DX 010 [BP] + [SI] [BP] + [SI] + D8 [BP] + [SI] + D16
011 BL BX 011 [BP] + [DI] [BP] + [DI] + D8 [BP] + [DI] + D16
100 AH SP 100 [SI] [SI] + D8 [SI] + D16
101 CH BP 101 [DI] [DI] + D8 [DI] + D16
110 DH SI 110 DIRECT [BP] + D8 [BP] + D16
ADDRESS
111 BH DI 111 [BX] [BX] + D8 [BX] + D16

Example
◆ MOV BL, AL
◆ Opcode MOV = 100 010
◆ AL – D=0; W bit = 0 (8-bits)
◆ MOD = 11 (Register Mode)
◆ REG = 000 (code for AL)
◆ R/M = 011 (Code for BL)
Opcode D W MOD REG R/M
100 010 0 0 11 000 011
• MOV BL, AL = 10001000 11000011 = 88, C3H

• ADD AX, [SI] = 00000011 00000100 = 03, 04H
• ADD [BX][DI]+1234H, AX = 00000001 10000001 = 01, 81, 43, 12H

8086 based Mirco-computer
System Design

System Design
◆8086 Pin Description
◆Clock Circuit Design
◆De-multiplexing of Address and Data lines
◆Memory Interfacing
◆Parallel Ports Interfacing
◆Serial Communication Interface
◆Keyboard Interface and Display Inteface
◆Interrupt Controller Interface

8086 Pin Diagram
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/ MX
AD7 9 8086 32 RD
AD6 10 CPU 31 HOLD / RQ/GT0
AD5 11 30 HLDA / RQ/GT1
AD4 12 29 WR / LOCK
AD3 13 28 M/ IO / S2
AD2 14 27 DT/ R / S1
AD1 15 26 DEN / S0
AD0 16 25 ALE / QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET

Read and Write Bus Cycle
T1 T2 T3 T4
CLK
ALE
M/ IO
Adress/ S3 - S7
A16-A19, BHE
Status
Float Data in D0 – D15 Float
AD0 – AD15 A0 – A15
RD
DT/ R
DEN
AD0 – AD15 A0 – A15 Data out D0 – D15
WR
DT/ R
DEN
8086 Pin Description
◆MN/MX:
◼ The minimum mode is intended for simple single
processor system on one printed circuit board (PCB)
◼ The maximum mode is intended for more complex
systems with separate I/O and memory boards
◼ This mode also supports coprocessors such as the 8087
NDP and 8089 IOP

◆Data Bus (AD0-AD15)
◼ These 16 pins from the CPU’s bidirectional data bus
◼ These lines are valid only during the T2 through T4 clock
states
◼ During T1 they hold the low 16 bits of the memory or I/O
address
◆Address Bus (AD0-AD15 and A16/S3 – A19/S6)
◼ 20bit address bus, allow the processor to access 220
locations
◼ The output lines are valid only during the T1 state
◆Address Latch Enable (ALE)
◼ Used to demultiplex the address, data, BHE/S7 and status
lines
◼ Every cycle begins with an ALE pulse during the T1 clock
state
◼ 20 bit address is valid when ALE switches from high to low
near the end of T1

◆Memory/IO (M/IO)
◼ Signal is output early in the T1 state
◆Read (RD)
◼ This is active low signal indicates that the direction of data
flow on the bus is from memory or I/O into the processor
◼ It output during T2 state and removed during the T4 state
◼ MEMR and IOR
◆Write (WR)
◼ Active low signal indicates that the direction of the data
flow on the bus is from Processor to Memory or I/O
◼ It output during T2 state and removed during the T4 state
◼ MEMW and IOW

Generating Memory & I/O Signals
RD
IOR
MEMR
M/ IO
MEMW
IOW
WR

◆ Clock (CLK)
◼ All the events in the microprocessor are synchronized to the system
clock applied to the CLK pin
◼ 8086 (5MHz), 8086-2 (8MHz) and 8086-1 (10MHz)
◆ Status (A16/S3 – A19/S6 and BHE/S7)
◼ These five signals outputs during T2-T4.
◼ They are intended primarily for diagnostic testing purposes
◆ Bus High Enable (BHE/S7)
◼ It is output only during the T1 state.
◼ When BHE=0, it indicates that AD8-AD15 are involved in data transfer
◼ This can occur for memory or I/O word higher byte access from an odd
address
◼ BHE and A0 are used for selection of even or odd memory banks or
I/O ports

BHE A0 Action
0 0 Access 16 bit word
0 1 Access odd byte to D8-D15
1 0 Access even byte to D0-D7
1 1 none
◆ Data transmit/ receive (DT/ R)

◼ Intended for direction of data flow on the data bus
◼ Low – Read operation, High – write operation
◆ Data Enable (DEN)
◼ This signal is intended to used with DT/ R to enable a set of
bidirectional buffers connected to the system data bus.
◆ RESET
◼ High – causes the 8086 to terminate its present activity and perform a
reset sequence
◆ Interrupts (INTR, NMI, and INTA)
◼ INTR and NMI are hardware Initiated interrupt requests
◼ The INTR input can be masked by resetting the IF processor status bit
(CLI)
◼ NMI is non-maskable interrupt that will always be serviced
◼ NMI is active – control automatically transfers to the address stored in
locations 00008-0000BH
◆ HOLD and HLDA
◼ HOLD active high – causes the processor to open circuit all of its bus
lines
◼ This effectively disconnect the CPU from its memory and I/O
◆ Power and ground (Vcc and GND)
◼ The 8086 requires a single +5V power and has two ground pins

Clock Circuit Design
◆Designed using 8484A Clock generator

Clock and Reset Interface to 8086
X1
Fc = 24MHz CLK
X2 To 8086
CLK Input
EFI
F/ C PCLK To 8086
Peripherals
CSYNC
8284A
+5V
100 KΩ RESET To 8086

RESET Input
RES
+
10 μF
-
Power on reset active time of 50 us

Bus Buffering and De-multiplexing
◆The address, data and control line from the
microprocessor need to be buffered to prepare them
to be connected to many components in the system
◆The 8086 has multiplexed address, data and status
signals
◼ AD15 – AD0 and A19/S6 – A16/S3 lines
◆Buffers and latches are used for buffering and
demultiplexing the address and data bus signals
◆Buffers: provide amplified current or power output
to drive address and data buses in the
microprocessor based systems

Bus Buffering and Demultiplexing
◆Uni-directional octal buffer: allows transmission of 8-
bit data in one direction. (74LS244)
◆Bidirectional octal buffer: allows transmission of 8-
bit data in either direction. (74LS245)
◆Octal Latch: has 8 D-latches and 8 – tristate buffers.

74LS244 Octal Buffer
1A1 1Y1
1A2 1Y2 INPUTS OUTPUTS
1A3 1Y3 1G, 2G A Y
L L L
1A4 1Y4
L H H
1G
H X Z
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4
2G

74LS244 Octal Buffer

74LS245 Octal Bus Transceiver
A1
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
A8 B7
B8
INPUTS
OUTPUT
E’ DIR
L L Bus B Data to Bus A
L H Bus A Data to Bus B
H X Isolation
DIR E

74LS245 Octal Bus Transceiver

74373 Octal Latch
D0 Q0
D Q
D1 CLK Q1
D C OC Q
D2 Q2
H H L H
D3 Q3 L H L L
X L L Q0
D4 Q4
X X H Z
D5 Q5
D6 Q6
D7 Q7
C OC

74373 Octal Latch

◆8086’s ALE signal is used to demultiplex the address
and data lines (AD0 – AD15) using 74373
◼ ALE of 8086 is connected to C input of the 74373
◼ OC signal is permanently grounded
◆8086 Control lines for bus buffering
◼ Output data Transmit/receive – DT/ R (Data Bus)
◼ Connected to pin DIR of the 74245
◼ DEN – signal enables the output of the buffer

◼ Connected to pin E of the 74245
◆8086 M/IO, WR and RD are buffered using 74244

◼ Pins of 1G of the 74244 is permanently connected to
ground
D15
U1
74245
DIR E D8
DT/R Data Bus
DEN
D7 D0- D15
U2
74245
DIR E D0
BHE/S7 BHE
8 A19
U3
74373 A19
A16 c oc A16
0
AD15 A15
U4
8 74373 Address Bus
AD8 c oc A8 A0- A19
6 AD7 A7
U5
74373
AD0 c oc A0
ALE
M/ IO IOR
M/ IO U6 Memory & IO
IOW
WR 74244 WR Read & Write
Signal MEMR
RD RD
1A Generation MEMW

Memory Interfacing
◆ Specifications
◼ EPROM
◼ 64KB of EPROM design using IC 27128 (16KB)
◼ RAM
◼ 256KB of RAM using IC 62256 (32KB) FFFFF
EPROM
F0000
3FFFF
Memory Mapping for 8086
RAM
00000

EPROM Memory Chip
Last address
PROM Type Size — Bits Size — bytes Length (hex)
(hex)
2704 4 Kbit 512 200 001FF
2708 8 Kbit 1 KB 400 003FF
2716, 27C16 16 Kbit 2 KB 800 007FF
2732, 27C32 32 Kbit 4 KB 1000 00FFF
2764, 27C64 64 Kbit 8 KB 2000 01FFF
27128, 27C128 128 Kbit 16 KB 4000 03FFF
27256, 27C256 256 Kbit 32 KB 8000 07FFF
27512, 27C512 512 Kbit 64 KB 10000 0FFFF

64KB EPROM Design Using 27128
Device 8086
A19 – A16 A15 – A12 A11 – A8 A7 – A4 A3 – A0 Size Device
Address Address
F0000H
1111 0000 0000 0000 0000 0000H 16KB
F0002H
.. .. .. .. ..
….
1111 0011 1111 1111 1111 3FFFH EVEN Chip0 F7FFEH
&
Chip1 F0001H
1111 0100 0000 0000 0000 0000H 16KB
F0003H
.. .. .. .. ..
….
1111 0111 1111 1111 1111 3FFFH ODD
F7FFFH
F8000H
1111 1000 0000 0000 0000 0000H 16KB
F8002H
.. .. .. .. ..
….
1111 1011 1111 1111 1111 3FFFH EVEN
Chip2 & FFFFEH
Chip3 F8001H
1111 1100 0000 0000 0000 0000H 16KB
F8003H
.. .. .. .. ..
….
1111 1111 1111 1111 1111 3FFFH ODD
FFFFFH
64KB

64KB EPROM Design Using 27128
MEMR
A0
A14-A1 A13-A0 D7-D0 D7-D0
A19
A18 0C Chip 0 EVEN
A17 CS
A16 A14-A1 A13-A0 D15-D8
D7-D0
0C Chip 1
A15 ODD
CS
BHE
A14-A1 A13-A0 D7-D0 D7-D0
0C Chip 2 EVEN
CS
A14-A1 A13-A0 D7-D0 D15-D8
0C Chip 3
ODD
CS

74138 Decoder/Demultiplexer



8255 Programmable Peripheral Interface

8255 Pin Decription
Symbol Type Description
Vcc Pow +5 V power supply
GND Pow Ground
D0-D7 I/O Data Bus
RESET Input RESET: A high on this input clears the control register and all ports (A,
B, C) are set to the input mode with the “Bus Hold” circuitry turned on.
CS Input Chip Select – Active Low Signal
RD Input Read – Active Low Signal
WR Input Write – Active Low Signal
A0 – A1 Input Address Lines to selects Ports and control word register
PA0 – PA7 I/O Port A – 8 bit input and Output Port
PB0 – PB7 I/O Port B – 8 bit input and Output Port
PC0 – PC7 I/O Port C – 8 bit input and Output Port

8255 Functional Diagram

8255 Basic Operation

8255 Mode Selection
◆There are three basic
modes of operation
than can be selected
by the system
software:
◼ Mode 0 - Basic
Input/Output
◼ Mode 1 - Strobed
Input/Output
◼ Mode 2 -
Bidirectional Bus

8255 Mode Definition

8255 BIT SET/RESET Configuration
◆Any of the eight bits of Port C can be Set or Reset
using a single Output instruction.
◆This feature reduces software requirements in
control-based applications.
◆When Port C is being used as status/control for Port
A or B, these bits can be set or reset by using the Bit
Set/Reset operation just as if they were output
ports.

8255 BIT SET/RESET Configuration

8251 USART
◆The 8251 is a USART (Universal Synchronous
Asynchronous Receiver Transmitter) for serial data
communication.
◆As a peripheral device of a microcomputer system,
the 8251 receives parallel data from the CPU and
transmits serial data after conversion.
◆This device also receives serial data from the outside
and transmits parallel data to the CPU after
conversion.

8251 Block Diagram

8251 Pin Diagram and Pin Description

Pin Description
◆ D 0 to D 7 (l/O terminal): This is bidirectional data bus which
receive control words and transmits data from the CPU and
sends status words and received data to CPU.
◆ RESET (Input terminal): A "High" on this input forces the 8251
into "reset status." The device waits for the writing of "mode
instruction." The min. reset width is six clock inputs during the
operating status of CLK.
◆ CLK (Input terminal): CLK signal is used to generate internal
device timing. CLK signal is independent of RXC or TXC.
However, the frequency of CLK must be greater than 30 times
the RXC and TXC at Synchronous mode and Asynchronous
"x1" mode, and must be greater than 5 times at
Asynchronous "x16" and "x64" mode.

Pin Description
◆WR (Input terminal): This is the "active low" input
terminal which receives a signal for writing transmit
data and control words from the CPU into the 8251.
◆RD (Input terminal): This is the "active low" input
terminal which receives a signal for reading receive
data and status words from the 8251.
◆C/D (Input terminal):This is an input terminal which
receives a signal for selecting data or command
words and status words when the 8251 is accessed
by the CPU. If C/D = low, data will be accessed. If C/D
= high, command word or status word will be
accessed.
Pin Description
◆ CS (Input terminal): This is the "active low" input terminal
which selects the 8251 at low level when the CPU accesses.
Note: The device won’t be in "standby status"; only setting CS
= High.
◆ TXD (output terminal): This is an output terminal for
transmitting data from which serial-converted data is sent
out.
◆ TXRDY (output terminal): This is an output terminal which
indicates that the 8251is ready to accept a transmitted data
character.
◼ But the terminal is always at low level if CTS = high or the device was
set in "TX disable status" by a command. Note: TXRDY status word
indicates that transmit data character is receivable, regardless of CTS
or command. If the CPU writes a data character, TXRDY will be reset
by the leading edge or WR signal.
◆ DSR (Input terminal): This is an input port for MODEM
interface. The input status of the terminal can be recognized
by the CPU reading status words.
◆ DTR (Output terminal): This is an output port for MODEM
interface. It is possible to set the status of DTR by a command.
◆ CTS (Input terminal): This is an input terminal for MODEM
interface which is used for controlling a transmit circuit. The
terminal controls data transmission if the device is set in "TX
Enable" status by a command. Data is transmitable if the
terminal is at low level.
◆ RTS (Output terminal): This is an output port for MODEM
interface. It is possible to set the status RTS by a command.

Operation between CPU and 8251
Control Words
There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)

Mode Instruction Asynchronous

Mode Instruction Synchronous

Command Word
◆ Command is used for setting the operation of the 8251.
◆ It is possible to write a command whenever necessary after
writing a mode instruction and sync characters.
◆ Items to be set by command are as follows:
◼ Transmit Enable/Disable
◼ Receive Enable/Disable
◼ DTR, RTS Output of data.
◼ Resetting of error flag.
◼ Sending to break characters
◼ Internal resetting
◼ Hunt mode (synchronous mode)

Bit Configuration of Command Word

Status Word
◆ It is possible to
see the internal
status of the
8251 by
reading a status
word.

8259 Priority Interrupt Controller
◆Eight-Level Priority Controller
◼ The Intel 8259A Programmable Interrupt Controller
handles up to eight vectored priority interrupts for the
CPU.
◆It is cascadable for up to 64 vectored priority
interrupts without additional circuitry
◆The 8259A is designed to minimize the software and
real time overhead in handling multi-level priority
interrupts.
◆Programmable Interrupt Modes
◆Individual Request Mask Capability

8259 Pin Diagram & Description

8259 Functional Diagram

8259 Pin Description Details

Initialization Command Words (lCWs)
◆ Whenever a command is issued with A0 = 0 and D4 = 1, this is
interpreted as Initialization Command Word 1 (lCW1).
◆ lCW1 starts the initialization sequence during which the
following automatically occur:
◼ The edge sense circuit is reset, which means that following
initialization, an interrupt request (IR) input must make a low-to-high
transition to generate an interrupt.
◼ The Interrupt Mask Register is cleared
◼ lR7 input is assigned priority 7.
◼ Special Mask Mode is cleared and Status Read is set to lRR.

ICW1

ICW2 & ICW3

ICW4

Operation Command Words (OCWs)
◆After the Initialization Command Words (lCWs) are
programmed into the 82C59A, the device is ready to
accept interrupt requests at its input lines.
◆However, during the 82C59A operation, a selection
of algorithms can command the 82C59A to operate
in various modes through the Operation Command
Words (OCWs).

OCW2

OCW3

Programmable Keyboard/Display Interface - 8279
◆A0: Selects data (0) or

control/status (1) for reads
and writes between micro
and 8279.
◆BD: Output that blanks the
displays.
◆CLK: Used internally for
timing. Max is 3 MHz
◆CN/ST: Control/strobe,
connected to the control
key on the keyboard.

8279 Interface
◆RL7-RL0: Return lines are inputs used to sense key
depression in the keyboard matrix
◆Shift: Shift connects to Shift key on keyboard
◆SL3-SL0: Scan line outputs scan both the keyboard
and displays
◆DB7-DB0: Consists of bidirectional pins that connect
to data bus on micro.

8086

Micro System Design Assignment
◆ Design Specifications (Use I/O Mapped I/O Interfacing):
◼ 8086 Minimal Mode (8MHz Processor)
◼ Design clock and Reset circuit
◼ Buffer and Demultiplex the data, control and address lines
◼ Design and Interface 512KB EPROM Memory using 27256 Chip
◼ Design and Interface 512KB SRAM Memory using 62256 chip
◼ Interface 6 Parallel ports
◼ Interface one serial port in asynchronous and synchronous serial
communication purpose
◼ Interface 8 hardware priority interrupts
◼ Interface 16 Keys Hex Key board and 8 Seven Segments to Display
(Hint: Use 8279 )
◼ Interface one DMA Controller (Hint: 8257)
◼ Tabulate all the I/O and Memory devices address decoding details as
well as address Mapping
Thank You!!

DDMP Unit 5 Final

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Microprocessors and

1 November 2023 Dr VSMS 1

1 November 2023 Dr. VSMS 2

1 November 2023 Dr. VSMS 3

Bus Interface Unit (BIU)

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Bit Name Function

6 ZF Set if result is zero; cleared otherwise

7 SF Set equal to high-order bit of result (0 is positive, 1 if negative)

1 November 2023 Dr. VSMS 7

◼ All the higher bytes can be stored in even locations

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◆ 8085 – Program instructions, data and subroutine

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7 November 2023 Dr. VSMS 13

MOV SegRegister , Register16 MOV DS, AX ; DS  AX

MOV Memory16, SegRegister MOV MEMWDS, CS ;[1001H:1000H]  CS

MOV Register16, SegRegister MOV DX, ES ; DX  ES

7 November 2023 Dr. VSMS 14

XCHG Register, Register XCHG AX, BX ; AX ↔ BX

Opcode Destination Source Example

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NOT Memory -- NOT [SI] ; [SI]  ~[SI]

AND Destination Source

AND Memory Register AND [SI}, AX

AND Register Memory AND AX, [SI]

AND Register Immediate Data AND BX, 8000H

AND Memory Immediate Data AND [SI], FF00H

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Bit 7/15 Bit 0

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JE/JZ Address Equal/ Zero (ZF = 1)

JP/ JPE Address Parity/ Parity Even (PF = 1)

JNC Address Not Carry (CF = 0)

JNE/JNZ Address Not Equal/ Not Zero (ZF = 0)

JNP/JPO Address Not Parity/ Parity Odd (PF = 0)

7 November 2023 Dr. VSMS 24

PUSH Source PUSH CX ;SP  SP – 2; [SP+1]  CH; [SP]  CL

RET Near Target IP  [SP+1 : SP]; SP  SP + 2

7 November 2023 Dr. VSMS 25

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◼ 0: Data flow from the REG to the R/M

◼ Data Size Bit (W bit)

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MOD = 11 Effective Address Calculation

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• MOV BL, AL = 10001000 11000011 = 88, C3H

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