ANALOG DEVICES Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators ADCMP572/ADCMP573 FEATURES 3.3/5.2 Vsingle-supply operation 150 ps propagation delay 1S ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth £80 ps minimum pulse width 35 ps typical output rise/fall 1Ops deterministic jitter (01) 200 fs random jitter (RU) (On-chip terminations at both input pins Robust inputs with no output phase reversal Resistor-programmable hysteresis Differential latch control Extended industrial -40°C to +125°C temperature range APPLICATIONS Clock and data signal restoration and level shi ‘Automatic test equipment (ATE) \h speed instrumentation Pulse spectroscopy ‘Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry GENERAL DESCRIPTION The ADCMPS72 and ADCMPS73 ae ultrafast comparators fabricated on Analog Devices’ proprietary XECBS Silicon (Germanium (SiGe) bipolar process. The ADCMPS72 features ‘CML output drivers and latch inputs, and the ADCMPS73 features reduced swing PECL (RSPECL) output drivers and latch inputs. oth devices offer 150 ps propagation delay and 80 ps ‘minimum pulse width for 10 Gbps operation with 200 fs ms random jitter (RJ). Overdrive and slew rate dispersion ace typically less than 15 ps A lexible power supply scheme allows both devices to operate witha single 3.3 V positive supply and a -0.2 V to +1.2V input signal range or with split input/output supplies to support a wider -0.2 V to 43.2 V input signal range and an independent range of output levels. 50.0 on-chip termination resistors are Rev.0 rton fuse by Analog Oeics bleed tobe accurate and lb Howerer: ne eqponaity stud by Analog Sees or Wwe orf) Spoctestons subjects change wth note ess ranted by mp rothenise unde any patente patent Hats of Analog Device Traders th ‘rege rademaris af the propery ot herespece ones FUNCTIONAL BLOCK DIAGRAM Voy TERMNATIONO-} =u" °TapoMPsT2 INVERTING gf ADEMPS73| war Yow soomune/t owe provided at both inputs with the optional capability to be left ‘open (on an individual pin basis) for applications requiring high impedance inputs The CML output stage is designed to directly drive 400 mV into 50 0 transmission lines terminated to between 3.3 Vto 5 ‘The RSPECT ouput stage is designed to drive 400 mV into 50 0 terminated to Veco ~ 2V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided. The ADCMP572 and ADCMPS73 are available in a 16-Lead LECSP package and have been characterized over an extencled industrial temperature range of ~40°C to +125°C Cone Technology Way, P.0.80x 9106, Norwood, MA 02062-9106, U.S.A Yet7813294700 wwe analog.com Fa 7814613113 ©2005 Analog Devices, Inc Allright reserved.ADCMP572/ADCMP573 TABLE OF CONTENTS lectrical Characteristic Absolute Maxim Ratings Thermal Considerations... ESD Caution. Pin Cos ‘Typical Performance Characteristics Application Information Power/Ground Layout and Bypassing. CMLIRSPECI Ourput Stage REVISION HISTORY 4/05—Revision 0: Initial Version iguration and Function Descriptions, 3 UsingyDisabling the Latch Feature. ~ Optimizing High Spoed Performance 5 (Comparator Propagation Delay Dispersion. 5 Comparator Hysteresis _7 “Typical Application Circuits. 9 “Timing information 9 Outline Dimensions... 9 Ordering Guide ev.0|Page 2016 Minimum Input Slew Rate Requirements.ADCMPS72/ADCMP573 ELECTRICAL CHARACTERISTICS Vee = Veco = 33 V, Ts = ~40°C to +125°C, typical at Ty ~ +25°C, unless otherwise noted. Table 1. Parameter Symbel___| Conditions Min Typ Max Unit ‘DC INPUT CHARACTERISTICS Input Voltage Range VW 02 2 v 2 31 v Input Differential Voltage =12 #2 v Input Offset Voltage Vos 50 20 450 mv Offset Voltage Tempco AVouaT 100 wee Input Bias Current bol Open termination “500-2500 A Input Bias Current Tempco 500 nArc Input offeet Current 320 ba Input impedance 50 a Input Resistance, Differential Open termination 50 ko Input Resistance, Common-Mode Open termination 500 ko Active Gain Ay sa B Common-Mode Rejection cere Vou =33V, Ve 6 eB Vor=00Vt0 10V Voa=5.2V, Veco =33V, 6 B Vor=0.0V 103.0 Power Supply Rejection —Vea PSBicc m B Hysteresis Rann ee sl nv, TATCH ENABLE CHARACTERISTICS ‘ADCMPS72 Latch Enable Input Range 28 Vao+02 |v Latch Enable Input Differential 02 04 os, v Latch Setup Time & io ps Latch Hold Time & 5 ps ‘ADCMPS73 Latch Enable Input Range 18 Voro-0.6 | V Latch Enable input Diferential 02 04 05 v Latch Setup Time & 90 ps Latch Hold Time w 100 bs Latch Enable Input Impedance 500 a Latch to Output Delay ‘oy tae 150 ps Latch Minimum Pulse Width ta 100 Ps ‘DC OUTPUT CHARACTERISTICS ‘ADCMPS72 (CML) Output impedance Zou 8 mA leur 50%% Output Swing ps Gbps Deterministic Jitter D Vao = 200 mV, 5 Vins, 10 ps PRES" — 11NRZ, 4 Gbps Voo =200 mi, 5 Vins, 2 ps PRBS*'— 1 NRZ, 10 Gbps MS Random Jitter ny Veo = 200 mV, 5 Vins, 1.25 GHe 02 ps Minimum Pulse Width PW ‘Ato/BPW <5 ps, 200mV OD 100 ps PW ‘Atrc/APW < 10 ps, 200 mV OD 80 ps Rise Time 20/80 35 ps FallTime t 20/80 35 bs POWER SUPPLY Input Supply Voltage Range Veo a1 54 v Output Supply Voltage Range Veco 31 54 v Positive Supply Differential Veo-Veco ~02 423 v ‘ADCMPS72 (CML) Positive Supply Current heat heco | Veo=33 V,Vero= 33 V, 4 2 ma terminate 500 to Vero Veo 5.2, Veco=5.2V, 44 52 terminate $00 t0 Vex Device Power Dissipation Po Veo=33V, Veo=33V, 140 165 mW terminate 500 to Veco Veo= 5.2, Veco= 5.2, 230 265 terminate 500 to Ver ADCMPS73 (RSPECL) Positive Supply Current heat hero | Vea= 33 V,Veco=33V, a 80 ma 50 to Vieo-2V Vea=52V, Veso=52V, 4 0 S00 Veco IV Device Power Dissipation Po Veo=33V, Veco= 33 V, no 160 mW 500 t0Veco-2V Vea 5.2, Veco=5.2V, 146 230 50M toVio-2V "Equivalent input banded assures spl ist rde response and’iscalculted with The following Yori Bhs = O22 eae!) whee Was the 20780 teasition time of quastGaussian signal applied tothe compaatorinput, and tas the fective tanstin ime cigitzed by the comparator ev.0|Page4ot 16ADCMPS72/ADCMP573 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter ‘SUPPLY VOLTAGE Input Supply Voltage (Vco to GND) ‘Output Supply Voltage (Vero to GND) Positive Supply Differential (Wea Voce) INPUT VOLTAGE Input Voltage Differential Input Voltage Input Voltage, Latch Enable HYSTERESIS CONTROL PIN ‘Applied Voltage (HYS to GND) Maximum Input/Output Current ‘OUTPUT CURRENT ‘ADCMPS72 (CML) ADCMPS73 (RSPECL) TEMPERATURE Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and tert quipment and can discharge without detection Although this product Features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high eneray electrostatic discharges. Therefore, proper ESD precautions are recommended to avold performance degradation or loss of functionality Rating ~05Vt0 +60 O5Vt0+60V -05Vt035V 05 V to Vex +05v) ~05Vt0 Ve +05V +05V 05VIoH1SV sma 420mA ~35 mA 40°C 10 125% 150°C =65°C 10 150°C Stress above those listed under Absolute Maximum Ratings may «cause permanent damage to the device. This sa stress rating, only and functional operation ofthe device at these or any other conditions above those indicated inthe operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliailt THERMAL CONSIDERATIONS The ADCMPS72/ADCMPS73 LFCSP 16-lead package has a (unction-to-ambient thermal resistance) of 70°C/W instil air. Rev.0|PageSof 16ADCMP572/ADCMP573 veo vce vw] ApoMest2 [50 & apewpsrs [9 “E] toewew vu] [Dveeo eee Figute 2. ADCMPS72/AOCMPS72 Pn Configuration Table 3. Pin Function Descriptions Pino. | Mnemonic __| Description 1 Vir Teemination Resistor Return Pn forVlnput 2 w Noninverting Analog Input 3 vu Inverting Analog Input. 4 Yow Termination Resistor Return Pi for Vi Input 5.16 Veo Positive Supply Voltage for Input Stage. 6 rE Latch Enable Input Pin, Inverting Side. compare mode (LE = low) the output tracks changes at the input of the comparator. Inlatch mode (CE = high. the output refiecs the input stat just prio to the comparator’ being placed into latch mode. LE must be driven in complement with LE 7 ita Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input ofthe comparator. Inlatch mode LE low) the output reflect the input state just prior ta the comparators being placed into latch mode. LE must be driven in compliment with LE 8 Vesa ‘eemination Return Pin forthe LEE Input Pins. Forthe ADCMPS72 (CML output stag), ths pin isinternally connected to and aso should be externally connected tothe postive Veo supply For the ADCMPS73 (RSPECL output stage, this pin should normally be connected to the Veco 2V termination potential. 9.12 Veco Positive Supply Voltage for the CMUIRSPECL Output Stage. 13,15 rr) Ground. _ 10 a Inventing Output. Gis at logic low ifthe analog voltage atthe noninverting input, Vi greater than the analog voltage at the inverting input, Va, provided the comparator isin compare mode. See the LEME descriptions (Pins 6 and 7 for more information. " a Noninverting Output. Qs at logic high ifthe analog votage at the noninverting input Vois greater than the analog votage atthe inverting input, Vx. Provided the comparator isin compare mode. See {he LELE descriptions (Pins 6 and 7 for more information 4 Ys Hysteresis Control Pin, Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably sized resistor to add the desired amount of hysteresis. Rafer Figure / for proper sing of RyrshySteresis contol resistor. Isolated | NIC The metallic back surface ofthe package is not electrically connected to any part ofthe circuit anit Heat sink + Bove) Figure 20 Hysteresis us Ri Conta Resistor ‘MINIMUM INPUT SLEW RATE REQUIREMENTS. As with all high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not ‘oscillate asthe input signal crosses the threshold, This ‘oscillation is due in part tothe high input bandwidth of the ‘comparator and the feedback parasitics inherent in the package. A minimum slew rate of 50 Vis should ensure clean output transitions from the ADCMP572/ ADCMPS73 comparators, “The slew rate may be too slow for other reasons. The extremely high bandwidth ofthese devices means that broadband noise can bea significant factor when input slew rates are low. There will be at least 120 wv of thermal noise generated over the full comparator bandwidth by two 50 0. terminations at room temperature. With a slew rate of only 50 V/us the input wil be inside this noise band for over 2 ps, rendering the comparator’ jitter performance of 200 fs moot. Raising the slew rate ofthe input signal andor reducing the bandwidth over which this resistance is seen at the input can greatly reduce jitter. Rev.0|Page 11 of 16ADCMP572/ADCMP573 TYPICAL APPLICATION CIRCUITS veo ld tf. Figure 2, Zero-Crossng Detects with 4.3 VCAML Outputs “ R } m Figure 2. 1VDS to 500 Back TesminatedRSPECL Receiver Meo35 Fue 23.Comportor wth Vinput Range ond 25 Vor 23 VCML Outputs ; saok Foon vs e ara : gure 24. Comparator wth OV to 3V nut Range and 33V0r52 V sive CL Ouputs ev.0| Page 12016 Necoe3.v _3y r [ADcwPsi *tee “te gure 2. ntetacing 13VCML 04 800 ‘Ground Terminated strument Figure 27. Disabling the ADCIPS73 Lath Feature xs Mesa } song $500 ST Jaoomests Figure 28 Adding Hysteresis Using the HYS Control PinADCMPS72/ADCMP573 TIMING INFORMATION Figure 29 illustrates the ADCMPS72/ADCMPS73 compare and latch timing relationships. Table 4 provides definitions of the terms shown in the figuee. (areHrENAELE ‘Bourur ‘Table 4. Timing Descriptions Figure 28 Syste Ting Diagram Symbol | Timing Description ‘wai | Input to output high delay Propagation delay measured from the time the input signal crosses the reference = the Input offset voltage) to the 50% point of an output low-to-high transition. twa | Input to output low delay Propagation delay measured from the time the inpurt signal crosses the reference (the input offset voltage) tothe 50% point of an output high-te-low transition. tra: | Latch enableto output high delay | Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition tna | Latch enable to output low delay | Propagation delay measured from the 50% point ofthe latch enable signal low-to-high transition to the 50% point of an output high-to-low transition, tw Minimum hold time [Minimum time after the negative transition ofthe latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs, tre Minimum latch enable pulse width | Minimum time thatthe latch enable signal must be high to acquire an input signal change, & Minimum setup time Minimum time before the negative transition ofthe latch enable signal that an input signal change must be present to be acquired and held at the outputs. t Output rise time ‘Amount of time required to transition from a low toa high output as measured at the 20% and 80% points. c Output fall time ‘Amount of time required to transition from a high toa low output as measured at the: 20% and 80% points. Yoo | Voltage overdrive Difference between the input voltages Va and Vi. Rew.0|Page 13016ADCMP572/ADCMP573 OUTLINE DIMENSIONS stm PIN 1 INDICATOR pus “ws rue twovcaron tt ms ae t ve aX azouax 180 REF} $a SEATING. ae oreNoM et "RUE HEN SES ANB =O sree ORDERING GUIDE ev.0| Page 14 16ADCMPS72/ADCMP573 NOTES Rew.0|Page 15016ADCMP572/ADCMP573 NOTES © 2005 Analog Devkes Ic. Abts reserved Tademars and Tegsteed wacearks are the Boparty of thelr respective owners. Go ANALOG DEVICES ev.0| Page 16 6 www.analog.com