Slla 471 B

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Application Note
Multiplexers and Signal Switches Glossary
ABSTRACT
Table of Contents
1. Introduction to Multiplexers and Signal Switches 2. Operation of Multiplexers and Signal Switches
• Signal switch • Absolute maximum ratings
• Multiplexer (Mux) • Recommended operating conditions
• Analog switches and multiplexers • Single power supply
• Protocol-specific switches and multiplexers • Dual power supply
• Precision • Switch control signal levels (VIH, VIL)
• Protection • Rail-to-rail
• Low voltage • Input/Output voltage beyond supply
• Mid voltage • Bidirectional signal path
• Configuration
• Channel
3. Additional Features 4. DC Characteristics

• 1.8-V control logic • On-resistance (RON)
• Fail-safe logic • On-resistance flatness (RON FLAT)
• Injection current control • On-Resistance Mismatch between channels (ΔRON)
• Integrated pulldown resistor on logic pin • OFF leakage current (ID(OFF), IS(OFF))
• Latch-up immunity • Powered-off I/O pin leakage current (IPOFF)
• Overvoltage protection • ON leakage current (ID(ON), IS(ON))
• Undervoltage protection • Control input leakage (ISEL or IEN)
• Fault Flag Indicators • Supply Current (IDD or ISS)
• Drain Response Output
• Powered-off protection
5. Dynamic Characteristics 6. Timing Characteristics

• Off capacitance source and drain (COFF) • Transition time (tTRAN)
• On capacitance source and drain (CON) • Device turn on time from enable pin (tON(EN) and tOFF(EN))
• Charge injection (QC) • Break-before-make time (tOPEN (BBM))
• Off-isolation (OISO) • Make-before-break time (tCLOSED (MBB))
• Channel-to-channel crosstalk (XTALK) • Propagation delay through the switch (tpd)
• Bandwidth (BW) • Output-to-output skew (tSK)
• Insertion Loss • Fault Response Time
• THD + N • Fault Flag Response Time
• Drain Response Enable Time
• Fault Recovery Time
• Fault Flag Recovery Time
SLLA471B – JUNE 2021 – REVISED DECEMBER 2021 Multiplexers and Signal Switches Glossary 1
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About This Multiplexers and Signal Switches Glossary www.ti.com
1 About This Multiplexers and Signal Switches Glossary

This glossary provides a brief overview and introduction to the terminology, features, and parameters for
TI'smultiplexers and signal switches for analog signal chain applications. The entire signal switches and
multiplexers portfolio can be found at www.ti.com/switches.
For components used to manage power rails and for applications that require a switch current of greater
than 500mA, TI offers a power switch and power multiplexer portfolio which can each be found at www.ti.com/
powerswitch.
2 Multiplexers and Signal Switches Glossary SLLA471B – JUNE 2021 – REVISED DECEMBER 2021
www.ti.com Introduction to Multiplexers and Signal Switches
2 Introduction to Multiplexers and Signal Switches
S D
Signal switch — An integrated circuit (IC) used for connecting and disconnecting
an electrical circuit. For more information, see the Switches and muxes: What are
switches & multiplexers? training video from TI Precision Labs.
Figure 2-1. Ideal 1:1 SPST Switch
A0 A1
S1
S2
D
Multiplexer (Mux) — An integrated circuit that connects a selected signal path to a S3
single line.
S4
Figure 2-2. Ideal 4:1 Mux
Analog switches and multiplexers — These devices are used for switching and multiplexing analog and digital signals up to 500 mA in
applications such as:
• Precision Data Acquisition
• GPIO Expansion
• Diagnostics
• System communication
• Bus Isolation
• System Protection
• Power Sequencing
• General-Purpose Signal Switching
Protocol-specific switches and multiplexers — These devices are defined to support specific protocol applications such as USB, HDMI,
LAN, MIPI, audio, memory and so forth.
Precision — These devices minimize offset error and signal distortion in a high-accuracy measurement system.
Protection — These devices isolate I/O signal paths and protect the system using powered-off, overvoltage and undershoot protection.
Low voltage — These devices support I/O signals ≤ ±25 V
Mid voltage — These devices support I/O signals > ±25 V
Configuration — Defines the number of signals that can be selected. Table 2-1 shows the typical configurations.
Channel — Defines the number of configurations (circuits) in a single device. Table 2-1 shows the 1- and 2- channel configurations, but the
number of channels may exceed 2.
Introduction to Multiplexers and Signal Switches www.ti.com
Table 2-1. Configurations and Channels

1-Channel 2-Channel
S1 D1
S D
1:1 S2 D2
2:1 S1 S1A
D D1
S2 S1B
S2A
D2
S2B
S1A
S1B D1
S1
S1C
S2 D
3:1
Configuration S2A
S3
S2B D2
S2C
S1A
S1B
D1
S1
S1C
S2
S1D
D
4:1 S3 S2A
S2B
S4
D2
S2C
S2D
S1A
S1B
S1C
S1D
D1
S1 S1E
S2 S1F
S3 S1G
S4 S1H
D
Configuration 8:1 S5 S2A
S6 S2B
S7 S2C
S8 S2D
D2
S2E
S2F
S2G
S2H
www.ti.com Introduction to Multiplexers and Signal Switches
Table 2-1. Configurations and Channels (continued)

1-Channel 2-Channel
S1
S2
S3
S4
S5
S6
S7
S8
D
Configuration 16:1 N/A
S9
S10
S11
S12
S13
S14
S15
S16
Operation of Multiplexers and Signal Switches www.ti.com
3 Operation of Multiplexers and Signal Switches

Absolute maximum ratings — These are stress ratings only, which do not imply functional operation of the device at these or any other
conditions beyond those indicated under the Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. Stresses beyond those listed under the Absolute Maximum Rating may cause permanent
damage to the device.
Recommended operating conditions — The operating conditions for which the device has been characterized.
Single Dual
Supply: Supply:
VDD (+V)
Single power supply — Device with only positive power supply pins with
reference to ground. The voltage applied is labeled as VDD, VCC, V+ and so
forth. GND
Dual power supply — Device with positive and negative supply pins with
reference to ground. Voltage applied at the positive pin is labeled as VDD, VCC,
V+, and so forth, and at the negative pin is labeled as VSS, VEE, V-, and so
forth.
VSS (-V)
Figure 3-1. Single and Dual Supply
V DD
Log ic
Switch control signal levels (VIH, VIL) — Voltage levels required on the ³HIG H´
control pins (EN, SEL, IN, and so forth) required for the switch to change the
internal signal path. VIH
• VIH – The minimum voltage for the input control signal to achieve a logic
"1"high value VIL
Log ic
• VIL – The maximum voltage for the input control signal to remain a logic
³LOW´
"0"low value GND
Figure 3-2. Switch Control Signal Levels
VDD
VI/O
Rail-to-rail — A common term meaning that a device will support VI/O voltage
range between the most positive and most negative power supply rails.
0V
(GND)
t
Figure 3-3. Rail-to-Rail
VI/O(MAX)
VDD
Input/Output voltage beyond supply – The switch can support voltage range
beyond the supply rail to VI/O(MAX)as indicated by the recommended operating
conditions.
0V
(GND)
t
Figure 3-4. I/O Voltage Beyond Supply
www.ti.com Operation of Multiplexers and Signal Switches
A0 A1
S1
S2
Bidirectional signal path – The switch conducts equally well from source
(S) to drain (D) or from drain (D) to source (S). Each channel has very D
similar characteristics in both directions and supports both analog and digital S3
signals. TI analog switches and multiplexers are typically bidirectional. See the
Switches and muxes: Are switches & multiplexers bidirectional? training video S4
from TI Precision Labs.
Figure 3-5. Bidirectional Signal Path
Additional Features www.ti.com
4 Additional Features
1.8-V Control Logic – Switches with this feature have a built-in voltage translator to prevent voltage mismatch between the supply rail and
the control logic. VIH and VIL levels are compatible with the 1.8-V logic levels at any voltage supply. See the Simplifying Design With 1.8 V
logic MUXes and Switches Tech Note for more information.
VDD = 0 V
VCC = 5 V VDD
Protection
VSEL
Fail-Safe Logic – Ensures the switch stays off and 0V

the voltage on the logic pin (VSEL) does not back-
Subsystem SEL
power VDD when VSEL is greater than VDD. See the A
Switches and muxes: What is fail-safe logic? training
Subsystem
video from TI Precision Labs. B
S High-Z D
Figure 4-1. Fail-Safe Logic
S1 D
Injection Current Control — Devices with Injection
Current Control shunt injected current on disabled Control
(high-Z) signal pathways to ground. This mitigates Circuitry
error on the active signal pathway as the injected
current is going into the ground rail and not the S2
power rail. See the Switches and muxes: Prevent
crosstalk with injection current control training video Control
from TI Precision Labs. + Circuitry
±
Figure 4-2. Injection Current Control
VDD
S D
EN
Integrated Pulldown Resistor on Logic Pin –
Internal weak pulldown resistors to GND to ensure
the logic pins are not floating.
GND
Figure 4-3. Integrated Pulldown Resistor on Logic Pin
www.ti.com Additional Features
NMOS PMOS VDD
Gate Gate
Latch-Up Immunity – Devices that are latch-up GND

immune can use various methods to achieve latch up
immunity such as being built in a Silicon On Insulator
Trench Oxide
Trench Oxide
Trench Oxide
(SOI) process, employing the use of guard rings, p+ n+ n+ p+ p+ n+
or a mix between different methods. When these
measures are taken Electrical Overstress, Electrically p-epi n-well
Fast Transients, and Injected Currents will not cause
latch up in these devices. See the Switches and
muxes: What is latch-up immunity? training video Buried Oxide Layer (Insulator)
from TI Precision Labs.
Substrate (p) / Handle
Figure 4-4. Latch-Up Immunity With SOI Process
Supply (VDD) Supply (VFP)

FIXED Threshold Threshold Threshold
VI/O(MAX) VI/O(MAX) VI/O(MAX)
Switch Switch Switch

“OFF” “OFF” “OFF”
Overvoltage Protection – When the input voltage
VI/O exceeds the defined threshold voltage, VTH
or VT, the switch enters the high impedance
VI/O VI/O
state, isolates signal path, and protects downstream VI/O
components. Depending on device the threshold can VTH VOFF

VT
VOFF
VT
VDD VFP
determined in 1 of 3 ways.
• Fixed Threshold
• Threshold = Supply Switch Switch Switch
“ON” “ON” “ON”
• Threshold = Configurable
VI/O(MIN) VI/O(MIN) VI/O(MIN)
Figure 4-5. Overvoltage Protection
Supply (VSS) Supply (VFN)

Undervoltage Protection – When the input voltage VI/O(MAX)
Threshold Threshold
VI/O falls below the defined threshold voltage, VTH, Switch

“ON”
Switch
“ON”
the switch enters the high impedance state, isolates

signal path, and protects downstream components. VSS VI/O
VFN VI/O
Depending on device the threshold can determined VOFF VT VOFF VT
in 1 of 2 ways.
VSS
• Threshold = Supply
Switch Switch
• Threshold = Configurable VI/O(MIN)

“OFF” “OFF”
This feature typically exists alongside Overvoltage

Figure 4-6. Undervoltage Protection
Protection
VDD
1k
Switch
Fault Flag Indicators – On some devices there is FLAG MCU / ASIC
a fault flag pin that will change states (typically from
high to low) when a fault is present on the device
and will return to its default state when the fault is +
-
cleared.
Figure 4-7. Fault Flag Indicators
Additional Features www.ti.com
VDD VFP VDD VFP
40k
FAULT FAULT
Drain Response Output – On some protection

DR = Low DR = Float or High
switches/multiplexers the output response of a Vs Z Vs Z
DR DR
Open Circuit When Fault Clamp to Fault Supply
device during a fault condition can be set to either Occurs (VFP if OV, VFN if UV)
clamp to supply or open circuit the output.

VSS VFN VSS VFN
Figure 4-8. Drain Response Output
VDD = 0 V
VDD
Powered-Off Protection – Protects switch and VCC = 5 V

isolates signal path when signals are present at the Pro tection
I/O pins and VDD = 0 V. See the Switches and SEL
muxes: Simplify power sequencing with powered-off VS
protection training video from TI Precision Labsand Sub system 0 V IS Sub system
the Eliminate Power Sequencing With Powered-off A S High-Z D B
Protection Signal Switches Tech Note for more
information.
Figure 4-9. Powered-Off Protection
www.ti.com DC Characteristics
5 DC Characteristics
For more parameter information, see the device data sheet.
VDD
RON
S1 D1
On-Resistance (RON) — The resistance of the switch pathway when the
switch pathway is closed (low impedance). The resistance varies with +
VS RL
temperature, supply voltage, and input voltage with respect to ground. ± Switch ON
Figure 5-1. On-Resistance
RON FLAT ( )
Flatness
On-Resistance Flatness (RON FLAT) — Difference between the maximum

and minimum value of Ron in a channel over the VD or VS voltage range
(w.r.t. ground).
VD or VS (V)
Figure 5-2. On-Resistance Flatness
VDD
S D
R_ON1
Vs
On-Resistance Match Between Two Channels (ΔRON ) – Difference S D
between On-Resistance of two different switch pathways at the same input R_ON2
voltage VS
Channel Mismatch : [R_ON1 – R_ON2]
Figure 5-3. ΔRON
VDD
S1 S D D1
Hi-Z
OFF leakage current (ID(OFF), IS(OFF)) — Leakage current measured at the + ID(OFF)
input port, with the corresponding channel output in the OFF state under VS RL
±
worst-case input and output conditions.
Switch OFF
Figure 5-4. OFF Leakage Current
DC Characteristics www.ti.com
0V
Protection
IPOFF
S1 S Hi-Z D D1
Powered-off I/O pin leakage current (IPOFF) — The leakage current flowing +
into or out of the source pin when the device is powered off (VDD = 0V). VS RL
±
Switch OFF
Figure 5-5. Powered-Off I/O Pin Leakage

Current
VDD
IS ID
S1 S D1
ON D
+ ID(ON)
ON leakage current (ID(ON), IS(ON)) — Leakage current measured at the input VS RL
or
port in the ON state, with the corresponding output port in the ON state and ±
IS(ON)
the output being open.
Switch ON
IS • ,D
Figure 5-6. ON Leakage Current
VDD
S1 S Hi-Z D D1
Control input leakage (ISEL or IEN) — Leakage measured at the switch EN

control pins. VSEL ISEL
or or
IEN
VEN
Switch OFF
Figure 5-7. Control Input Leakage
IDD VDD
Switch/Multiplexer
Supply Current (IDD or ISS) – The supply current is the amount of current
that is sourced from/sunk into the supply pins. IDD refers to current into the
VDD pin and ISS refers to current into the VSS pin.
ISS
VSS
Figure 5-8. Supply Current
www.ti.com Dynamic Characteristics
6 Dynamic Characteristics
For detailed information of dynamic characteristics, see the Multiplexers: Bandwidth, Channel-to-Channel
Crosstalk, Off-Isolation and THD+Noise training video from TI Precision Labs.
VDD
S1 S Hi-Z D D1
COFF
Off capacitance source and drain (COFF) — The capacitive loading
when a switch path is in the high-impedance state. VS RL
Switch OFF
Figure 6-1. Source and Drain Off Capacitance
VDD
S1 S D D1
SWITCH “ON”
Vs RL
On capacitance source and drain (CON) — The capacitive loading when CON/2 CON/2
a switch path is in the low-impedance state.
Figure 6-2. Source and Drain On Capacitance
Charge injection (QC) — Charge injection is a measurement of unwanted

signal coupling from the control (EN) input to the analog output. This is
measured in coulomb (C) and measured by the total charge induced due
to switching of the control input.
Figure 6-3. Charge Injection
Dynamic Characteristics www.ti.com
VDD
VS1
VD1
S1 S D D1
Hi-Z
Off-isolation (OISO) — A measurement OFF-state switch impedance. This
is the ratio of VD1 to VS1 measured in dB at a specific frequency, with the VS RL
corresponding channel in the OFF state. Switch OFF
Figure 6-4. Off-Isolation
VDD
VS1
S1 S ON D D1
+
VS1 RL
±
Channel-to-channel crosstalk (XTALK) — A measurement of unwanted

signal coupling from an ON channel to an OFF channel. This is the ratio of VS2
S2 S Hi-Z D D2
VS2 to VS1 measured in dB at a specific frequency.
+
VS2 RL
±
XTALK =
Figure 6-5. Channel-to-Channel Crosstalk

Magnitude (dB)
í3 dB
Ban dwidth
Bandwidth (BW) — The frequency range of signals that can pass through
the switch with no more than 3 dB of attenuation from the DC gain ( 0 Hz).
Freque ncy (Hz)
Figure 6-6. Bandwidth
VS VOut
Insertion Loss - The loss through the switch with predefined load across Rs Switch ON RL CL
Vin
frequency. Since the switch is more than just a resistor when closed there
is frequency dependent loss associated with the switch - this is defined by
Inseron Loss IL = 20log(VOut/Vs)
Insertion Loss
Figure 6-7. Insertion Loss
www.ti.com Dynamic Characteristics
VDD VSS
0.1 µF 0.1 µF
VDD VSS
Audio Precision
Total Harmonic Distortion + Noise (THD+N) - S1
Also called Sine Wave Distortion – this parameter looks at the harmonic
40 Ÿ
content introduced by the switch and is defined by summing all non- D
VOUT
fundamental harmonics RMS amplitudes + the noise floor and dividing VS RL Other
it by the RMS amplitude of the fundamental frequency. This parameter is Sx pins
50Ÿ GND
commonly expressed as a percentage.
Figure 6-8. THD + N
Timing Characteristics www.ti.com
7 Timing Characteristics
For detailed information, see the Switches and muxes: What are timing characteristics? training video from TI
Precision Labs.
VDD
S1 S D D1
ON
+
VS RL
±
SEL
VSEL Switch ON
Transition time (tTRAN) — The time taken by the switch output to rise or fall
within a given percentage of the final value after the address signal has risen
or fallen past the logic threshold. VDD
VIH
VSEL
VIL
0V
tTRAN
VS
90%
VD1
10%
0V
Figure 7-1. Transition Time
VDD
S1 S ON D D1
+ EN
VS RL
±
Switch ON
VEN
Device turn on time from enable pin

(t ON(EN) and t OFF(EN) ) — The time taken by the switch output to rise or fall VDD
VIH
within a given percentage of the final value after the enable has risen or fallen VEN
past the logic threshold. VIL
0V
tON (EN) tOFF (EN)
VS
90% 90%
VD1
0V
Figure 7-2. Device Turn on Time From Enable

Pin
www.ti.com Timing Characteristics
VDD
S1A S D D1
+ RL CL
VS
±
S1B S D
SEL
VSEL
Break-before-make time (tOPEN (BBM)) — Ensures that in a multiplexer, two
multiplexer paths are never electrically connected when the signal path is
changed by the select input.
VDD
VSEL
0V
VS
90%
VD1
tBBM1 tBBM2
0V
tOPEN (BBM) = min ( tBBM1, tBBM2)
Figure 7-3. Break-Before-Make Time
VDD
S1 S D D1A
+ RL CL
VS
±
S D D 1B
SEL
RL CL
VSEL
Make-before-break time (tCLOSED (MBB)) — Ensures that in a multiplexer, two

multiplexer paths are never electrically disconnected when the signal path is
changed by the select input. VDD
VSEL VIH
0V
VS
90%
VD1A
0V
VS
90%
VD1B
0V
tCL OS ED (MBB)
Figure 7-4. Make-Before-Break Time
Timing Characteristics www.ti.com
VDD
S1 S ON D D1
+
VS RL
± Switch ON
VS
Propagation delay through the switch (tpd) — The time required for a VS1 50% 50%
signal to pass from the input signal pin to the respective output signal pin. 0V
tPD 1 tPD 2
VS
VD1 50
50%
%
0V
tpd = max ( tPD 1, tPD 2)
Figure 7-5. Propagation Delay Through the

Switch
Figure 7-6. Output-to-Output Skew

VDD
S1 S ON D D1
+
VS RL
±
S2 S ON D D2
Output-to-output skew (tSK) — The maximum difference between the
propagation delays of different outputs due to different internal paths. VS
+
RL
±
Switches ON
VS
VD1 50% 50%
0V
tSK1 tSK2
VS
VD2 50% 50%
0V
tSK = max ( tSK1, tSK2)
VSS VFP
0.1 µF 0.1 µF
0V VDD VFN
GND GND
VFP + 0.5 V
VS VS
VFN - 0.5 V 0.1 µF 0.1 µF
0V VDD VSS VFP VFN
Fault Response Time (tRESPONSE) - Fault response time (tRESPONSE) tRESPONSE (FP)
VFP 0V
tRESPONSE (FN) GND
Sx SW
Dx
GND
Output
measures the delay between the source voltage exceeding the fault supply Output VFP × 0.5 Output
VFN × 0.5 VS All other
source &
voltage (VFP or VFN) by 0.5V and the drain voltage failing to 90% of the fault 0V VFN
GND
drain pins
RL CL
GND GND
supply voltage exceeded. This only applies to Fault Protected Devices.
tRESPONSE = max ( tRESPONSE(FP), tRESPONSE(FN))
GND
GND
Figure 7-7. Fault Response Time
www.ti.com Timing Characteristics
VSS VFP
0.1 µF 0.1 µF
VDD VFN
GND GND
0V
VFP + 0.5 V 0.1 µF 0.1 µF
VS VS VDD VSS VFP VFN
GND GND
Fault Flag Response Time (tRESPONSE(FLAG)) - Fault flag response time

VFN - 0.5 V
0V Sx SW
Dx
tRESPONSE(FLAG)_FP tRESPONSE(FLAG)_FN
(tRESPONSE(FLAG)) measures the delay between the source voltage exceeding 5V 5V VS

RL CL
5V
the fault supply voltage (VFP or VFN) by 0.5 V and the general fault flag (FF)
VFF VFF GND All other
source & RPU
0.5 V 0.5 V drain pins GND GND
0V 0V
pin to go below 10% of its original value. This only applies to devices with an tRESPONSE(FLAG) = max ( tRESPONSE(FLAG)_FP, tRESPONSE(FLAG)_FN)
GND
FF
FF pin. CL_FF
GND
GND
Figure 7-8. Fault Flag Response Time

VSS VFP
0.1 µF 0.1 µF
VDD VFN
GND GND
3V 3V
0.1 µF 0.1 µF
VDR 1.5V VDR 1.5V VDD VSS VFP VFN

GND GND
Fault Drain Enable Time (tRESPONSE(DR)) -tRESPONSE(DR) represents the 0V

Sx SW
Dx
tRESPONSE(DR)_FP tRESPONSE(DR)_FN
delay between the voltage at the DR pin falling from a high to low signal and VFP
VFP x 0.9
0V
VS
RL CL
the output of the drain pin reaching 90% of the fault supplies (VFP or VFN). Output (VD)
0V
Output (VD)
VFN x 0.9
GND
DR
All other
source &
GND GND
tRESPONSE(DR) is a measure of how quickly the internal pull-up engages in VFN
tRESPONSE(DR) = max ( tRESPONSE(DR)_FP, tRESPONSE(DR)_FN)

VDR
drain pins
response to the DR pin. Only on devices with a DR pin. GND

GND
GND
VS > VFP + VT (to measure tRECOVERY(DR)_FP) or

VS < VFN - VT (to measure tRECOVERY(DR)_FN)
Figure 7-9. Fault Drain Enable Time
Fault Recovery Time (tRECOVERY) -

Fault recovery time (tRECOVERY) measures the delay between the source
voltage falling from overvoltage condition to below fault supply voltage (VFP
or VFN) plus 0.5 V and the drain voltage rising from 0V to 50% of the fault
supply voltage exceeded (only on fault protected devices).
Figure 7-10. Fault Recovery Time

VSS VFP
0.1 µF 0.1 µF
VDD VFN
GND GND
0V
0.1 µF 0.1 µF
VFP + 0.5 V VFN - 0.5 V
VDD VSS VFP VFN
VS VS GND GND
Fault Flag Recovery Time (tRECOVERY(FLAG)) – Fault flag recovery time 0V

tRECOVERY(FLAG)_FP
tRECOVERY(FLAG)_FN Sx SW
Dx
(tRECOVERY(FLAG)) measures the delay between the source voltage falling from 5V
3V
5V
3V
VS
RL CL
5V
the overvoltage condition to below the fault supply voltage (VFP or VFN) plus
VFF VFF GND All other
source & RPU
0V 0V drain pins GND GND
0.5 V and the general fault flag (FF) pin to rise above 3 V with 5 V external tRECOVERY(FLAG) = max ( tRECOVERY(FLAG)_FP, tRECOVERY(FLAG)_FN)
GND
FF
pull-up (only on devices with fault flags). CL_FF

GND
GND
Figure 7-11. Fault Flag Recovery Time
Revision History www.ti.com
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2021) to Revision B (November 2021) Page

• Added Undervoltage protection topic..................................................................................................................8
• Added Fault Flag Indicators topic....................................................................................................................... 8
• Added Drain Response Output topic.................................................................................................................. 8
• Added On-Resistance Mismatch between Channels topic............................................................................... 11
• Added Supply Current topic.............................................................................................................................. 11
• Added Insertion Loss topic............................................................................................................................... 13
• Added THD + N topic........................................................................................................................................13
• Added Fault Response Time topic....................................................................................................................16
• Added Fault Flag Response Time topic............................................................................................................16
• Added Drain Response Enable Time topic.......................................................................................................16
• Added Fault Recovery Time topic.....................................................................................................................16
• Added Fault Flag Recovery Time topic.............................................................................................................16
Changes from Revision * (March 2020) to Revision A (June 2021) Page

• Updated the numbering format for tables, figures and cross-references throughout the document...................3
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3. Additional Features 4. DC Characteristics

5. Dynamic Characteristics 6. Timing Characteristics

1 About This Multiplexers and Signal Switches Glossary

2 Introduction to Multiplexers and Signal Switches

Figure 2-2. Ideal 4:1 Mux

Table 2-1. Configurations and Channels

Table 2-1. Configurations and Channels (continued)

3 Operation of Multiplexers and Signal Switches

Figure 3-1. Single and Dual Supply

Figure 3-2. Switch Control Signal Levels

Figure 3-3. Rail-to-Rail

Figure 3-4. I/O Voltage Beyond Supply

Figure 3-5. Bidirectional Signal Path

Fail-Safe Logic – Ensures the switch stays off and 0V

Figure 4-1. Fail-Safe Logic

Figure 4-2. Injection Current Control

Figure 4-3. Integrated Pulldown Resistor on Logic Pin

NMOS PMOS VDD

Latch-Up Immunity – Devices that are latch-up GND

Figure 4-4. Latch-Up Immunity With SOI Process

Supply (VDD) Supply (VFP)

Switch Switch Switch

components. Depending on device the threshold can VTH VOFF

Figure 4-5. Overvoltage Protection

Supply (VSS) Supply (VFN)

VI/O falls below the defined threshold voltage, VTH, Switch

the switch enters the high impedance state, isolates

• Threshold = Configurable VI/O(MIN)

This feature typically exists alongside Overvoltage

Figure 4-7. Fault Flag Indicators

VDD VFP VDD VFP

Drain Response Output – On some protection

clamp to supply or open circuit the output.

Figure 4-8. Drain Response Output

Powered-Off Protection – Protects switch and VCC = 5 V

Figure 4-9. Powered-Off Protection

Figure 5-1. On-Resistance

On-Resistance Flatness (RON FLAT) — Difference between the maximum

Figure 5-2. On-Resistance Flatness

On-Resistance Match Between Two Channels (ΔRON ) – Difference S D

Channel Mismatch : [R_ON1 – R_ON2]

Figure 5-3. ΔRON

Figure 5-4. OFF Leakage Current

Figure 5-5. Powered-Off I/O Pin Leakage

Figure 5-6. ON Leakage Current

Control input leakage (ISEL or IEN) — Leakage measured at the switch EN

Figure 5-7. Control Input Leakage

Figure 5-8. Supply Current

Figure 6-1. Source and Drain Off Capacitance

a switch path is in the low-impedance state.

Figure 6-2. Source and Drain On Capacitance

Charge injection (QC) — Charge injection is a measurement of unwanted

Figure 6-3. Charge Injection

Figure 6-4. Off-Isolation

Channel-to-channel crosstalk (XTALK) — A measurement of unwanted

Figure 6-5. Channel-to-Channel Crosstalk

Figure 6-6. Bandwidth

Figure 6-8. THD + N

Figure 7-1. Transition Time

Device turn on time from enable pin

Figure 7-2. Device Turn on Time From Enable