_, 5-DAYS WORKSHOP On RTL2GDSII Using SYNOPSYS Tools. SS Learn how to Transform RTL into GDSII in just 5-days Puneet Mittal FOUNDER & CEO, MENTOR & PASSIONATE TRAINER AT VLSI EXPERT PVT. LTD. ABOUT THE SPEAKER: + 17+ YEARS OF INDUSTRY EXPERIENCE + TRAINED 2000+ CANDIDATES & MENTORED 5000+ CANDIDATES TILL NOW ES centtication after Completion 26) Dedicated Synopsys Tool Access (5+5 Days) eee [2] Help in Campus Interview 324 Delivered by Industry Experts + Basic working and truth table of logic gates, + Excitation and Characteristics tables for D-fip flop multiplexers, adders and subtractors. + Concept of synchronous and asynchronous inputs + Concept of latch and flip flops. + Basics of Verilog HDL REGISTRATION FEES REGISTER NOW Including (18%) GST Tie eLieT Bo) rea yrs OT\E DAY-WISE SCHEDULE Clexpene 31) RTL TO GDSII FLow SESSION 1 - CONCEPTUAL SESSION 2 - CONCEPTUAL + RTL Design Overview + Logic Synthesis Optimization + Logic Synthesis Concepts + Timing Constraints Basics + Floorplan Overview @3®) INPUT FILES AND PDK OVERVIEW Power planning Overview Placement Overview Routing Overview Static Timing Analysis Overview Physical Verification Overview SESSION 1 - CONCEPTUAL SESSION 2 -LaBs + Input Files for different Stages + Basic Linux Comands + Overview of PDK files + RTL Simulation using VCS/Verdi GO) STATIC TIMING ANALYSIS OVERVIEW SESSION 1 - CONCEPTUAL SESSION 2 -LaBS + Static Timing Analysis and Delay concepts + Synthesis of RTL using Design Compiler + Timing Checks and Timing Report overview + Comparison of pre-and post-synthesis simulations. @®)) HANDS-ON SESSION SESSION 1 -vass SESSION 2 -LaBs + Floor planning using ICCIL + Placement using ICCII + Power planning using ICCII + Clock Tree Synthesis using ICCII 309) HANDS-ON SESSION SESSION 1 -LaBs SESSION 2 + Routing using ICCII + Interview questions related to RTL to GDSII flow + Static Timing Analysis using Primetime + Resume Preparation guideline REGISTRATION FEES REGISTER NOW Including (18%) GST