1. Design an FSM that has 1 i/p and 1 o/p.

The o/p becomes 1 and remains 1 when

at least two 0's and two 1's have occurred as i/p's.

2.Design a "%3" FSM that accepts one bit at a time, most significant bit first,
and indicates if the number is divisible by 3.

3. If an FSM is redesigned using a state register with minimum number of bits after
connecting the output of a 3-state FSM to the inputs of an 9-state FSM, what is
the maximum number of bits needed?

4. Design a state-machine to give an output ’1’ when the number of A’s are even
and number of B’s are odd. The input is in the form of a serial-stream
(one-bit per clock cycle). The input s could be of t he type A, B or C. At any
given clock cycle, the output is a ’1’, provided the number of A’s are even and
number of B’s are odd. At any given clock cycle, the out put is a ’0’, if the
above condition is not satisfied.

5. Design a FSM to detect the sequence ‘abca’ when the inputs can be ‘abcd’.

6. Design a finite state machine for a modulo-3 counter when x=0, and
modulo-4 counter when x=1.

7. Design a logic which mimics a infinite width register. It takes input

serially 1 bit at a time. Output is asserted high when this register holds
a value which is divisible by 5.