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Specification Template
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Table of Contents
TABLE OF CONTENTS...........................................................................................................................................3
1 INTRODUCTION...........................................................................................................................................5
1.1 DOCUMENT PURPOSE AND SCOPE...........................................................................................................................................5
1.2 USAGE AND ASSUMPTIONS.................................................................................................................................................... 5
1.3 DEFINITIONS........................................................................................................................................................................5
1.3.1 Cell......................................................................................................................................................................... 5
1.3.2 Component.............................................................................................................................................................6
1.3.3 Part........................................................................................................................................................................ 6
1.3.4 PDB (Parts DataBase).............................................................................................................................................6
1.3.5 Partition................................................................................................................................................................. 6
1.3.6 Pad......................................................................................................................................................................... 6
1.3.7 Hole........................................................................................................................................................................6
1.3.8 Padstack.................................................................................................................................................................6
1.3.9 Pin Mapping...........................................................................................................................................................6
1.3.10 Property.............................................................................................................................................................6
1.3.11 Model................................................................................................................................................................6
1.3.12 Symbol...............................................................................................................................................................7
2 LIBRARY STRUCTURE...................................................................................................................................7
2.1 NAMING CONVENTION FOR PARTITION AND PARTITION SEARCH PATH SCHEMES..............................................................................7
2.1.1 Partition Names.....................................................................................................................................................7
2.1.2 Library Partition Search Path Schemes...................................................................................................................7
2.2 LIBRARY SYMBOL PARTITIONS.................................................................................................................................................8
2.2.1 Symbol Partition Search Path Schemes..................................................................................................................8
2.3 LIBRARY CELL PARTITIONS......................................................................................................................................................9
2.3.1 Cell Partition Search Path Schemes........................................................................................................................9
2.4 LIBRARY PART PARTITIONS.....................................................................................................................................................9
2.4.1 Part Partition Search Path Schemes.....................................................................................................................10
3 COMPONENT PROPERTIES.........................................................................................................................10
3.1 COMPONENT PROPERTIES – ALL CATEGORIES..........................................................................................................................10
3.1 COMPONENT PROPERTIES – RESISTOR...................................................................................................................................10
3.2 COMPONENT PROPERTIES – CAPACITOR.................................................................................................................................10
4 PARTS (PDB)..............................................................................................................................................11
4.1 PART IDENTIFIERS...............................................................................................................................................................11
4.2 PART (PDB) PROPERTIES.....................................................................................................................................................11
5 SYMBOLS..................................................................................................................................................12
5.1 REFERENCES FOR SYMBOL STANDARDS...................................................................................................................................12
5.2 SYMBOL NAMING CONVENTION............................................................................................................................................12
5.3 GENERIC SYMBOL ALTERNATE ROTATED VIEW.........................................................................................................................13
5.4 SYMBOL BODY GRAPHICS....................................................................................................................................................14
5.4.1 Unit Length.......................................................................................................................................................... 14
5.4.2 Grid Setting.......................................................................................................................................................... 15
5.4.3 Symbol Graphics Precision....................................................................................................................................15
5.4.4 Symbol Origin.......................................................................................................................................................15
5.4.5 Object to Object Clearance...................................................................................................................................16
5.4.6 Minimum Body Size..............................................................................................................................................16
5.5 SYMBOL BODY PROPERTIES..................................................................................................................................................17
5.6 SYMBOL PINS.................................................................................................................................................................... 17
5.6.1 Pin Graphics......................................................................................................................................................... 18
5.6.2 Using Explicit Power and Ground Pins (option 1).................................................................................................19
5.6.3 Explicit Bus/Vectored Pins (option 2)....................................................................................................................20
5.6.4 Using Implicit Power and Ground Pins (option 3).................................................................................................21
5.6.5 Pin Naming Standard...........................................................................................................................................22
5.6.6 Pin Name Property...............................................................................................................................................22
5.6.7 Pin Number Property............................................................................................................................................22
5.6.8 Pin Identification Text.......................................................................................................................................... 22
5.6.9 Pin Properties.......................................................................................................................................................23
5.6.10 Pin Property Placement...................................................................................................................................24
6 CELLS.........................................................................................................................................................26
6.1 CELL STANDARD REFERENCES................................................................................................................................................26
6.2 CELL NAMING................................................................................................................................................................... 26
6.2.1 Through Hole Cell Naming Convention.................................................................................................................26
6.2.2 Surface Mount Cell Naming Convention...............................................................................................................28
6.2.3 Generic and Manufacturer-Specific Cells..............................................................................................................29
6.3 CELL CONSTRUCTION RULES.................................................................................................................................................29
6.3.1 Cell Layer Graphic Definitions...............................................................................................................................29
6.3.2 Cell Units of Measurement...................................................................................................................................31
6.3.3 Pin Spacing...........................................................................................................................................................31
6.3.4 Package Orientation............................................................................................................................................ 31
6.3.5 Cell Origin.............................................................................................................................................................32
6.3.6 Assembly Data..................................................................................................................................................... 32
6.3.7 Silkscreen Data.....................................................................................................................................................33
6.3.8 Placement Outline................................................................................................................................................36
6.3.9 Placement Rules...................................................................................................................................................36
6.4 CELL PROPERTIES............................................................................................................................................................... 36
6.4.1 Standard Cell Properties.......................................................................................................................................37
6.4.2 Clearance Types...................................................................................................................................................37
6.4.3 Custom Cell Properties.........................................................................................................................................37
6.4.4 Cell Property Text.................................................................................................................................................37
6.4.5 Cell Pin Text..........................................................................................................................................................38
7 PADSTACKS...............................................................................................................................................38
7.1 PADSTACK NAMING............................................................................................................................................................38
7.2 PADS AND HOLE NAMING....................................................................................................................................................39
7.3 PADSTACK TECHNOLOGIES................................................................................................................................................... 39
7.4 PADSTACK GRAPHICS.......................................................................................................................................................... 40
7.4.1 Padstack Graphics – Through Hole.......................................................................................................................40
7.4.2 Padstack Graphics – SMD.....................................................................................................................................40
1 APPENDIX 1: CENTRAL LIBRARY FILE STRUCTURE.......................................................................................40
The intent of this document is to provide rules and regulations for the creation and maintenance of
the Mentor Graphics Expedition Enterprise ECAD library. Following these rules and regulations
will ensure that all necessary data is associated with their respective objects at the time of creation,
enabling consistent and more efficient use of the design tools.
Companion Documents:
Library Requirements to Support Analysis in the EE Flow - This document describes how to
modify a corporate library and how to create the library infrastructure to support simulation and
analysis.
http://communities.mentor.com/mgcx/docs/DOC-2939
1.3 Definitions
This section defines some of the main terms used in this document. For more definitions refer to the
PCB Glossary for the Expedition Enterprise Flow.
1.3.1 Cell
Two-dimensional graphic component representation used in Expedition PCB. Cells can be of the
following types:
Package – Graphical and physical representation of a manufacturer’s component.
Mechanical – Graphical representations of mechanical objects that may not have a pin
association. These objects can be, but not limited to: mounting sockets, nuts, bolts, card ejectors,
heat sinks, and washers
Drawing – Graphics representations of design documentation and are composed of drawing
objects (e.g. sheet borders, cross sections) and textual notes
Panel – Graphical elements added to a manufacturing panel to aid in the manufacturing process
In general use, component refers to an electrical part. In the context of this document, component
refers to a part number and related properties in a database. This term is used to distinguish the
database entry from the Part (PDB) defined in the Library Manager Part Editor.
1.3.3 Part
Object used in both DxDesigner and Expedition PCB. The part consists of one or more symbols, one
or more cells and the pin mapping relationship between said symbol and cells. Parts are edited using
Part Editor
Parts in Library Manager are commonly referred to as being in the Parts DataBase or PDB for short.
Individual parts are sometimes referred to as “PDBs” or “PDB entries”. PDB entries are edited
using Part Editor.
1.3.5 Partition
Storage construct used in Library Manager to group library elements of a similar type.
1.3.6 Pad
1.3.7 Hole
1.3.8 Padstack
Graphical representation of the physical copper pads, soldermask, solderpaste and/or thermal relief
found in a cell and used on a printed circuit board. Padstacks are referenced by cells to define hole
and pad locations
The relationship between a part’s symbol(s) pin names and cell(s) pin numbers.
1.3.10 Property
A characteristic associated with a library element. Properties are comprised of a name and a value,
for example “Value=10K”.
1.3.11 Model
A functional representation of a device or system that is delivered in object code format, used to
perform design simulation/verification.
2 Library Structure
This section provides an overview of the Central Library structure, the naming conventions
and rules to be followed by the library user when creating library objects such as (but not
limited to): Partitions, Components, Symbols, Cells & Padstack.
The table below provides a high level view of the ECAD Library objects:
Symbols, padstacks, cells and parts define electrical parts
Templates, Reusable Blocks and Models partitions contribute to the design process and are
managed within the Library.
2.1 Naming Convention for Partition and Partition Search Path Schemes
2.1.1 Partition Names
Partition names will be of <case type> case and will use only letters, numbers, and the underbar (‘_’)
character. Partition names are to be as consistent and descriptive as possible without being any
longer than necessary with a maximum of 32 characters.
Note: The names given in this template document serve as examples only.
Example: A symbol partition name for ICs of analog type could be “Analog_IC”.
For information on the purpose and usage of library search path schemes, refer to the Library
Development Process Guide.
Search path scheme names will be of <case type> case and will use only letters, numbers, and the
underbar (‘_’) character.
For information on the purpose and usage of library search path schemes, refer to the Library
Development Process Guide.
The following symbol search path schemes are defined in the library.
For information on the purpose and usage of library search path schemes, refer to the Library
Development Process Guide.
The following cell search path schemes are defined in the library.
For information on the purpose and usage of library search path schemes, refer to the Library
Development Process Guide.
The following part search path schemes are defined in the library.
3 Component Properties
Component properties are stored in the DMS database/Dx DataBook database. All properties except
those specifically required by the software to be stored in the part (PDB) shall be stored at the
component level.
Component properties differ for each category of component as described in the following tables.
Provide a separate heading and table for each component category. Remember that component
database categories do not have to exactly match the part (PDB) partitions. For example, a DMS
database may have multiple levels of hierarchy in the component categories, such as Resistors/Fixed,
Resistors/Variable, and Resistors/Network. Part partitions allow only a single level of hierarchy,
such as Resistors.
Some properties are used strictly to help guide part selection and are not added to the symbol
(annotated) when parts are placed in a schematic. Other properties are annotated to the symbol to
enable certain software functions or to enhance schematic documentation. When annotated to the
symbol, the symbol property name does not have to match the component database property name.
This is illustrated in the examples below.
Part Number and Part Name are required. Part Label is optional.
Part Identifiers
Part Number Company standard part number.
Required to be assigned for every part in the library. Must be unique.
Example: CORPIDNUMBER0100-00’
Part Name General descriptive name of the part.
Required to be assigned for every part in the library, but it does not have to be
unique.
Exanple: 74AC04SC
Part Label Alternate descriptive name of the part
Not required to be assigned for every part in the Library and it does not have to
be unique,
Example: 74AC04_DIP14
The purpose of this standard is to clarify the following reference material, not to replace it.
Provide the character limits defined by the company. Refer to Library Manager Process Guide for
Library Object Name Limits and Legal Character set.
Differing property
placement with Rotate,
Flip & Mirror.
The ANSI/IEEE 91-1984 standard uses “units” to define proportions for symbol graphics. All
standards in this document are based on unit length proportioning. This convention allows this
library specification to remain independent of the actual measured size in English, metric or scale
factor used on the schematic and ensure correct proportions
A unit is best defined by relating it to other common objects and measurements used on every
symbol. For example, a unit is the length between two pins divided by <eight>; in other words, the
minimum distance between two pins is <eight> units.
The standard definition of a unit is 1 unit = 0.025 inches for English or 1 unit = 0.625 mm for metric
environment.
When editing symbols the minimum pin grid must be set correctly and displayed. This provides an
easy way to know that measurements are accurate.
The minimum clearance between the graphic items must be two units (refer to ’Object to object
clearance’ section). The Symbol Editor grid setting must be two units.
A grid unit of <Insert Unit in English or metric> shall be set for all symbol creation.
The library Symbol Editor allows for "High Precision" setting and a "Backward Compatible" setting.
All symbols will use the “High Precision" setting.
Note: The “Backward Compatible” setting is used only if symbols are to be used with older versions
of DxDesigner (the values are rounded by 10 mils).
All symbols must be built with the symbol origin located on the left side of a symbol, on the lowest
pin.
The minimum white space (clearance) between symbol objects graphics and text is two units.
Rectangular shaped symbol body minimum width is 16 units and minimum height is 16 units.
Make sure that the properties listed in the table below correspond to the “annotated to symbol
property” column in the table of component properties.
Note: Text height of four units with 1 unit=0.025 inch, approximately matches the font size of 15
typography points
The table below lists the standard properties that will be built into the symbol as place holders.
All symbol properties will have the following default characteristics unless otherwise specified in
the table below.
Font Type: Fixed
Font Size: 15
Font Color: Automatic
Visibility: Value Visible
Property text shall have no less than two units of vertical white space above and below an adjacent
property, and eight units of horizontal white space between any two properties (see also the Object
to object clearance section).
The pin whisker that extends from a symbol body must follow certain length and positioning
standards. The pin whisker might also contain one or more special symbols to indicate items such as
signal flow, polarity, or a non-logic connection. The following discusses length matching for pin
whiskers, standard whisker lengths, whisker centering, input and output pins, flow arrows and
polarity indicators on pins, special pin types, and pins on the top and bottom of a symbol.
Pin whiskers on discrete components are distinct graphics, and are not subject to any
restrictions or rules other than the pin spacing rule.
Do not place pin whisker symbols on discrete analog symbols
All pin whiskers must be equal in length on any one side of a symbol. The addition of such
objects on a whisker as bi-directional arrows or other special symbols do not affect the whisker
length
Pin whiskers with no special objects must have a minimum length of eight units
Pin whiskers with a bubble are always 16 units in length.
Pin whiskers on one side of a symbol must have the same length, the whiskers might be
different lengths on different sides of a symbol.
Pin whiskers should be centered to an array element
The flow of data on a schematic is from left to right, where input lines shall always be on
the left and output lines shall always be on the right.
All Pins of a symbol are to appear “explicitly” on the symbol body instance. No pins are to
be defined “implicitly” in the Part (PDB).
On large parts this may requires the use of multiple symbols containing signal pins and
power, ground, and no-connect pins. All symbols of the device must be placed to ensure device
is powered.
Place these pins on the side of the symbol, not on the top or bottom of a symbol.
Each individual pin is placed separately as shown below. There shall be no use of bus/vectored pins.
A bus pin is a single pin on a symbol that represents a group of power/ground pin bundled
together and used to minimize symbol size. Bus pins may be utilized on symbols for
power/ground pins.
Each bus pin contains a range of pins, for example, GND[10:1] in the figure below
represents a bus pin, where one pin represents 10 bits (GND[10],…,GND[1]). Engineers would
connect a 10-bit bus to the symbol pin and all 10 bits are connected.
Indicate a bus pin by making the pin graphics bold.
Power, ground, and no-connection (NC) pins may be defined in the Part (PDB) file
(referred to as implicit pins) rather than being explicitly defined on the symbol.
Default net assignments for each supply pin are included in the PDB.
To inform the schematic designer exactly what implicit nets are assigned add a Supply
Rename property to any symbol that has implicit pins defined in the part (PDB). Annotate each
default implicit power / ground net name as defined in the part.
Set the Supply Rename property to visible. The property also appears in the symbol
properties dialog.
In a schematic, the engineer may map the default power/ground nets to different nets by modifying
the Supply Rename property as shown below. For example, the default net “AVDD” is replaced by
net “5V” on the device below.
Use pin naming standards to ensure consistency and simplicity for the design engineer. Each symbol
in the library, regardless of the technology or manufacturer of the part, must follow the same set of
pin naming rules.
The pin naming standards followed by digital symbol pins in the library must be compliant with
ANSI, IEEE, IEC, and ISO design standards.
A pin name property is required for proper operation of the DxDesigner/Expedition flow.
The pin number property specifies the physical cell pin number to which the logic pin is related. A
pin number property is required for proper operation of the DxDesigner/Expedition flow.
Each pin must have a pin number property assigned with the value visible.
Pin number values are not required to be assigned in the symbol because this information is
stored in the part (PDB) definition and annotated to the symbol when packaged.
Librarians may assign pin number values in the symbol as an option. This is beneficial
when importing the pins into the part (PDB) editor as all the pin names/numbers will be
automatically mapped.
If pin name properties are made invisible, annotation text must be placed to identify pin functions.
For example, rather than visibly displaying unique pin names “GND1” & “GND2”, identification
text “GND” may be placed between the two pins
Notice, the True Type fonts work best for the PDF generation: adjust font type and font size
appropriately to fulfill height requirement.
Preferred text height for such pin identification (pin labels) is four units.
Vertically center all pin identification characters to their associated pin whisker. When the
pin identification applies to a group of pin whiskers, vertically center it to the group of pin
whiskers.
Separate the pin identification text from other objects using the minimum values shown in
the table below.
8 units Horizontal distance to any text not associated to the pin identification.
4 units Vertical or diagonal distance to any text not associated to the pin identification.
4 units Any vertical line other than the corresponding pin whisker body junction.
2 units Horizontal distance to the pin whisker body junction or to a corresponding
dynamic input, hysteresis, bit grouping, and so on.
2 units Vertical distance to any horizontal line.
Pin Name, Pin Type and Pin Number are default properties assigned automatically once the pin is
instantiated in the Symbol Editor. Additional custom properties may be added. Every property must
first be specified in the Central Library Property Definition Editor (CentLib.prp file) before it can be
used.
The table below lists the standard properties that will be added to symbol pins.
All symbol properties will have the following default characteristics unless otherwise specified in
the table below.
Font Type: Fixed
FontSize: 15
Font Color: Automatic
Visibility: Value Visible
All pin properties must be placed relative to the graphical pin on the symbol.
All pin properties must be placed at the same vertical and horizontal distance from the
graphical pin.
The justification point for the pin name property is two units above and six units away from
the pin.
The justification point for the Pin Number property is two units above and five units to the
right or left of the pin (depending if the pin is on the left or right side of the symbol body).
The figure below shows the location of the Pin Name (named “Pin Name”) and Pin Number (named
“99”) properties and their justification points (represented by a hollow circle).
Pins located to the left of the symbol have properties placed as follows:
Pin name justification is bottom left
The Pin Name justification point is two units above and six units to the left of the pin.
Pin number justification is bottom right
The pin number justification point is two units above and two units to the right of the
symbol body.
Pins located to the right of the symbol have properties placed as follows:
Pin name is justified bottom right
The pin name justification point is two units above and two units to the right symbol body
Pin number is justified bottom left
Pin number justification point is two units above and five units to the left of the pin.
Library Specification Template - Page 24
Pin Name and Pin Number Placement on Analog and Passive Symbols
Many analog and passive symbols do not have the concept of a pin whisker, and pins might appear
on both the top and bottom of the symbol. The figures below show the special consideration given to
the placement of Pin Name and Pin Number on those symbols.
Cells must be created according to the specifications in the IPC, JEDEC, ANSI, and MIL-STD
standards.
In the following cell naming conventions, the text between curly braces {L|W} represents optional
information, while the text between angle brackets (such as <P|C>) represents a required element of
the name.
Other through-hole cells that do not follow the JEDEC standard package types or do not follow the
JEDEC specified dimensions use the format xxx_yyy where:
xxx is an uppercase string denoting a code for the generic type of part or a specific
manufacturer.
yyy is the manufacturer-specific designator or base part number of the device.
Examples of cells using generic part codes include CONN_RM351_152, FUSE_265, and
RELAY_640.
Examples of cells using codes for a specific manufacturer include MOT_22A01, NS_H08B, and
SANYO_SPA_2040
Cell data shall be entered in inches or millimeters according to the data sheet.
The company standard could specify different pin spacing rules for standard through-hole cells, axial
and radial cells, and surface mount cells (see the examples below).
Refer to component datasheet. When pin spacing is not given use IPC-CM-770B.
For example, follow the requirements listed in IPC-1902/IEC 60097 - Grid Systems for Printed
Circuits where the preferred nominal grid in the layout is 0.5 mm or 0.05 mm.
Pin 1
BGA Packages
The cell origin for all Surface Mount Devices shall be at the center of the device.
The origin of all Plated Through Hole geometries shall be at the center of pin 1.
For all others, the origin shall be at X,Y coordinate value of 0,0.
Assembly data includes the placeholder for Ref Designator and Part Number property and Assembly
Outline (graphic combination of lines, circles, arcs and text).
Define standard line thickness and text setting for assembly items. The following requirements could
apply.
Ref Designator and Part Number shall be placed inside the cell body if possible. If this is
not possible because the cell is too small, place outside the placement outline.
By default, the silkscreen data includes the placeholder for the Ref Designator and Part Number and
silkscreen outline (graphic combination of lines, circles, arcs).
On vertically oriented through hole geometries, the text size is 0.10 inch (or 2.5 mm for
metric-based cells).
On all other through hole and surface mount geometries, the text size is 0.075 inch (or 2.0
mm).
Reference Designator text should always be positioned outside of the component outline.
Text is positioned as follows.
A good design practice is to add anode and cathode markings on the silkscreen layer.
Cathode
Placement outlines shall have a minimum line thickness of 0.01 and a maximum line thickness of 0.1
Use placement outline to specify the cell height and undersize space properties if needed. A cell may
have multiple placement outlines that each can carry a different height and underside space.
Use this section to specify the allowed placement sides and rotations when the cell is placed in
layout. Rules are typically associated with particular types of cells, specified by Package Group or
Clearance Type.
Height and Underside Space differ from most properties in that Expedition specifically looks for
these properties in the cell and in the part (PDB). Placing these properties in DxDatabook/DMS and
annotating them onto the symbols will have no effect on Expedition. Height and Underside Space
may be entered on the cell, in the part, or in both places. If defined in both places, the part properties
override the cell properties. Height and Underside Space are used by Expedition’s DRC and
mechanical interface (IDF) file export functions.
Property Required/Optional
Height
Underside Space
Package Group
Mount Type
Clearance Type is used to further refine package type-to-package type clearance rules in CES.
When first beginning to use Clearance Types in Cell Editor, none will be available in the pick list, so
the name must be typed in. Once entered, each Clearance Type name is available in the pick list for
selection in any cell.
Use custom cell properties to add optional properties to cells such as case to air thermal resistance.
Property Text is a “text placeholder” in the cell which is associated with a specific Part (PDB)
property. When the cell is placed in Expedition the property text is automatically updated with the
property value specific to that part from the parts database.
Pin Text is optionally used to create text to identify a pin on the cell. Such text helps engineers to
relate the physical board to the electrical schematic diagrams or other user-defined labels. Typically
only one type of pin text is used in a cell. For logical pin names, the pin text values are updated
based on the associated symbol when the cell is placed in Expedition. Update the table below per
company standards.
7 Padstacks
This section describes conventions related to padstacks in the Central Library.
For consistency use upper case character set across the library.
Do not use following signs in the names: % (percent) * (asterisk) | (pipe), ? (question mark) < >
(angle brackets) “ (quotation).
Use the Expedition “Generate name from properties” option for pad names and hole names.
Enter company standards below. Values given are just examples. Plane clearance and thermal pads
are used only for negative planes.
Central Library data is stored in a single directory containing several subdirectories and files.