(MA) MOTOROLA ~ SEMICONDUCTORS Ponta e MC6809E 8-BIT MICROPROCESSING UNIT The MCBS09E is a revolutionary high performance 8-bit microprocessor which supports modern programming techniques such as position independ: fence, reentrancy, and modular programming. This third-generation addition to the M6800 Family has major architectural improvements which include additional registers, instructions, and addressing modes. ‘The basic instructions of sny computer are greatly enhanced by the presence of powerful addressing modes, The MOB803E has the most com plete set of addressing modes available on any &-bit microprocessor today. ‘The MCBRODE has hardware and software features which make it an ideal processor for higher level language execution or standard controller applica tions. External clock inputs are provided to allow synchronization with peripherals, systems, or other MPUs, ‘M8800 COMPATIBLE (© Hardware — Interfaces with All M6800 Peripherals © Software — Upward Source Code Compatible Instruction Set and ‘Addressing Modes ARCHITECTURAL FEATURES © Two 16-Bit Index Registers © Two 16-Bit indexable Stack Pointers © Two BBit Accumulators can be Concatenated to Form One 16-Bit Accumulator © Direct Page Register Allows Direct Addressing Throughout Memory HARDWARE FEATURES © External Clock Inputs, E and Q, Allow Synchronization © TSC Input Controis Internal Bus Butters © LIC indicates Opcode Fetch © AVMA Allows Efficient Use of Common Resources in a Multiprocessor System BUSY is Status Line for Multiprocessing Fast Interrupt Request Input Stacks Only Condition Code Regis Program Counter Interrupt Acknowledge Output Allows Vectoring By Devices ‘Sync Acknowledge Output Allows for Synchronization to External Event Single Bus-Cycle RESET Single 6-Volt Supply Operation NM Inhibited After RESET Until After First Load of Stack Pointer Early Address Valid Allows Use With Slower Memories Early Write Data for Dynamic Memories ‘SOFTWARE FEATURES © 10 Addressing Modes + M6800 Upward Compatible Addressing Modes * Direct Addressing Anywhere in Memory Map + Long Relative Branches + Program Counter Relative = True indirect Addressing + Expanded Indexed Addressing 0., 5 8, or 16-Bit Constant Offsets & ‘or 16-Bit Accumulator Offsets ‘Auto-Increment/Decrement by 1 or 2 Improved Stack Manipulation 1464 Instruction with Unique Addressing Modes 8 x 8 Unsigned Multiply Y6-Bit Arithmetic Transter/ Exchange All Registers Push/Pull Any Registers or Any Set of Registers Load Effective Address and HMOS (HIGH-DENSITY N-CHANNEL, SILICON-GATE) s-BIT MICROPROCESSING UNIT Lsurrix (CERAMIC PACKAGE (CASE 715 P SUFFIX PLASTIC PACKAGE CASE TY SUFFIX CCERDIP PACKAGE CASE 738 PIN ASSIGNMENT has ata ats (NOTOROLAING, Te TERMAXIMUM RATINGS ‘This device contain Grcuity to protect the Rating ‘Symbor Vaio AR] inputs against damage due to high sate Scpply Vorage Vee [oo aOst +7D | V_| vokoges or electric fields: however, its ad Vised that normal precautions be taken to Tnput Vota in [0st + v put Veloge Vi oe avaid application of any voltage higher than ‘Operating Temporature Range ToT ‘maximum rated voltages to this high in MOBEOSE, MCEEACBE, MOBSBOSE Tr. Oto +70 Sc ame ea aan MOSSOSEC, MOSSAQBEC, MCSEBODEC 4010 +86 Rolabilty of operation is enhanced unus- Siocage Temperature Range. Tag Lee | CT] od inputs ate ved to an appropriate loge voltage level (e.g. ether Vss er Voc) ‘THERMAL CHARACTERISTICS (Characteristic ‘Symbol__[ Vaue | Unt ‘Thermal esisance ‘ceramic Ea Ceraip| un © srw Paste 100 POWER CONSIDERATIONS. ‘The average chip-unction temperature, Ty, in °C canbe obtained from Tye Tas lPo+al © Were Tas Ambient Temperature, °C am Package Thermal Resistance, Junctionto-Ambient, °C/W PD=PINT* PPORT PinT=lcc%Vec, Wats ~ Chip inven Power PpoRT= Pon Power Dissipation, Watts ~ User Ostend For most applications PpORT-} cl ——Avna I. ajo am o| tse I= -— os ART o | co lel cont Fea Tes —Saisy aw bool Terieg * eternal Tree-State Control FIGURE 3 — BUS TIMING TEST LOAD 5ov Aun22K0 Test Point mo7000 or Equiv. (C=30 pF for BA, BS, LIC, AVMA, BUSY 120 pF for 0007” 90 F for AD-ANS, A/W R= 174M for 0007 165 KO for AD-ANS, AW 2440 for BA, BS, LIC, AVMA, BUSY fe PROGRAMMING MODEL ‘As shown in Figure 4, the MCGB09E adds three registers 10 the set available in the MCEB00. The added registers include 2 direct page register, the user stack pointer, and a second index register. ‘ACCUMULATORS (A, B, D) The A and B registers are general purpose accumulators Which are used for rithmetic calculations and manipulation of data Certain instructions concatenate the A and B registers to {orm a single 16-bit accumulator. This is referred to as the D register, and is formed with the A register as the most signifi cant byte, DIRECT PAGE REGISTER (DP) The direct page register of the MCEBQRE serves to enhance the direct eddressing mode. The content of this register appears at the Figher address outputs (AB-A15) during direct addressing instruction execution. This allows the direct ‘mode to be used at any place in memory, under program Control. To ensure M6800 compatibility, all bits of this register are cleered during processor reset ® MOTOROLA Semiconductor Products Inc. 4FIGURE 4 — PROGRAMMING MODEL OF THE MICROPROCESSING UNIT 18 ° 2X Index Register Y — tnx Regist U = User Stack Panter commen 5 — Haraware Stack Pointer PC Program Counter A 8 Accumulaters 3 2 ° oP Direct Page Regste: 7 2 ELFLML TS]2[v Je] ce ~ conetion code Register INDEX REGISTERS (X, Y) ‘The index registers are used in indexed mode of address ing. The 16-bit address in this register takes part in the cal- culation of effective addresses. This address may be used to point to data directly or may be modified by an optional con- stant or register offset. During some indexed modes, the Contents of the index register are incremented and decre- ‘mented to point to the next item of tabular type data. All four pointer registers (X, Y, U, S) may be used as index registers. ‘STACK POINTER (U, S) ‘The hardware stack pointer (S) is used automatically by the processor during subroutine calls and interrupts, The user stack pointer (U) is controlled exclusively by the pro- ‘grammer. This allows arguments to be passed to and from Subroutines with ease. The U register is frequently used as a stack marker. Both stack pointers have the same indexed mode addressing capabilities 2s the X and Y registers, but ‘also support Push and Pull instructions. This allows the MCBSDRE to be used efficiently as a stack processor, greatly fenhancing its ability to support higher level languages and ‘modular programming, NOTE The stack pointers of the MC5809E point to the top of the stack in contrast to the MCBSOO stack pointer, which pointed to the next free location on stack PROGRAM COUNTER The program counter is used by the processor to point to the address ofthe next instruction to be executed by the pro- cessor. Relative addressing is provided allowing the program Counter to be used like an index register in some situations. CONDITION CODE REGISTER The condition code register defines the state of the pro- cessor at any given time. See Figure 4 @® MOTOROLA Semiconductor Products Inc. 5 FIGURE 5 ~ CONDITION CODE REGISTER FORMAT Us[zPTe Tcary Overton 210 Nogative IRQ Mask Hatt Cory FIRQ Mack entee Flog CONDITION CODE REGISTER DESCRIPTION BIT O(c] Bit 0 is the carry flag and is usually the carry from the binary ALU. C is also used to represent a “borrow” from subtract ike instructions (CMP, NEG, SUB, SBC) and is the ‘complerrent of the carry from the binary ALU. BIT Bit 1 isthe overflow flag and is sotto @ one by an operation which ceuses a signed twos complement arithmetic over- flow. This overflow is detected in an operation in which the carry from the MSB in the ALU does not match the carry from the MSB-1 Bir 2(@ Bit2 isthe zero flag and is set to @ one if the result of the previous operation was identically ero.BITSIN) Bit3 is the negative fag, which contains exactly the value ‘of the MSB of the result of the preceding operation. Thus, a negative twos complement result will leave N set to a one. Bir 4n Bit is the TRG mask bit. The processor will not recogriae interrupts from the TRO lie if this bit is set to @ one, NM FIRO, TRO, RESET, and SWI all set! to @ one. SWI2 and 'SWIS do not affect | BIT 5 (H) Bit 6 is the half-carry bit, and is used to indicate a carry from bit 3 in the ALU as a result of an B-bit addition only (ADC or ADDI. This bit is used by the DAA instruction to perform a BCD decimal add adjust operation. The state of this flag is undefined in all subtract-like instructions. BIT 6(F Bit 6 is the FIRG mask bit The processor will not recognize interrupts from the FIRG line if this bit is @ one. Mi, FIFO, SWI, and RESET all set F to a one. TRO, SW/2, fend SWIS do not affect F. BIT 7 (6) Bit7 isthe entize flag, and when set to one indicates that the complete machine state (all the registers) was stacked, {8 opposed to the subset state (PC and CC). The € bit of the stacked CC is used on @ return from interrupt RTI to deter- ‘mine the extent of the unstacking. Therefore, the current E lett in the condition code register represents past action, PIN DESCRIPTIONS POWER (Vss, Vcc) Two pins are used to supply power to the part: Vss is ‘ground oF 0 volts, while Voc is +5.0 V 25%. ADDRESS BUS (A0-A15) Sixteen pins are used to output address information from the MPU onto the address bus. When the processor does ot require the bus for a data transfer, it will output address FFFF ig, R/We 1, and BS=0; this is a “dummy access" or VMA ‘cycle. All address bus drivers are made high- impedance when output bus avalable (BA) is high or when TSC is asserted. Each pin will drive one Schottky TTL load or four LSTTL loads and 90 pF. DATA BUS (D0-D7) These eight pins provide communication with the system bigiectional deta bus. Each pin will drive one Schottky TTL load or four LSTTL loads and 130 pF. READ/WRITE (R/W) This signal indicates the direction of data transfer on the data bus. A low indicates that the MPU is writing data onto the data bus. R/W is made high impedance when BA is high ‘or when TSC is asserted, RESET A low level on this Schmitt-rigger input for greater than ‘one bus cycle will reset the MPU, as shown in Figure 6. The reset vectors are fetched from locations FFFE}g and FFFF1g (Table 1) when interrupt acknowledge is tue, (BABS = 1) uring inital power on, the reset line should be held low until the clock input signals are fully operational Because the MC6809E RESET pin has a Schmitt-triggerin- put with @ threshold voltage higher than that of standard Peripherals, a simple R/C network may be used to reset the tentre system, This higher threshold voltage ensures that al peripherals are cut of the reset state before the processor. RAT ‘A low level on tis input pin wil cause the MPU to stop running at the end of the present instruction and remain halted indefintey without oss of data. When halted, the BA output is driver high indicating the buses are high im- ppedance. BS is cso high which indicates the processor isin the hat state. While halted, the MPU will not respond to ex- temal realtime requests (FIRG, 10) although NM or RESET will be latched for later response. During the helt state, Q and E should continue to run normaly. A halted state (BA*BS=1) can be achieved by puling HALT iow while RESET is stil low. See Figure 7. BUS AVAILABLE, BUS STATUS (BA, 8S) The bus avaiable output is an indication of an internal ‘control signal wrich makes the MOS buses of the MPU high impedance. When 8A goes low, 2 dead cycle will elapse before the MPU acquires the Bus. BA will not be asserted when TSC is active, thus allowing dead cycle consistency. The bus status output signal, when decoded with BA, represents the MPU state (valid with leading edge of Q) Meu Sum [MPU State Defition BA] 8s 0 | 0 | Normal (Rusning) © | 1 | inept or Reset Acknowledge 1 | 0 | Syne Acknowledge 1 1_| Hatt Acknowledge Interrupt Acknowledge is indicated during both cycles of a hardware vector fetch (RESET, NMI, FIRG, TRO, SWI ‘SWI2, SWI3). This signal, plus decoding of the lower four faddress lines, can provide the user with an indication of Which interrupt level is being serviced and allow vectoring by device. See Table 1 TABLE 1 — MEMORY MAP FOR INTERRUPT VECTORS on ee ra ee MS 1s ription RFC FFFO. Ni FFFE ‘FFT FIR m MOTOROLA Semiconductor Products Inc. 6Mies ‘pou espaowio ssqun ‘son 0° Jo @Benon YB @ PUE SHON g'9 JO ABAYOA Mo} € wo} puE OL PEOUEIE}H xe siuOWeINsEEW BUN '3LON ~ xX Wa XX Wiasna x : wnay | cw) aru | ‘ONW 13834 — 9 auno1a _ ® MOTOROLA Semiconductor Products Inc.MC6809E In 5A 9 J0 BB@OR YBIY @ pu SOA g ‘ONGIA WLSAS HOS ONIWIL NOLLNDX3 NOLONASNI STONIS ONY Lavi — n —_—_—— & MOTOROLA Semiconductor Products Inc.‘Sync Acknowledge is indicated while the MPU is weitng _defer the erbitraton of the next bus cyte to insure the in- for extaal synchronzaton on an iterupt ine tegrty of the above operations. This eferenoe provides the Halt Acknowledge i indicated wien the MC6G09E isin _—_indvble memory access required for a “testand-set” hat condition primitive, using anyone of several react mocity-wite struc tions NON MASKABLE INTERRUPT (NF BUSY does not become active during PSH or PUL opere- 'A negative transition on tis input requests that 9 non- tions. Atypicelread-modify-wite instruction (ASL) is shown maskaole interrupt sequence be generated. Anon-maskable in Figure“. Timing information i given in Figure 12. BUSY interrupt cannot be hibited bythe rogram ond also has @ i Vad tcp ater the rising edge of higher prorty than FIRG, IFO, or software interapts. Our ing recognition of an NMI, the entire machine state is saved on the hardware tack, After eset, sn Nl wil not be recog aval nized until the first program load of the hardware stack AVMA is the advanced VMA signal and indicates that the pointer (S). The pulse width of NMI low must be at least one MPU will use the bus in the following bus cycle. The predic- Zroal tthe Nt input does not moot te manimum Se Up tive netue of the AVMA signa allows efficent shareo-Ous with respect to Q, the interrupt will not be recognized until multiprocessor systems. AVMA is low when the MPU is in. the next eyele See Figure tither 3 FACT or SYNC state. AVMA is valid tcp atter the Tsing e0ge of FAST-INTERRUPT REQUEST (FIRG)" ‘A low level on tis input pin wil rite a ast inert e- quence, provid is mask bit (Fin the Cis Gear Ts se re once hes pri ver the standrdterept request (RC) SEE) tndisfastnnesence tet itslcks ony recontencibe grit natn cyl i il dring the st evi Conan coce gitar nd ineprogram counter The nie Sweyinsucdon, and ite wonton from Nigh tw Wn Tap sowie reutine hould ler te sure ofthe ntarupt___-cuathahe fst byte ofan opr eaiched at he end ‘before doing an RTI. See Figure 9. halted at the end of an instruction li.e., not in CWAI or RESET. nsyne slate. or while stacking during Interns Licis vag tgp after the ring edge oF INTERRUPT REQUEST (IRQ) ‘A ow level input on this pin wal initiate an interrupt re- ‘quest sequence provided the mask bit ()) in the CC is clear Since IRQ stacks the entire machine state, it provides a sc slower response to interrupts than FIRO. [RO also has a TSC (three-state control) will cause MOS address, data, Tower prio than FIFO. Again, the interupt service routine and R/W buffers to assume a highimpedance state. The should lear the source of the interrupt before doing an ATL control signals (BA, BS, BUSY, AVMA, and LIC) will nat go See Figure 8 to the high-impedance state. TSC is intended to allow @ Single bus to be shared with other bus masters (processors CLOCK INPUTS , a 0+ DMA controls. _ E and Q are the lock signals required by the MCSED9E. © While Ei low, TSC controls the address butters and R/W rust lea E; that i, a transition on Q must be folowed by 2 directly. The data bus butters during a write operation are in Similar transition on € after @ minimum delay. Addresses will ® high-impedance state unt Q rises et which time, if TSC is be veld from the MPU, tap alter the faling edge of E, and ‘tue, ther wil remain in @ high-impedance state. If TSC is data will be latched from the bus by the faling edge of & held beyond the rising edge of E, then it will Oe internally While the Q inputs fully TTL compatible, the E input directly latched, teeping the bus drivers in a high-impedance state hives internal MOS circuitry and, thus, requires high level for the remainder of the bus cycle. See Figure 13, ‘above normal TTL levels. This approach minimizes clock skew inherent with an internal buffer. Refer to BUS TIMING CHARACTERISTICS for E and Q and to Figure 10 which shows a simple clock generator for the MCBEDSE. MPU OPERATION Busy During normal operation, the MPU fetches an instruction BUSY will be high for the read and modify cycles of a from memory and then exeoutes the requested function. read-madity-write instruction and during the access of the This sequence bagins after RESET and is repeated indefinite- first byte of 8 double-byte operation le.g., LOX, STD, ly unless altered By a special instruction or hardware occur- ADDO). BUSY is also high during the frst byte of any in- rence, Software instructions that alter normal MPU oper direct oF other vector fetch (e.g., jump extended, SW in tion are: SWI, SWI2, SWIG, CWA, ATI, and SYNC. An. direct, etc.) interrupt or HALT input can also alter the normal execution In @ multiprocessor system, BUSY indicates the need 10 of instructions. Figure 14 is the flowchart for the MCBSDSE. "RI, FRO, and IAG requests are sampled onthe fling edge of 0. One cycle is required for synchronization belore these interrupts ae coq, aged. Th gencig trop] vl nat be senvend unl completion tthe curentnsructon ues SYNC or CWA gndton presen IRS and ERE co ft rain ow ut completo of te event nace, they ma ot be vecognged weve NM hu dred ‘gal remain iow for one cycle No mtecrupts are recognize or atched between the ating eage of RESET and tne sing eage of 8S ncicatn RESET acknowledge. Sev RESET sequence in the MPL flowchart in Figure 14 ac * @ MOTOROLA Semiconductor Products inc. :: IU |c Hy: C 2 Cc i G z = 2 if i z ale e e iE 2 ea) 2Sc(h |e GS BH aGclk |e cf foo |e C Sele /4 none Peas opel te 10 ——_—— @® MOTOROLA Semiconductor Products Inc. ———————~‘ou esiniewo sejun si}0K 0:7, Jo BBRIOK YBIY @ pu SHOR B10 Jo @et}On mo} @ oH} uP 0 psOUELB}o Be suBwe:NsEOW BUN “3LON ‘yuo au19}1 40; UMOYS OP 3 LI L? Y / sna oe Coen FE WA TO4MON HOdMON YA yD Hod tod VINA YC >>>» >For Fr >* > >= IF n ‘out Sod} L+OeMON O4mMON _44sse _L4ddB ou4us 44nd ends Z-ds_i-us aus odd XC XC FFF FFF eine J TLS J lo l L# [osu | ise | etw | pew | cew | oem | gem | yew | erm | z+m | i+w wo touew | oz-w | 0 a rrr ~~ vanbeg wing rote pue Buyaeig nv Samal vom iueung jo 049 801 ONINLL LaNUWaLNI Ould ~ 6 34NDLE & MOTOROLA Semiconductor Products Inc.FIGURE 10 — CLOCK GENERATOR war lo Sa coptonal | MAD Creu f ras7a 1.10 Systm and Processor Ete Systen Vee! i090 222228, NOTE: If options ckcut isnot included the CLR and PRE inure of U2 and US must be ted high ROY ‘STRETCH FIGURE 11 — READ-MODIFY-WRITE INSTRUCTION EXAMPLE (ASL EXTENDED INDIRECT) Memory ‘Memory Location Contents Contents Desciotion a Po s0200 @ [ASL Indexed Opcode soot F Extended Indirect Postbyte 0202 ES Indirect Adsress 4i-Byt0 s0203| oo Indirect Adress Lo Byte 0204] Next Main instuetion — $6200 ct Etfectve Adéress Hi-Byie $8501 $06 Effective Address LoSyte _——_—~ £306} 5 Target Data LC —— ® MOTOROLA Semiconductor Products Inc. 2MC6B09E patou yo sate 1904 aN6 01 LIFLIFLSESLS LF Lr Lier ur Ll iti Li lL? {0 on ‘ asa - Xs wa oe 298 Xx XC Xx =e x xX ee coe 4iise wove oneoe onze X = X X X= ssp l LFurerwtsS LU Lr Lr Ll Littl be LEFLAFLPLPesr lr erp Llypiusytsy Ll Lr lL: | ow | orw | erm | cow | oom | stu | pew | cow | zew | ae fw J iw | ONIWIL ASN@ ~ Z1 3uNDHS @® MOTOROLA Semiconductor Products Inc.® MOTOROLA Semiconductor Products Inc. “ADDRESSING MODES ‘The basic instructions of any computer are greatly en- hanced by the presence of powerful addressing modes. The [MCE809E has the most complete set of addressing modes available on any microcomputer today. For example, the [MCS808E has 69 basic instructions; however, it recognizes 1464 different variations of instructions and addressing modes. The addressing modes support modern program ‘ming techniques. The following addressing modes are avail ‘ble on the MC6B0SE: Inherent (Includes Accumulator! Immediate Extendes Extended Indirect Direct Register Indexed Zero-Otfset Constant Offset Accumulator Offset ‘Auto Increment/ Decrement Indexed indirect Relative ‘Short/Long Relative Branching Program Counter Relative Addressing INHERENT (INCLUDES ACCUMULATOR) In this addressing mode, the opcode of the instruction contains al the address information necessary. Examples of inherent addressing are: ABX, DAA, SWI, ASRA, and CLRB. IMMEDIATE ADDRESSING In immediate addressing, the effective address of the date is the location immediately following the opcode (i.e, the data to be used in the instruction immediately folowing the ‘opcode of the instruction). The MC68O9E uses both & and 16-bit immediate values depending on the size of argument specified by the opcode. Examples of instructions with in- mediate addressing are: LOA #820 Lox #8F000 Loy #caT NOTE 2 signifies immediate addressing; § signifies hexadeci- mal value to the MC6809 assembler EXTENDED ADDRESSING In extended addressing, the contents of the two bytes immediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address generated by an extended instruction defines an absolute address and is not position independent. Examples of extended addressing include’ LDA CAT STx MOUSE LoD $2000 & MOTOROLA Semiconductor Products Inc. EXTENDED INDIRECT AS a special case of indexed addressing (discussed bbeiow), one level of indirection may be added to extended ‘addressing. In extended indirect, the two bytes following the ;postbyte 0" an indexed instruction contain the address of the data LDA cat] LOX. [sFFFE) STU [D0G) DIRECT ADDRESSING Direct addressing is similar to extended addressing except that only ane byte of address follows the opcode. This byte specifies the lower eight bits of the address to be used. The Upper eight bits of the address are supplied by the direct page register. Since only one byte of address is required in direct addressing, this mode cequires less memory and exe- utes faster than extended addressing. Of course, only 256 locations (one page) can be accessed without redefining the Contents of the OP register. Since the DP register is set to 800 on reset, direct addressing on the MC6B09E is upward Compatible with direct addressing on the M6800, indirection is not allowed in direct addressing. Some examples of direct dressing are LDA where DP= $00 LDB where DP=S10 LoD | Beane] rosie ]P tom | ‘Sweets | [7 | “sm | 'Soeote | 2/5 Conman Oise Hom A | Si B | anronreo[ of -[ Laan (2s conpemen orses) — [CSROtT aut [ oftnenen | 1[o-[ “duo Ear Oto a Testo Ref tanoToor_[-s[2 In ammoo 2 cara Ost Fon FA Rep Ot RoR Pano [To] ta | sion [a fo [2s comolamentOtsex)("S RegaerOter S| anmooTor | rfo | tem rior [ao Seger ote a ra Teen ORSaTON T | resonant yt ae ana [aT Telia Increment By 2 ‘arco | 3/0 | CA++) | iARi0001 | 6]0 Seeman BT aro [aT roles Cesena By? immo 3[o-[ La=m | amo eT casa Ofee Fam FEL Bator TOTO LIP Pome (2s Compement Otses) [Sao ‘peat 8|2 te, PeR)—| heaton [8 [2 Ended aes 768i maar . ee tear ps2 ReEYUOe Tr dont cae and “[icicate the number of aditonl cytes and byes respectively forthe petcularndexing vraton ® MOTOROLA Semiconductor Products Inc. 16ACCUMULATOR-OFFSET INDEXED — This mode is similar to constant offset indexed except that the twos com- ‘plement value in one of the accumulators (A, 8, or O) and the contents of one of the pointer registers are added to form the effective address of the operand. The contents of both the accumulator and the pointer register are unchanged by the addition. The postbyte specifies which accumulator to use as an offset and no additional bytes are required. The ad- ‘vantage of an accumulator offset is thatthe value of the off set can be calculated by a program at run-time ‘Some examples are: LOA 8,Y Lox 0,¥ LEAX 8.x AUTO INCREMENT/DECREMENT INDEXED — In the ‘auto increment addressing mode, the pointer register con- twins the address of the operand. Then, after the pointer register is used, itis incremented by one or two. This ad: dressing mode is useful in stepping through tables, moving data, oF creating software stacks. In auto decrement, the pointer register is decremented prior to use as the address of the data, The use of auto decrement is similar to that of auto increment, but the tabes, etc, are scanned from the high to low addresses. The size of the increment/ decrement can be either one of two to allow for tables of either 8- or 16-bit data to be accessed and is selectable by the programmer. The ppre-decrement, postincrement nature of these modes: allows them to be used to create adcitional software stacks that behave identically to the U and S stacks, Some examples of the auto increment/ decrement ‘eddressing modes ere: LDA X+ STD Y++ Woe .-¥ Lox |--s Care should be taken in performing operations on 16-bit pointer registers (X, Y, U, S) where the same register is used to calculate the effective address. Consider the following instruction STX 0,X+ + (X initialized to 0) “The desired result is to store a zero in locations $0000 and 30001, then increment X to point to $0002. In reality, the for lowing occurs: O-temp calculate the EA; temp is a holding register X+2—-X perform auto increment X—=(temp) do store operation INDEXED INDIRECT Al of the indexing modes, with the exception of auto in- crement/ decrement by one or @ + S:bit offset, may have an ‘additional level of indirection specified. In indirect address- ing, the effective address is contained at the location specitied by the contents of the index register plus any off sat. In the example below, the A accumulator is loaded in irectly using an effective address calculated from the index register and an offset Betore Execution ‘A= XX (don't care) X= $000 $0100 LDA (610,x] EA is now $F010 sF010 sft S160 is now the SOIT $50. new 6A SFISD SAA After Execution ‘A=SAA lactual data loaded) X= $F000 [All modes of indexed indirect are included except those which are meaningless (e.g, auto increment/ decrement by 1 indirectl. Some examples of indexed indirect are: LA Lx) (oo 10,8) LOA (8,1 LOD LX++) RELATIVE ADDRESSING The byiels) following the branch opcode is (are) treated 2s a signed offset which may be added to the program counter. If the branch condition is true, then the calculated address (PC + signed offset) is loaded into the program counter. Program execution continues at the new location as indi- cated by the PC; short (one byte offset) and long (two bytes offset) relative addressing modes are available. All of memory can be reached in long relative addressing as an ef- tective acdress interpreted modulo 218. Some examples of felatve addressing ae: BEQ = CAT.-— (shot BGT 0G short cat LBEQ = RAT —_—_ long) Bos LBGT RABBIT long) RAT Nop RABBIT NOP PROGRAM COUNTER RELATIVE ‘The PC can be used as the pointer register with or 16-bit signed offsets. As in relative addressing, the offset is added to the current PC to create the effective address. The effec- tive address is then used as the address of the operand or data. Program counter relative addressing is used for writing position independent programs, Tables related to @ particular routine wll maintain the same relationship after the routine is moved, if referenced relative to the program counter. Examples are: LOA CAT, PCR LEAK TABLE, PCR Since program counter relative is @ type of indexing, an ‘additional level of indirection is available. LDA [CAT, PCR] LDU (006, PCR] ® MOTOROLA Semiconductor Products Inc.The instruction set of the MCGBOQE is similar to that of the [M8800 and is upward compatible atthe source code level The number of opcodes has been reduced from 72 to 58, but because of the expanded architecture and additional ad- dressing modes, the number of available opcodes (with dit- ferent addressing modes) has risen from 197 to 1464, Some of the new instructions are described in detail below. PSHU/PSHS. The push instructions have the capability of pushing onto either the hardware stack (S) or user stack (U) any single register or set of registers with a single instruction PULU/PULS The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately following ‘the push or pull opcode determines which register or registers are to be pushed or pulled. The actual push/ pull se- {quence is fixed; each bit defines a unique register to push or pul, as shown below, Push/Pul Postovte Stacking Order Pll Orser 4 TCT cea ca i a 8 8 Loa. ey a XH a Xo si va ea bo us Hi u/s to PCH PC Lo Push Order Increasing Memory ' TER/EXG Within the MC6808E, any register may be transferred to or exchanged with another of lke size; i.e., &-bit to E-bit of T6-bit to 16-bit. Bits 47 of postbyte define the source rogister, while bits 0-3 represent the destination register “These are denoted as follows: INSTRUCTION SET ‘Tanster/Exchange Postbyte Force] Seiaicn Feo Fat com=piA8) 1000" coax tor=e oopey toio=ecn conu ton=ben NoTE Al ether combinations are undefined and INVALID. LEAX/LEAY/LEAU/LEAS. The LEA (load effective address) works by calculating the cffective address used in an indexed instruction and stores that address value, rather than the data at that address, in a pointer register. This makes all the features of the internal addressing hardware available to the programmer. Some of the implications of this instruction ae illustrated in Table 3 The LEA instruction also allows the user to access data {and tables in a position independent manner. For example: LEAX MSGI, PCR LBSR_POATA (Print message routine) Msi FCC “MESSAGE” This sample progrem prints: ‘MESSAGE’. By writing MSG1, PCR, the assembler computes the distance between ‘the present address and MSGI, This result is placed as a constant into the LEAX instruction which will be indexed {rom the PC value at the time of execution. No matter where ‘the code is located when itis executed, the computed offset ‘rom the PC will put the absolute address of MSGI into the X pointer register. This code is totaly position independent. “The LEA instructions are very powerful and use an internal holding register (temp). Care must be exercised when using the LEA instructions with the auto increment and auto ‘decrement addressing modes due o the Sequence of internal ‘operations. The LEA internal sequence is outlined as follows: LEAa,b+ (any of the 16-bit pointer registers X, ¥, U, or S may be substituted for @ and b.) 1. bottemp (calculate the EA) 2. btI-=b (modify b, postinerement) 3. temp-+a (load a) Leva ,—b 1. bo I+ temp (calculate EA with predecrement) 2. b-1—b —_Imodify b, predecrement) 3. temo {load al ‘TABLE 3 — LEA EXAMPLES Tnswueton | Operation ‘Comment LEAK 10,X[X+ 10 —=X| Adds SB Constant 100% LAX 600,X] X+500—= x] Adds 16-8t Constant SUD 10 X tay AY] y+a —y| dos 28it A Accumulator to ¥ Jtay vy} y+0 =v] dos 168% 0 Accumulster to ¥ Ueau-10,.U | U~10 =U] subseace 10 from U Leas 10.5 | S-10 S| Used to Reserve Area on Stack Juss tos|s+10 -s Used to ‘Cian Up Stace uex_ss[s+s =x Tranters As Well As Adis ® MOTOROLA Semiconductor Products Inc. 18‘Auto increment-by-two and auto decrement-by-two instruc- tions work similarly. Note that LEAX .X+ does not change X; however LEAX,~ X does decrement X.LEAX 1,X should be used to increment X by one. MUL “Multilies the unsigned binary numbers in the A and B ac: Ccumulator and places the unsigned result into the 16-bit D ‘accumulator. This unsigned multiply also allows multiple- precision multiplications LONG AND SHORT RELATIVE BRANCHES. ‘The MCEB09E has the capability of program counter relative branching throughout the entire memory map. In this mode, if the branch is tobe taken, the or 16-bit signed offset is added to the value of the program counter to be Used as the effective address. This allows the program to branch anywhere in the 64K memory map. Position indepen dent code can be easily generated through the use of relative branching. Both short (8 bit) and long (16 bit) branches are available SYNC ‘After encountering a sync instruction, the MPU enters 3 syne state, stops processing instructions, and waits for an interrupt. IL the pending interrupt is non-maskable (NM or rmaskable (FIRG, IRQ) with its mask bit (F or) clear, the pro ‘cessor will lear the sync state and perform the normal inter- rupt stacking and service routine. Since FIRG and IFO are not edgetriggered, @ low level with @ minimum duration of three bus cycles is required to assure that the interrupt will bbe taken. if the pending interrupt is maskable (FIAQ, RO) with its mask bit (For set, the processor wil clear the sync state and continue processing by executing the next in-line instruction. Figure 16 depicts sync timing ‘SOFTWARE INTERRUPTS. ‘A software interrupt isan instruction which will cause an interrupt and its associated vector fetch. These software in- terrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and soft- ware development systems, Three levels of SWI are available fon this MCBB0GE and are prioritized in the following order: SWI, SWI2, SWI. ‘16-BIT OPERATION ‘The MCBBODE has the capability of processing 16-bit data ‘These instructions include loads, stores, compares, adds, subtracts, transfers, exchanges, pushes, and pulls, CYCLE-BY-CYCLE OPERATION The address bus cyce-by-cyte performance chart (Figure 16) illustrates the memony-access sequence corresponding to each possible instruction and addressing mode in the MOSEO9E. Each instruction begins with an opcode fetch While that opcode i being internally decoded, the next pro- ‘gram byte is always fetched. (Most instructions will use the next byte, 80 ths technique considerably speeds through- UL) Next, the operation of each opcode wil follow the flowchan, VMA's en inicaton of FFFFI6 on the address bus, R/W-=1 and 8S=0. The folowing examples iustvate the use of the chart Example 1: L8SR (Branch Taken) Before Execution SP= F000 000 \BsR CAT saoo0 CAT CYCLE-BY-CYCLE FLOW (Cyeie # | Address | Date [IW [Description T | 800 [17 | 1 [Opoode Fetch 2 | aor | 2 | 1 fottser High ave 3 | eoce | oo | 1 fottset tw Byte 4a ree | * | 1 [ommove 5 | eee | + [1 Kwacye & | acco | + | 1 [Computes Bronch Address 7 | fee | * | 1 |wacyce 8 | err | a | 0 |stack High Order Bye of Return Acdeess| 9 | ere | a3 | 0 Stack Low Orcer Byte of Rewin caress Example 2: DEC (Extended) seco0 «(DEC = $000 A000 FCB $80 CYCLE-BY.CYCLE FLOW ‘Gyale # [Asaress | Data [R/W]Description 7 [ao | 7a | 1 [Opcode Fetch 2 | aor | A0 | 1 Joperand Address, High Bye 3 | soz | 00 | 1 |Operand address, Low Byte a | eee | * | |ommcyae 5 | so | a | 1 |Read the Oats eo | ere | * | 1 WMA cyoe 7_| Free | 7 | 0 |Stoxe me Decremented Dats "The data bus has the data at that particular adcress. INSTRUCTION SET TABLES The instructions of the MCSBORE have been broken down into five different categories. They are as folows: bit operation (Table 4) 16-bit operation (Table 5) Index ragister/stack pointer instructions (Table 6) Relative branches {long or short) (Table 7) Miscallaneous instructions (Table 8) Hexadecimal values for the instructions are given in Table 8 PROGRAMMING AID Figure 18 contains @ compilation of data that wil assist you in programming the MC6B03E. MOTOROLA Semiconductor Products Inc.Mies porou asynoui ss ‘ueso0014 rh ss0ppe wou, Jon 0:2 10 0Be}08 yO © pue OH gO 10 BENDA Mole WOH} pue O} PooUO.}O! ove swwoWEINSeoU BURN 8popmouroy aus ONIWLL ONAS — 91 BUNDLE ——— ® MOTOROLA Semiconductor Products Inc.FIGURE 17 — CYCLE-BY-CYCLE PERFORMANCE (Sheet 1 of), Ce ~~ ® MOTOROLA Semiconductor Products Inc.FIGURE 17 — CYCLE-BY-CYCLE PERFORMANCE (Shest 2 of 5) t+ = n T i T + ; sed Ce = t T + t L t n _ == i S| fey 5 ee ; — me] freee] i = =a j = — = — conan T T — a Fe ) MOTOROLA Semiconductor Products Inc. 2Mest FIGURE 17 — CYCLE-BY-CYLE PERFORMANCE (Sheet 3 ofS) & MOTOROLA Semiconductor Products Inc.FIGURE 17 ~ CYCLE-BY-CYCLE PERFORMANCE (Steet 4 ofS) EF] a see) ee el Cee T t + ® MOTOROLA Semiconductor Products Inc. aFIGURE 17 — CYCLE-BY-CYCLE PERFORMANCE (Sheet Sof 5) ® MOTOROLA Semiconductor Products Inc. %‘TABLE 4 ~ 88IT ACCUMULATOR AND MEMORY INSTRUCTIONS Tiremonica) ‘Operation [ADGR, ADCE Tada memory to accurTuator with cary [AOA ADDE ‘Add memory 19 accumulator IANDA, AND: ‘And memory with accumulator IAS. ASLA, ASTB | Avithme shift of sccumustor or memory It IASR, ASRA, ASRO | Aithmeie shift of sccumulator or memory ght arr, Bir Bit test memory with accumula IELR, CLRA, CURB | Clear socumitor or memory locaton [OMA CMPE Compare memory rom sccumuator ICOM, COW. COMB | Complement accumulator or memory IoesT0m DAA, Decimal ast A accumulator [DEC DECA, DECE | Decrement accumulator or memory loeaion IEORA, EORS Exclusive of memory with accumulator IEXG Ai, R2 Exchange Ai with R2 (AT, R2 = A, B, GC, DF) INC. INCA, INCE Tnerement secumulator or memory locaton TDA, tos Toad accuriator from mamony ISL, tStA USE Topical shit eft absurulator or memory Tecan CSR, CSRA, LSRB | Logie! shift ight socumulator or memery locaton Mo Unsigned mutton (A x 8 — DI INEG, NEGA, NEGE | Negete accumulator or memory [ORA, ORB, ‘OF memary with scsumulator IROL, ROLA, ROLE | Rotate accumulator or memory Wh IROR, RORA, RORS | Rotate accumulator or memory Fight ISBCA, SBCB 'Subvastremory from accumulator wit BOTW ISTA, STB Slows soeumulstor 19 meron ISUBA, SUBS Subtract memory fom accumulator [TST. TSTA, TSTS | Test eocumulator or memory location ITeR AI, Aa Transfer Ri 19 R21, 2 = A,B, COOP) NOTE: A, 8, CC or OF may be pushed io (pul from) ether stack wih PSHS, PSHU IPULS, PULL instructions TABLE 5 — 16-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS. Ninemonicis) Operation [ADDO a memory 1 D accumulator [omen Compare memory trom D accumulator IxG 0.8 Exchange D with X,Y. S, Vor PC [Loo Load D sooumator from memory Sex Sign Extend B accumulator nto A SesuTatOr isto Store D scoumlator to memory IsuBD Subvact memory tom D scoumlator [TFR OLA Transfer D to X.Y. 8, Vor PC [TERA O. TransterX, Y, S; Uor PC 16D NOTE: © may be pushed {pulled to ether stack with PSHS, PSHU (PULS, PULL! instructions ‘TABLE 6 — INDEX REGISTER/STACK POINTER INSTRUCTIONS. Instruction Description CHIPS, CMU. Compare memary Wom stack power ‘CMPX, CMPY Compare memery Wom index register XG RT, A Exchange 0. X, ¥, $, U or PC with 0, ¥,¥, 5, Ur PC TEAS, UEAU Tose effecive address into stack pointer TEAK, LEAY Loach effecive address into index regite 1S, LOU Lead stack pointer from memony Tox, LY Load index register from memory PSHS: PushrA, B, CC, OP, 0, X, ¥, U, or PC ante harGware stack PSHU Push A.B, CC, DP, 0. X, ¥. S. or PC cnto user stack PULS Pul A, 8, CC. DP. D. XY. U or PC fom nardware stack PULW, PulA, 8, CC, DP,D. X,Y, S or PC ton hardware stack 31, 57 Store sock pointer 19 memory SIX. st, Store index register to memory TFA AI, AD Transter D.X, ¥, 5, Vor PCD YS UOC ex [Aca 8 sccumulater fo X lunsgned? @& MOTOROLA Semiconductor Products Inc. %MC6809E ‘TABLE 7 — BRANCH INSTRUCTIONS Tnsruction Deseripton SIMPLE BRANCHES BES, 1BEO Branch if equal BRE, LBNE Branch iF equal BMI, LOM Branch itmnus PL, LBPL Branch ips acs, Lacs Branch cary set BCC, LBC, Branch ifearry ear VS, LBVS Branch i overfow set BvC, Lave Branch if overtiow clear ‘SIGNED BRANCHES BGT 18Gr Branch it greater Isgned! BvS. Levs Branch ified P's complement raul [Boe tee Branch i greater than or equal (signed! [Be0. Lse0 Branch iF equal BNE, LENE ‘Branch if not eaual BLE, BLE Branch f less than or equal lagred) BvC, Lave Branch i vai 7s complement result UT, LBLT ‘Branch i ess thas Isigned) UNSIGNED BRANCHES oH er Branch higher lonsigned) CC, Lace Branch i higher oF some (unsgnedl HS, LHS Branch higher or same (unsigned EO, BEG Branch equal BNE, UBNE Braneh not equal BLS, L8LS. Branch i lower or same (unsigned) BCS, L8CS, Branch if lower [unsigned BLO, LBLO Branch i lower lunsignes! (OTHER BRANCHES BSA LeSR, Branch to subroutine BRA, CORA Branch aivays GAN, LAN ranch never TABLE 8 — MISCELLANEOUS INSTRUCTIONS instruction Description ANDES "AND condition code repster cwAl "AND condition code register, then wal for interrupt NOP, (No operation ‘ORG ‘OR condition code oui Me sare ISR amp 1 subroutine aTr Few from interrupt ATS. Return from subroutn SWI, SWIZ, SWS | Software erupt labsolute marect SYNC ‘Syrcheorie with nterupt line ® MOTOROLA Semiconductor Products Inc.Meco ‘TABLE 8 — HEXADECIMAL VALUES OF MACHINE CODES. OP | Mor Mode [= | # JP | Mom Meae_[= Mer ose [= 0 | NES Direct [6 ao | LeAX. Tncexed [4 NEG Indexed [ox | 2+ of 3i | Leavy 4 : 4 a}s a2 | Leas 4 + 3 | com se] 2 |x | ceau Inddaed 4 com e+ | 24 ot | usr 6] 2 | | eshs Irmmod | 5 Ls e+ | 2+ 6 | 35 | pus. Innes | 5+ . 06 | ROR es] 2 |x| psn Immes | 5 ROR e+ | 24 o7 | ase 6 |2 |x| eu immed | 5+ ASR 6+ | 2+ og | ASL, ist e]2 Jal: = ASL. LSL e+ | 2+ o@ | AOL 6] 2 |x| ats Ineront| 5 FOL e+ | 24 oa | Dec 6 | 2 | 3a asx 3 Dec. e+ | 2+ ell 3a | an ens) * vc | ine 6 | 2 | sc} cw 20 Inc e+ | 2+ oo | tst 6 | 2 Ja] mu Innerent| 11 1st e+ | 2+ oe | ae a]2 [xls ~ JMe ¥ [as | 2+ of | cia ovter |e | 2 | a | sw lenerent| 19 cur Indexes |6+ | 2+ 10 | Page2 ee Innerent| 2 Nes extends]? | 3 11 | Page3 a5 ale . 12 | nor lnperent|2 | 1 Jaz | * * 13 | syne Innerent|=4] 1 | «3 | coma 2 com 7/3 we a | UsRa 2 tsa 7 | 3 | a|e . 16 | vera Restve|5 | 2 | a6 | Rona 2 ROR 7 |3 17 | casa Feaive|9 | 3 | a7 | Asna 2 ASA 7/3 w | ae | Asta, isi 2 ASL, SL 7 |3 19 | vas, Inmerent|2 | 1 | 49 | noua’ 2 ROL! 7 |3 1a | once immed {3 | 2 | 4a] veca 2 Dec 7 \3 w|+ = ae | > . tc | anoce immed }3 | 2 J ac | inca 2 Inc 7 Ja 10 | sex tnnerent|2 | 1 | ap | Tsta 2 1st 7 |3 te | exc immed] | 2 | ae} = MP a [3 iF | FR immed |s | 2 | 4 | cura tentrent| 2 cur lexondea}7 | 8 zo | ara Rewve|3 | 2 | 0 | nace innerent| 2 SUBA immea 2 | 2 21 | BRN a}2 fal: MPA a |2 [2 2 | aH a}2 [als SBCA 2 | 2 a | aus 3 | 2 | 53] come 2 SUBD a [3 24 | BHS, 8ce 3] 2 | os | isae ANDA 2 [2 25 | 810, acs, a}2 [al- Bia 2 |2 25 | BNE 3 | 2 || rors 2 Loa 2 [2 a | Bea a] 2 | 57 | sre 2 . | ave 3 [2 J se | asie isis 2 coRA 2 |2 2 | avs 3 |2 | =| ros 2 DCA 2 |2 2a | ape 3 | 2 | sa] vece 2 ona, 2 |2 2a | an 3 [2 [sl - ADDA y [2 [2 2c | ace 3 | 2 J sc] ince 2 mex. immes [@ | 3 20 | sur 3 | 2 | x0] tte 2 ase Reatwe|7 | 2 ze | act 3 |2 [sl Lox Immes }3 | 3 2 | au Reatve|3 | 2 5F | cure snndrent| 2 * Leceno: Number of MPU cycies tess possible push pull or indexed-made cycles) £ Number of program bytes * Denotes unused opcode & MOTOROLA Semiconductor Products Inc. ceTABLE 9 — HEXADECIMAL VALUES OF MACHINE CODES (CONTINUED) (OP _ Miner Mode [= | # [OF | Wnom Mode [+ [oP [Mnom Mose [- Te wo —SUBA Diest |= co | sues immes [2 | 2 si CMPA Ale 12 7 oct | cue a [2 | 2 age 2 and 3 Mechine ec Seca 4 ]2 | a seco 2 | 2 Codes so suaD 612 | a] sooo a] 3 8s ANDA 2 ]2 | a| anos 2 | 2 [02 [usa Reawe|s | « sara 4]2 || ane immed }2 | 2 | 1022 | cae 0)| 4 6 LDA 4 ]2 | | we immed |2 | 2 J 1023) cats 56] sr STA ae ]2 Pol: 4 1024 | LaHs, ace sie) | 4 se EORA «12 | | core 2 | 2 | 102s |tecs: veto 50 | 4 so ADCA #12 | | aoce 2 | 2 | 102s | cone 50] faa ORA | 2 | cal one 2 | 2 | r027| taco 6) | 4 88 ADDA 412 | ce! aoos 2 | 2 | 1028 {rave sie) | 4 sc cMPx 6 }2 | cc} woo | 2 | 102s) tavs 50] 6 80 JSR 7/2 Jools ' roza}LaPL 5 4 8 Lox v |e [2 | ce] wo immed {3 | 3 J to2e| com 50) | 4 oF STK ower {3 [2 | cel + 1o2c | Lace | 4 J] i020] taut 56 | 4 ‘80 SUBAL Indexed }4+ | 2+ J 00 | sue ome eT 3 | toze| tact 56] 4 Al CMPA A [as] 24 | or | cure S| 3 J soze | eve eatve | 561] & a2 SBCA a+| 2+ | 92] sace 2] 3 | tase | swe Inberent| 20 | 2 63 SUBD e+] 2+ | 03} ADD toes | caro Immes 5 | 3 As ANDA as | 22 | 4 | Anos 4] 2 | rcec| cmey is [a as BTA jaz] 2s | 05] ere 4] 2 | cee | tov tmmes a | 2 jas toa ei] 2b | 06 | we a] 2 Voss [euro Ore [> | 3 ay sta las [2+ | o7 | ste 3 | to8c | omer 7 |3 na eona a] 22 | oe cons “| 2 | tse |tov e 3 Jas ADCA ay] 24 | 98] ance 4] 2 | soar | sty iter Jo | 3 AA ORR as] 2s J oa] one: 4} 2] soa] cme noes |7+ | 34] JAB ADDA jas | 2 | 98] Doe £] 2 | toaclcwey 7+ | 34 Jac CMPX ex] 2+ J OC} 100 E| 3 | toreluoy e+ | 34 aD JSR 74] 2s J 20] sto £] 2 | tone] sty inatses 6+ | 33] ae Lx ¥ [sv | 2+ | OF] wou NTE} 3. | 1083] ero Exenced) 8 | lar sTx inderea|5+ | 2+ [OF | stu DiectllP rose] cwPy je | | suse Tndsxes | a] 2 | 1088 | Lov n [4 so suBA exendes]s [2 | ex | core A [4s] 2+ | soBe| sty enenses]? | a1 cMPA 5 ]3 | e| sace e+] 2+ | soce] Los tmmed [4 | 4 ez Seca 513 | | aooo f=] 2+ | r00e| cos Orect fo | 3 83° SUBD 7 13 |e | anos =| 2+ | so0F] sts Dives [| 3 34 ANDA 8 ]3 |e | one jes] 2+ J soe [cs insexes [6+ | 34] 85 iT 5 ]3 | es | toe ja] 2+ | oer [sts indexes fo | 35] 88 LDA 5 |3) | e| ste 3] 2+ | sore [cos Exended|7” | & 37 STA 5 |3 | | cone jes] 24 | sore [sts Extended]? | 88 EORA 5 ]3 | | aoce a4] 2+ | rae [sw Innere [20 | 2 39 ADCA 5 [3 | eal one jes] 2+ | sas [omeu immed |5 | 4 BA ORA 5 ]3 | ee] soos 44] 2+ | nec cues immed [5 | 33 ADOA 5 ]3 | ec] woo ea] 2+ | 195 [cmeu Drect |7 | 3 Bc cMPx 7 )3 | | sto f+] 2+ | rac|cmes Dre [7 | 3 ao sR e fa | el tou ¥ [ex] 2+ | stas|cmeu indexes {7+ | 344 BE Lx vie }3 Le | sw ingexes [54] 2+ | riac|cmes indexes |7+ | 34] te 3 ten we __Jeweds [2 Papas —Jougede 2 | rarleums | Seal | Fi | cme. p| 3 F2 | sace is] 3 3 | poo i] 3 F4 | Anos. is | 3 5 | are is | 3 6 | oe js) 3 #7 | ste s | 3 NOTE: Al iss pcos beh untnes | #3 | £080 5] 3 oT Fa | one vy [5] 3 ra | apo exenced|s | 3 re | too Exenced] 6 | 3 | sto o| 3 Fe | Lou s| 3 re | stu emensed]s | 3 ® MOTOROLA Semiconductor Products Inc. 2MC6809E FIGURE 18 — PROGRAMMING AID arora OE Tnimadaie [rect indewed —[ Eo s|alz|slo nsrcton| Forms [Op [= et Oe [=| At Sel =| FL Of =F] Oo] =| 7 Desciption rewtzivrel AeK BAT S| 1[8+X—x iUnsigned! eTelelele aoc [aoa wT AT A] BLA] a] wl Tw] STS aris =a Thy soce_|co|2| 2] o8/4| 3] eles] as| ro 5] 3 esmecce abhi faoS—aooa [ee] 2} 2] s+] 2] 48] a=] 2] 88] 8] roe nnn sone jes} 2] 2) oe} 4 | | ee/e-| 2s|ra| 5| 3 esnce ihe soop_|e|é| 3] ose | a| eslec|as|rs| >| 3 sae 1-0 shits ARO —JanDA Tw ZTAY wT] a] aay ep epee] STS RR M=E Oe anos |ce{2| 2) o«/4| 2] tela] a>] ea] s| 3 paws fifo] fanoec |¥¢ | 3] 3 eda hance ; ast asin Slab) a — ahr ASB | 2|:] leit ee Jaleyili]t At co fe| 2| else a-| | 7] 3 whe br me feel Rasa 2 Spy ASR sf 2| 4 e}Of Tp +0 alili}e]e ash alelo nas wy ge lelililel Ce Ce Ca sys] a Tea MAR sya] = are__|e|2|2|os[s|2 fls|a Bi text 8M AB) stilifol: eae Yee Pap aoa efor iyo] o cine Js] 2] sJoze |2]o}s [a] 0 eu olela lala oat fo itele eur ewe PTET ay ot ay a ayeps careae Ton pre ewes fer |2] 2] or [| 2 fy s| a Caroare M om 8 ele}ifilt Jeweo |'o]é] 2] %0]7| 3 ol elé Canoes Mtr om B sfefiltls | 8 2 2 | Jews |i ]s] | m ne] « Coron MM hom $ efefelele omy |i |s] ef 8 ]r fs t]e| camoate MM om U effete @ 2 a cuex Jac] ] a] se fe | 2 bel >| 3 | compare Mints tom x fils ewer Jo |s] 2| 10/9] 3 ol a|¢ angare MM= thom Y at ee 2 el" | con [cone Byzp as THOT cous s) 2] iE3 ififols com cafe] 2] cales|2| ra] >| 2 iw thiol War Raz oA WIN=CC Wat TT 7 OR t TELE Ossetia SEES Dee] BEC TEPER spp | ece sa] 2] ife-tce fhe bee oa} | 2| efor] 2-fra] 7 | 2 tm chide [ER Teoma Tez] zp we Psy 2] aay epee] STS ME Tyo cons__|co|2| 2| oe [a 2] eles a:| Fel 5 | 3 Benne hho) ee [av e2 [eet 2 i= *EePTel ie] We =pIp pee TPT Nee se| 2| s]ecize BARE Ime oc} a| ocloe| 2-| re] >| 2] neice chet: aa ce [af 2peela-[2-[el<] ay eFC ielletel= sR wT [aT aolreles feo; ss Tees STO [EEEE we —}rox Je] 2] A] eT 2] a8] =] af oO] S| a Tyo toe ee |2) 2) o/s] 2| eela-|ar| ro) 5 | 3 hoe t}i}fol too ce] 3] 4] oe|s| 2| ee|s-]ar|ec| 6 | 3 Mates=0 t]s}i fol: tos fica) 2/50] e | 3] tolec| sx | >| & Musics 2]i]ifo) = ce oe]? |? | ce fe wou [ee] a] a] oe|s | 2| else|arfrel s| 2 wueru efi] }o} tox |e) 3) 3] [5 | 2| else] a-|ae| 6 | 3 Maen ffl fol toy fio) 2] 3] 0 fe | | toler] ax] to) 9 | « teusicy sfefatg} = s B 2 se tex UES le] eas oP ple teu a s| 2+] eau SAM eax a as| 2+ esta oysfa]efs ay alar| es ey ELSE LEGEND: Complement ot 1 Testandsetif sue, cleared otherwise ‘OP Operation Code Hevadecima) Transfer ito + Not Attectes “= Number of MPU Cycles Ho Hattcary rom bx 3) Ce Condton Code Register 4 Number of Program yes Negative (gn bt CConcateston| + Arithmetic Plus. Z Zero result V__ Logical or = astnmete Minus V_Overtion, 2 complement A Logical and + Musiiy © carry rom ALU Logical Exctsve or & MOTOROLA Semiconductor Products Inc. 20URE 18 — PROGRAMINNG AID COUTINED aia ae ee |e slalzlile eee foi SEE apr oR es omceson —_FRTETY aa ett Ace see a2} 1] Ae |} | fe PB eer NOP T T2] 2 [1 [No Operation elelel one. 2] al 4] 2] elas] 2+] ral 5] 3 Jevu-e slilrlole Jorce 2 i [CCV IMM= Co 21} [Pur PULS. 2 T [Pull Regaters from S Stack le ls|ele) ROL os} 6 | 2| o9j6+| 2+] 79] 7] 3 Toy oa ehiteds fore | ye]2] 3) SOO |2]: |: me os] | 2| esfeel axl v6] of Ts sw | 1 |.20 | 1 [Software interrupt 3 efele fete 2 1 Toacaun gutabenecyeandbyiecoun, Tecan coun ad avo cba om he NOEXED ADDRESSING MODE bl, 6. Sit oon ond, Sald ond SW Sor ara 1. Condon Cot ate dct et oon ratte, Spm Cae to an SE ) MOTOROLA Semiconductor Products Inc.FIGURE 18 — PROGRAMMING AID (CONTINUED) Branch Instructions slalalilo FIFAED Ineoueion pewieson _[A[NIZ[VEC tnarucion| Forme Dewioton [HNL] ae 2 [Bann coo * Bs SY S| 2 owen tomer] *]o] 9] {Ste | 10|si6| ¢ |Con banon : ena tees | to|sia| « Jtonpannen | |] BS see spy = car tetr | 0st & flora Sranenczero 2] 2] 2/2] 2 We] S| foe Perry 2 Bee ]aGE Pac] 3] oannetwe T=] [of] = 8 {Ste | Io)oe|& owt [2]5)515]¢] foe ae a a ePll]= Cae oa Co a eer | t0[sta| « |tongaranen>zee | [2] 2]2] aR faa] SF aren Ps soc 2 | | tee, |'10|sie| 4 llong Brancneus 2s] ]o | masa mare PPP] | al*° 2 — | tema [6] § | 3 tong erarcn wor [o>] | 2 Coe oe eC ee ‘rsone tam |io] € [4 lorserrcemove |2]2)2]2]2 tans | r0]sia) « jucng aren igre | o]]«] «| © y 2 or Sone Tease Jao] 7 | fawn w Smears] |] p> WE Ya] F] 3 | a iennsteo tse || $ | 3 Kongerneno |= |o] =] fats | %|si0| & [Cone Semen zor Stoovire Ea WE [ove foaren v=o Toss ae fore | ele * feb | * WEP SP Ya tvs s/ 3 fog ec L S at ‘SIMPLE BRANCHES, P= SIMPLE CONDITIONAL BRANCHES (Notes 1-4) BRA 32 Tot___Trwe___OP___Falee__OP. eae ore Net BM 2B PLA BRN 2 3 2 sco BNE 8 (eRN 102154 BS GB Bsr oO 7 2 BCS CCH Lesa 7 9 3 ‘SIGNED CONDITIONAL BRANCHES (Notes 1-4) [UNSIGNED CONDITIONAL BRANCHES (Notes 1-4) Tost Tre OP __Falso__OP Tet____Tre___OP__—Fao OP. vom BGT 26~—~«wLESCF im BH mm BoE 2G LTD tam BHS BL tem Be 7 BNE 8 BEQ BNE 8 tem BE Fact fem LS BHC rem BLT 2D GE. 2 fem BLO HBS NOTES 1. All condonsl branches have both short and long variations 2. All short branches are 2 bytes and require 3 eyes. 3. All conditional long branches are formed by pefxing the short branch opcode with $10 and using @ 16-bit destination offset. |4 All conditions long branches require 4 bytes and 6 cycles if the branch is taken cr 5 cycles ifthe branch isnot taken. 5. 5I6} means: 5 eyeles if branch not taken, 6 cycles i taken, ® MOTOROLA Semiconductor Products Inc. 2INDEXED ADDRESSING MODES None Tae esrb 5] > [Rear Pox |=] re Forms orm | opcose |-[#| tom | once |-|3 consent Gree Fam Fi No OTE ® fiawccro}ofoy 1A hrasoo] sf Sai Ofer 1.'e fanmonna| fo] “axtaurs to eon Een ote nom [impor] ft] inca prieo| fp Tear oft nik [immorot|el2 [inal [nator | 12 Iscmtatr Ota From BR A~Reiser foe] A A finwoori] Jo] taal Faarorso] fo Scnogete otter | 2h |inmooor] fo] (o-a) faasorr| fo Bega ot 8a fimmownfslo| fo.A1 fnanor | 9 Ia reemenToRcemeT A — Treen ‘aroono| 20] ra lowes invent 82 "eromor| 30 | 1m + ipaaenr | fo Sxceert 81 taromro| 20 | "" * rl etowes urea 8) 2 ‘nro | fo -.a)"pamaon [fo censure Frm Fo EB OTe pearaop | fn Pom px Teo af 168 of o.2¢a | exon] s]2] in rca fers | la Eonar TES Adon aie ta _fonn fohe YU oS XoBori coe INOEXED ADDRESSING POSTEYTE REGISTER BT ASSIGNMENTS See rccnenearer areal Indexed = Index Register Post-Byte Register Bit eee TsTereTsT aT TreretaTstanTo Yes Reger STREP Dah — Pott Rate TATA] olo [ols eae) ifatefofofo fife 5 = Hardware Stok TET Eos Tale [ fo] [ofo-[ eae 8 OTe 5 a Taleo] fol em = + Accs Oe Tale ole [ro fea-= sh = Acca of a TPRLR[T [fo oo] ex = Re er Ofer Tae ofopT fesse vesrorer| §©\——\ 7 Talat o[t eee R= 0 of ¥ Tbe [o[o Tee = FC = bar OTe metagen Thxfe[ TT] Ops [ER = PC + 16 Bi Ortser ee ect Page Register Teta ty ee = 1 —condtion Code Tetelf [A= Laas EEL Tz[ye] ce conston co Wore T— casero Acteting Moe Fal TiN) ‘Overtiow as 200 epatie (Sign bit when b7 = O! IRQ Interrupt Mask Regi Ft RR ta Cory ox fest wrap as orev Lee Stato Sac ‘oly X= Dont cae nes ® MOTOROLA Semiconductor Products Inc. maPusn/PulPost Bvt ec Stacking Oder PuOraer Tcca : A ce Los a oPr 8 x OP ee00 vectors y xvi FEE Renan su Xlo FRC NM FFA SW i YH Feroira Tranaer/ Exchange Post Byte Y to FFFS FIR = U/SHi FFFa swiz Sourze | [oetingon Uslo Eee sw PCH FFFO Reseved Polo p ote Puan Order aor0=¥ i Inerestng Memory yor=0PR ‘ORDERING INFORMATION Postage Temperature Type | Frequency | "Range | Order number Teenie 10 WHe | O° te TOS] WOROOEL LSufe | LoMHz | —a0°C toasec | MosmaECL ismie | oscto 70% | MoeEADBEL 1smiz | aoe toasec | MceBaovecl 2omHe | oscto 70% | MCssEoeL 2omie | aoe to asec | MosBB09ECL, Paste 1 0Me [0-10 70°C | MCBROEP PSutix | 10 MHz | ~a0%ctosec | MCBEORECP tismHz | 0°c%0 70°C | McseacgEe isms | 40°C wo asec | mcesAcnece 20MHz | o°cto 70°C | MCBEBOOEP 2amie_| -4o%c toasec | Mossen9ece cara TOMHs | O°C to 70°C | MCBBDES ‘SSutfx | 1oMHz | -a0°c roasec | MosemDEcs 15MH: ] oc to 70% | MoBBAODES 15 mHz | 40°C w 85°c | MosBAoBECS 2omHe | oct 70° | MceeBo8eS 2omns | aoc roasec | wceea09ecs ® MOTOROLA Semiconductor Products Inc. aIie PACKAGE DIMENSIONS. ‘© mension Lo cenTeR PLEADS WHEN FORMED Panauvec” 5. Dimension Aan 8 mecuoeswenseus, 6 | aera - ° He { ote i were oe te 5 =F ‘ ae a aE ue Pie Tae ae eee fect Hite Tao ree of satin a surex oneness ave rmcace [RELATION TO SEATING PLANE AND CASE TIN08 ete rae tata CHE ee RSENS no sur aa) ee Besancon T [-_Jimuimerens] “cues: ae ea | “ef re70-| 549 | 000 0 a : SHetat ae te f Eig tes | 080 | Ee Pea oat ete Sa nye tee ares wr Hi-Hat) anne G [essere STS) centr Pact 2 Co amen Care & MOTOROLA Semiconductor Products Inc.“Motrclaroservws ight to make change wthou ther note to any products erin, Motrla rakes nowarary, representation or quararoorogardng ‘he sutabany of produ lr any parSoderpupoee, or Goes Moora assume ny indy ang ot ofthe apoication or us ota proau! or cout, _andepectcaly declams any andalliaoity ncn wihout uma consequonalorertal damages. Typeal parameters canandcovary nite ‘ppleations. Aloperating parameter, incudg Typical must be vated or each customer aplcaton by Cusiome'stectncal experts, Motola does ‘ot convey an fewree unde is pant igh rote rights of er. Motorla products are ot Goxigned, red, o authorize use as compos _ystersrtendad for sutgeal plato te body, or aheraploatonswtendedo suppor or suet a orfr any oe apeston n whic the are ot ‘he Metola prod cous cea astuson whore personal ay or th may oot Shou Buyer purchase or use Motor produ foray Such ‘Usntondeder uraihoteed apleaton, Buyer chal nderny dhol Metroland ts oficars, employs, ubatlanes alates and stibtersRarmoss ‘Spat all came, cot, damages, and exponsos, and raaorabl atoms tos aring oto, ty of rey. ry cam of paren! ry of Goa ‘ssoiaed wit sich unintended or unauorze se, even suc clam alleges ha terol was negigetrepacng he design or menfactue othe part. tori a (8) aro rgitre wadorars of Moola, e. Motorola, re. ean Eaual OpporuntyAtratve Action EMDOYS. Literature Distribution Centers: USA: Motorola Literature Distbution; PO. Box 20012; Phoenix, Arizona 86038. EUROPE: Motorola Lid; European Literature Centre; 88 Tanners Drive, Blakelands, Mion Keynes, MK4 SBP, England, JAPAN: Nippon Motorola Li; 482-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan, [ASIA PACIFIC: Motorola Semiconductors H.K. id; Siloon Harbour Center, No.2 Dai King Street, Tai Po Industrial Estate, Tai Po, N-T, Hong Kong, = @® moronora | ‘MCB809E/0 {N08 0