Present Sat State Variables \ ABC Present State Identifiers LD st cen ns Pit ist r ores Indicates @ holding condition — Indicates a sample transition path () ) FIGURE 11.42 Representation of a fictitious five-state FSM having two external inputs and two outputs, (a) State diagram representation. (b) The equivalent state table for the FSM in (a).11,10.2 State Tables and State Assignment Rules The tabular representation of the state diagram is called the state table, or next state table if output data is excluded. Shown in Fig. 11.42 are two representations for a Mealy FSM hay- ing two inputs S and T, and two outputs P and Q. The state diagram for this FSM, lacking only a suitable state code assignment, is given in Fig. 11.42a, and its equivalent state table Tepresentation is presented in Fig. 11.42b. In both representations, literals (a, b, c, d, e) are uscd for state identification. On the vertical axis of the state table they represent the present state (PS), and within the state table they represent the next state (NS). The encircled state identifiers indicate a holding condition for which PS =NS. Thus, in state a the FSM must hold on input condition S + 7, so the identifier a is encircled in row a for ST input values 01, 11, and 10, meaning S7 + ST + ST = §+T. The state identifiers that are not encircled in the state table represent unstable conditi For instance, in state a under holding condition 57, a transition to state b takes placé ut 7 changes 1 + 0, as indicated by the two transition paths. Or in state b, holding on 57, a transition to state e will occur if input S changes 0 1. The FSM cannot transit from state b to state ¢ without changing both inputs simultaneously, a condition that should be avoided if possible. Clearly, the state table presents all features of the state diagram and is, therefore, the tabular equivalent of the state diagram or ASM graphic representation. But the sequential behavior of the FSM is much more easily grasped from the state diagram than from the state table. Furthermore, given a suitable state code assignment, it should be obvious that the state diagram is far easier to use540 CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS fora“pencil-and-paper” design of an FSM than is the state table. There are, however, several important usages of state tables, among them being their use for CAD purposes explored in Section 11.11. ‘The state table provides a relatively simple means of obtaining the state code assignments required for the optimum or near-optimum NS and output logic of an FSM by using D flip- flops as the memory. There are three state assignment rules by which this can achieved, listed in descending order of priority: Rule 1 (The “into rule”): Make logically adjacent assignments to present states that branch “into” a common next state, provided that their input conditions are the same. Rule 2 (The “from rule”): Make logically adjacent assignments to states that are the next states “from” a common present state, provided that their input conditions are logically adjacent. Rule 3 (The output rule): Make logically adjacent assignments to states having the same outputs. Rule 3 is relatively unimportant except where large numbers of outputs are involved. In Fig. 11.43a use is made of the next state table in applying rules 1 and 2 to the FSM of Fig. 11.42. Here, rule I has the highest priority and is applied to state adjacency sets in columns under constant input conditions. Thus, by rule 1, states within the set (abc) should be made logically adjacent, and those within set (de) should be made adjacent, both sets be- ing under the same input condition fg = 57, Similarly, states within sets {ae} and {bd}, under input condition f= ST. should be made logically adjacent, etc. Rule 2, of lesser priority, is applied to the rows of the state table as indicated in Fig. | 1.43a. Now the input conditions must be logically adjacent. For example, in present state d, states with sets (de), {cd}, and {ce} should be made logically adjacent. State sets that appear in both rule | and rule 2 are given the highest priority and are indicated in dashed boxes. These are followed in priority by those that appear only in rule 1. Those of least priority appear only in rule 2. Notice that not all sets appearing in rules 1 and 2 can be accommodated, hence the reason to prioritize, as just discussed. For example, it is not possible to include set (ce} together with the higher priority sets. By incorporating rules | and 2, as indicated in Fig. 11.43a, there results the following three-bit state assignments: a=000, b=001, c=O0Il, d=101, and e= 100. These assignments are used in the state diagram of Fig. 11.43band will generate an optimum or near-optimum set of nexi-state functions, but only in three bits. It is possible, albeit unlikely, that a four-bit set could result in a more optimum set of next-state functions. However, no attempt will be made to explore this possibility. Note that ORGs are possible in both P and Q. The NS K-maps are plotted from the state diagram in Fig. 11.43b, assuming the use of D flip-flops, and are given in Fig. 11.44 together with the output K-maps. Also shown are the minimum covers for the K-maps that yield the following NS and output@ © FIGURE 11.43 ‘Application of state assignment rules J and 2 othe FSM of Fig 12a (a) Next tate table showing _rouping of states (shaded areas that satisfy rule 1 andthe results of ue 2. () Te fully documented state diagram showing an optimism or near optimum se of sate code assignments resulting from application of rules f and 2 (a) woo tt to ot te ttt o |{serl| st | + of o fst] rig ofS [sa [sa] ¥)| 6a 2 g ; Te lePePel fel Pele ‘s FIGURE 11.44 [Next-tate and oupat K-maps plotted from the state diagram in Fig. 1143b assuming the use of D Aip-tops and showing minimum cover. 341 542 [CHAPTER 11 / SYNCHRONOUS FSM DESIGN CONSIDERATIONS Dy=CsT + BCST + ACS + AT Dy =CST + BT De = AS + CT ‘ atin PaacsT Q=ACS + BCST + ABC ‘These results represent a total gateFinput tally of 14/40, excluding possible inverters. Eqs. (11.11) will be compared with the results generated by using the array algebraic approach to design discussed next in Section 11.11.