Digital Design: Verilog and FPGA Course

This course aims to provide a comprehensive introduction to digital electronics design using
Verilog and implementation using field-programmable gate arrays (FPGAs).
The curriculum will cover a wide range of topics, including digital design flow, Verilog, static timing
analysis, power considerations, clock domain crossing, clock dividers, FPGA flow and
architecture, and embedded systems.
Course Overview:
• You can enroll in either the FPGA course only or both Verilog and FPGA courses.
• Total of 18 sessions over 9 weeks:
o An introductory session for each of the Verilog and FPGA courses.
o The Verilog course will consist of 5 sessions.
o The FPGA course will consist of 13 sessions.
Schedule:
• Days: Friday and Saturday
• Session Duration: 4 hours each
Location:
• Most of The Sessions are Online.
• Onsite sessions held at Zewail City of Science and Technology
Hardware Platforms:
• Spartan 6 FPGA SP605 Evaluation Kit
• AMD Zynq 7000 SoC ZC702 Evaluation Kit
Practical Work:
• Labs and Assignments Provided in Each Session
• 4 Projects
Instructor: Yousef Sherif
• FPGA Design and Verification Engineer @ PyramidTech LLC
• Teaching Assistant @ AUC
• VLSI Community Founder
• Mentor for a digital design graduation project at Cairo University
• Knowledge in Digital Design, Verification, FPGA, and ASIC flow
• LinkedIn Profile: https://www.linkedin.com/in/yousef-sherif-6343b219b/
Course Registration:
https://forms.gle/hfj3Ap91Tds1mBVy9
Here is my YouTube channel if you want to see me explaining some Digital Design topics:
https://www.youtube.com/channel/UC0uOIvW491kamm9wWEpYVqA

Eng. Yousef Sherif Digital Design: Verilog and FPGA Course 2024
 Session 1: FPGA & Verilog Courses Introduction

• Overview on Electronics
• Digital Circuit Implementation Approaches
o Custom
o Semicustom
▪ Array-Based
• Pre-Diffused Arrays
• Pre-Wired Arrays (FPGA)
▪ Cell-Based (ASIC)
• Standard Cells
• Macro Cells
Online
• ASIC Flow

• FPGA Flow
• Companies
o Company Types
o Companies in Egypt
o Positions Rules

• Tools
o Getting Familiar with The Tools We Use
o See The Tools Outputs Through a Small Example

Session 2: Verilog

• Motivation for Verilog

• Data Types
o Data types
o Scalar/Vector
o Arrays
• Building Blocks
o Module
o Port Online
o Module Instantiations
o Sequential vs Combinational Logic
o Assign Statements
o Operators
o Concatenation
o Always Block
o Initial Block
o Generate Block

Eng. Yousef Sherif Digital Design: Verilog and FPGA Course 2024
 Session 3: Verilog

• Behavioral Modeling
o Block Statements
o Assignment Types
o Blocking / Non-Blocking
o If-Else-If
o Case Statement
o Un-Intentional Latches Online
o Loops
o Functions / Tasks
o Parameters
o `ifdef `elsif
o Inter / Intra Delay
o Hierarchical Reference

Session 4: Verilog

• Simulation
o Simulation Basics
o Testbench
o Timescale
o Scheduling Regions
o Clock Generator
o System Tasks and Functions Online
▪ Display Tasks
▪ Math Functions
▪ Timeformat
▪ Timescale Scope
▪ File Operations
o Compilation and Simulation Automation Script

Session 5: Verilog

• Finite State Machine

o FSM Motivation and Usage
o FSM with a Single Process Online
o FSM with Two Processes
o FSM with Three Processes

Project (1) Announcement: Designing a UART Transceiver

Eng. Yousef Sherif Digital Design: Verilog and FPGA Course 2024
 Session 6: FPGA Course Introduction

• FPGA Vendors and Tools

• FPGA Architecture
• Understanding JTAG Online
• Embedded System Design
• Practical Example on The FPGA Flow

Session 7: Static Timing Analysis

• STA
o STA Motivation
o Timing Paths
o Understanding Important STA Terms:
▪ Setup, Hold, and Tc2q Times
▪ Arrival, and Required Times
Online
▪ Recovery, and Removal Times
▪ Slack and Skew
o Setup and Hold Equations
o Reason for Setup and Hold Time in Flip-Flop
o How to Solve Setup and Hold Violations
o Important Timing Constraints

Session 8: Static Timing Analysis and Power Analysis

• STA
o Important Timing Constraints [Cont.]
o Analyzing Timing Reports

• Power
Online
o Importance of Low Power
o Causes of Power Dissipation
o Factors Affecting Power
o Power Reduction Techniques
o Analyzing Power Reports

Eng. Yousef Sherif Digital Design: Verilog and FPGA Course 2024
 Session 9: Clock Domain Crossing and Clock Dividers

• Clock Domain Crossing (CDC)

o Clock Domain
o Metastability Due to CDC
o Problems Due to Metastability
o Synchronizer Types
▪ Bit Synchronization
▪ Bus Synchronization
o Mean Time Between Failures (MTBF)
o Data Loss
▪ Slow to Fast Crossing
▪ Fast to Slow Crossing
▪ Preventing Data Loss Through FIFO Online

• Clock Dividers
o Synchronous and Asynchronous Clock Dividers
o Modulo Counters
o Ring Counters
o Divide by N Using Modulo Counters
o Divide by N Using Ring Counters
o Behavioral RTL Clock Dividers
o Structural RTL Clock Dividers
o A General Clock Divider
o Xilinx Clock Buffer Resources

Session 10: ISE Design Suite

• Getting Familiar with The Tool

• Understanding the Steps to Program an FPGA
o With a Schematic Example
o With a Verilog Code Example Online
• Understanding ISE Simulator
• Applying Timing and Physical Constraints
• Analyzing Reports and Solving Violations

Project (2) Announcement: Elevator Controller

Eng. Yousef Sherif Digital Design: Verilog and FPGA Course 2024
 Session 11: Hands-on Experience with ISE & Spartan 6 FPGA

• Getting Familiar with the Spartan 6 FPGA

• Revision on ISE Design Suite
OnSite
• On-Site Practical Projects
• Implementing Project 2 on FPGA

Session 12: Vivado

• Getting Familiar with The Tool

• Understanding the Steps to Program an FPGA
• Understanding Vivado Simulator Online
• Applying Timing and Physical Constraints
• Analyzing Reports and Solving Violations

Session 13: Vivado IP Resources

• Phase-Locked Loop (PLL)

• Clock Buffer Primitives (BUFGCTRL)
• Block RAM (BRAM)
• First In First Out (FIFO) Online
• Integrated Logic Analyzer (ILA)
• Digital Signal Processing (DSP)
• Creating a Custom IP

Project (3) Announcement: RSA Encryption Algorithm

Session 14: Hands-on Experience with Vivado & Zynq 7 FPGA

• Getting Familiar with The Zynq 7 FPGA

• Revision on Vivado
OnSite
• On-Site Practical Projects
• Implementing Project 3 on FPGA

Eng. Yousef Sherif Digital Design: Verilog and FPGA Course 2024
 Session 15: Embedded System Design with Vivado

• Embedded System Design with Microblaze Soft Core Processor and Vitis
o Defining and Configuring MicroBlaze Processor
o Adding Peripherals and IP blocks to The System
o Generating and Implementing The Design
o Exporting Hardware and Creating an Application Project in Vitis
o Writing C code for MicroBlaze
o Building The Software Project to Generate ELF File
Online
o Generating Boot Image & Programing FPGA with Boot Image
• Embedded System Design with Zynq Hard Core Processor and Vitis
o Similar Flow as Microblaze Soft Core Processor
• Using ILA with an Embedded System
o Adding an ILA to your Embedded System
o Using the ILA for Debugging the Internal Signals of The FPGA

Final Project Announcement: AES Encryption Algorithm

• Implement AES Algorithm on The FPGA Fabric
• Create a Custom IP for The AES
• Build an Embedded System that Contains:
o Your AES Custom IP
o Zynq Hard Core Processor
• Use a PLL IP for Generating the System Clock
• Write C Code that Runs on the Processor
• Debug the Internal Signals of the System Using an ILA

Session 16: Hands-on Experience with Embedded System Design

• Practical Projects on Embedded System Design OnSite

Session 17: Selected Topics in FPGA

• Using TCL Commands to Execute the Tool Flow

Online
• FPGA in The Loop (FIL) Concept Overview [FPGA with MATLAB]

Session 18: Final Project Implementation

• Program The FPGA with The Final Embedded System Project OnSite

Eng. Yousef Sherif Digital Design: Verilog and FPGA Course 2024