Unit 1 Module 1-Merged

Computer Architecture and
Organization
The General Purpose Machine

Prerequisites
Experience with a high level language
◦ Pascal
◦ C, etc.
Assembly language programming
Digital logic circuits
Chapter 1 - A Perspective
Alan Turing showed that an abstract computer,

a Turing machine, can compute any function
that is computable by any means
A general purpose computer with enough
memory is equivalent to a Turing machine
Over 50 years, computers have evolved
◦ from memory size of 1 kiloword (1024 words) and clock periods of 1
millisecond (0.001 s.)
◦ to memory size of a terabyte (240 bytes) and clock periods of 100 ps.
(10-12 s.) and shorter
More speed and capacity is needed for many
applications, such as real-time 3D animation,
various simulations
Scales, Units, and
Conventions
Term Normal Usage As a power of
2
K (kilo-) 10 3 2 10 = 1024
M (mega-) 10 6 2 20 = 1,048,576
G (giga-) 10 9 2 30 = 1,073,741,824
T (tera-) 10 12 2 40 = 1,099,511,627,776
Term Usage
Note the Powers of 2 are
diﬀerences m (milli-) 10 - used to describe
μ (micro-) 3
between usages. 10 - memory sizes.
You should commit 6
n (nano-) 10 -
the powers of 2 and 9
p (pico-) 10 -1
10 to memory. 2
Units: Bit (b), Byte (B), Nibble, Word (w), Double Word, Long Word
Second (s), Hertz (Hz)
Views of Computer
There are various views of computer, such
as
User
Machine language programmer
Computer architect
Computer logic designer
Fig 1.1 The User’s View of a
Computer
The user sees software, speed, storage

capacity,
and peripheral device functionality.
Machine/assembly Language
Programmer’s View
Machine language:
◦ Set of fundamental instructions the machine can execute
◦ Expressed as a pattern of 1’s and 0’s
Assembly language:
◦ Alphanumeric equivalent of machine language
◦ Mnemonics more human oriented than 1’s and 0’s
Assembler:
◦ Computer program that transliterates (one-to-one
mapping) assembly to machine language
◦ Computer’s native language is assembly/machine
language
◦ “Programmer”, as used in this course, means
assembly/machine language programmer
Machine and Assembly
Language
The assembler converts assembly language to machine
language. You must also know how to do this.
Op Data reg. #5 Data reg. #4
code
MC68000 Assembly Language Machine Language
MOVE.W D4, D5 0011 101 000 000 100
ADDI.W #9, D2 00000001 10 111 100

0000 0000 0000 1001
Table 1.2 Two Motorola MC68000 instructions

The Stored Program
Concept
The stored program concept says that the program
is stored with data in the computer’s memory. The
computer is able to manipulate it as data
• for example, to load it from disk, move it in
memory, and store it back on disk.
It is the basic operating principle for every computer.

It is so common that it is taken for granted.
Without it, every instruction would have to be
initiated manually.
Fig 1.2 The Fetch-Execute Cycle
Programmer’s Model:
Instruction Set Architecture
(ISA)
Instruction set: the collection of all machine
operations.
Programmer sees set of instructions, along
with the machine resources manipulated by
them.
ISA includes
◦ instruction set,
◦ memory, and
◦ programmer accessible registers of the system.
There may be temporary or scratch-pad
memory used to implement some function is
not part of ISA.
◦ “Non Programmer Accessible.”
Generations of
Microprocessors
There are various generations of
microprocessors
In Fig 1.3 (next page) a comparison between
some of them is given
Points to consider when analyzing

Microprocessors
◦ Programmer’s manual
◦ Machine instruction classes
◦ Machine, processor, and memory states
◦ Procedure calls and machine interrupts
● Procedure calls
● Machine interrupts
● Exceptions
Fig 1.3 Programmer’s Models
of 4 commercial machines
Machine, Processor, and
Memory State
The Machine State:
◦ contents of all registers, m/c memory in system, accessible to
programmer or not
The Processor State:
◦ registers internal to the CPU
The Memory State:
◦ contents of registers in the memory system
◦ “State” is used in the formal finite state machine sense
◦ Maintaining or restoring the machine and processor state is
important to many operations, especially procedure calls and
interrupts
Data Type: HLL Versus Machine
Language
High level language (HLL) provide type
checking
◦ Verifies proper use of variables at compile time
◦ Allows compiler to determine memory requirements
◦ Helps detect bad programming practices
Most machines have no type checking
◦ The machine sees only strings of bits
◦ Instructions interpret the strings as a type:
● usually limited to signed or unsigned integers and
FP #
◦ ASCII, EBCDIC, etc
◦ Interpretation of bits:
● A given 32 bit word might be an instruction, an
integer, a FP #, or four ASCII characters
Tbl 1.3 Examples of HLL to
Assembly Language Mapping
This compiler:
◦ Maps C integers to 32 bit VAX integers
◦ Maps C assign, *, and + to VAX MOV, MPY, and ADD
◦ Maps C goto to VAX BR instruction
The compiler writer must develop this
mapping for each language-machine pair
Tools of the Assembly
Language Programmer
The assembler
The linker
The debugger or monitor
The development system
Who Uses Assembly
Language?
The machine designer
◦ must implement and trade-off instruction functionality
The compiler writer
◦ must generate machine language from a HLL
The writer of time or space critical code
◦ Performance goals may force program specific optimizations
of the assembly language
Special purpose or imbedded processor
programmers
◦ Special (additional) functions and heavy dependence on
unique I/O devices in embedded systems can make HLL’s
useless
Key Concepts in Assembly
Language Programming
Instruction set
Programmer’s model of machine
◦ Instruction set architecture (ISA)
Manipulation of machine’s data types
Available data types in machines
Mapping between HLL and the ISA
The Computer Architect’s
View
Architect is concerned with design &
performance
Designs the ISA for optimum programming
utility and optimum performance of
implementation
Designs the hardware for best implementation
of the instructions
Uses performance measurement tools, such as
benchmark programs, to see that goals are
met
Balances performance of building blocks such
as CPU, memory, I/O devices, and
interconnections
Meets performance goals at lowest cost
Constraints
Constraints on optimization:
◦ Cost
◦ System size
◦ Thermal/mechanical durability
◦ Timely availability of components
◦ Immunity to static charge
Constrained imposed by
◦ Internal
◦ External (corporate marketing, department of defense, etc)
Constraints may be ‘conflicting’
The Big Picture
ISA as a bridge
CPU and memory
Buses
Examples
Buses as Multiplexers
Interconnections are very important to

computer
Most connections are shared
A bus is a time-shared connection or
multiplexer
A bus provides a data path and control
Buses may be serial, parallel, or a
combination
◦ Serial buses transmit one bit at a time
◦ Parallel buses transmit many bits simultaneously on many
wires
Fig 1.4 One and Two Bus
Architecture Examples
Fig 1.5 Getting Specific:
The Apple PowerMac G4 Bus
(simplified)
Fig 1.6 The Memory
Hierarchy
Modern computers have a hierarchy of memories
◦ Allows tradeoffs of speed/cost/volatility/size, etc.
CPU sees common view of levels of the hierarchy.
Tools of the Architect’s
Trade
Software models, simulators and emulators
Performance benchmark programs
Specialized measurement programs
Data flow and bottleneck analysis
Subsystem balance analysis
Parts, manufacturing, and testing cost
analysis
Key Concepts: Architect’s
View
Architect responsible for the overall system
design and performance
Performance must be measured against
quantifiable specifications
Architect uses various performance
measurement tools
Architect is likely to become involved in
low-level details
Architect often uses formal description
languages to convey details
Architect strives for harmony and balance in
system design
Computer System Logic
Designer’s View
Implementation Domain
What is implementation domain?
Designs the machine at the logic gate level
The design determines whether the architect
meets cost and performance goals
Architect and logic designer may be a single
person or team
Implementation Domains
An implementation domain is the collection of

devices, logic levels, etc. which the designer uses.
Possible implementation domains:
VLSI on silicon
TTL or ECL chips
Gallium Arsenide chips
PLA’s or sea-of-gates arrays
Fluidic logic or optical switches
Fig 1.7 Three Different
Implementation Domains
2-to-1 multiplexer in three different implementation
domains
◦ generic logic gates (abstract domain)
◦ National Semiconductor FAST Advanced Schottky TTL (VLSI on Si)
◦ Fiber optic directional coupler switch (optical signals in LiNbO3)
The Distinction between Classical
Logic Design and Computer Logic
Design
The entire computer is too complex for
traditional FSM design techniques
◦ FSM techniques can be used “in the small”
There is a natural separation between
data and control
◦ Data path: storage cells, arithmetic, and their connections
◦ Control path: logic that manages data path information
flow
Well defined logic blocks are used
repeatedly
◦ Multiplexers, decoders, adders, etc.
Two Views of the CPU PC
Register
31 0
Programmer: PC
Logic Designer
(Fig 1.8):
Tools of the Logic Designer’s
Trade
Computer aided design tools
◦ Logic design and simulation packages
◦ Printed circuit layout tools
◦ IC (integrated circuit) design and layout tools
Logic analyzers and oscilloscopes
Hardware development system
Key Concepts: The Logic
Designer
Logic designer works in both the domain of
abstract Boolean logic and the selected
implementation domain
◦ At the abstract logic level, the logic designer is concerned with the
correctness of the design
◦ At the selected implementation domain level, the logic designer is
concerned with fan-in and fan-out constraints, logic minimization
techniques, power required, heat dissipation, propagation delay, number
of components, and so on
Logic designer must bounce between the abstract
logic level and the implementation level to get an
optimum design
Logic designer works with logic design and
minimization tools, board layout tools, IC design
tools, and hardware design tools (such as logic
analyzers, oscilloscopes, and development sys)
Historical Generations
Early work
◦ Charles Babbage
◦ George Boole
◦ Claude Shannon
Relay Computer: 1930s

◦ George Stibitz
◦ S.B. Williams
◦ G. K. Zuse
◦ etc
Generations
Historical Generations
1st Generation:
◦ 1946-59 vacuum tubes, relays, mercury delay lines
2nd generation:
◦ 1959-64 discrete transistors and magnetic cores
3rd generation:
◦ 1964-75 small and medium scale integrated circuits
4th generation:
◦ 1975-present, single chip microcomputer
Integration scale: components per chip
◦ Small scale: 10-100
◦ Medium scale: 100-1,000
◦ Large scale: 1000-10,000
◦ Very large: greater than 10,000
Summary
Three different views of machine structure and
function
Machine/assembly language view: registers,
memory cells, instructions.
◦ PC, IR,
◦ Fetch-execute cycle
◦ Programs can be manipulated as data
◦ No, or almost no data typing at machine level
Architect views the entire system
◦ Concerned with price/performance, system balance
Logic designer sees system as collection of
functional logic blocks.
◦ Must consider implementation domain
◦ Tradeoffs: speed, power, gate fanin, fanout
2-1 Chapter 2 - Machines, Machine Languages, and Digital Logic
Chapter 2: Machines, Machine

Languages, and Digital Logic
Instruction sets, SRC, RTN, and the mapping of register

transfers to digital logic circuits
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
Chapter 2 Topics
• 2.1 Classification of Computers and Instructions

• 2.1 Different ISA styles: 3, 2, 1, & 0 Address Operations
• 2.3 Informal Description of the Simple RISC Computer,
SRC
• 2.4 Formal Description of SRC using Register Transfer
Notation (RTN)
• 2.5 RTN Description of Addressing Modes
• 2.6 Register Transfers and Logic Circuits: from
Behavior to Hardware
What are the components of an ISA?

• Sometimes known as The Programmers Model of the machine
• Storage cells
• General and special purpose registers in the CPU
• Many general purpose cells of same size in memory
• Storage associated with I/O devices
• The Machine Instruction Set
• The instruction set is the entire repertoire of machine operations
• Makes use of storage cells, formats, and results of the
fetch/execute cycle
• Defines Register Transfers
• The Instruction Format
• Size and meaning of fields within the instruction
• The nature of the Fetch/Execute cycle
• Things that are done before the operation code is known
Fig. 2.1 Programmer’s Models of

Various Machines
We saw in Chap. 1 a variation in number and type of storage cells
M6800 I8086 VAX11 PPC601
(introduced 1975) (introduced 1979) (introduced 1981) (introduced 1993)
7 0 15 87 0 31 0 0 63
A AX R0 0
32
15 B Data BX 12 general 64-bit
registers purpose floating point
6 special IX CX R11
registers registers
purpose SP DX AP 31
registers
PC FP 0 31
SP
Status Address SP 0
and BP 32 32-bit
PC general
count SI
registers purpose
DI registers
PSW
31
CS
Memory 0 31
0 segment DS 232 bytes 0
216 bytes
of main registers SS of main More than 50
memory ES memory 32-bit special
capacity capacity purpose
216 – 1 232 – 1 registers
IP
Status More than 300
Fewer instructions
than 100
instructions 0 252 bytes 0
220 bytes
of main of main
memory memory
capacity capacity
220 – 1 252 – 1
More than 120 More than 250
instructions instructions
What Must an Instruction Specify?

Data Flow
• Which operation to perform: add r0, r1, r3
• Op code: add, load, branch, etc.
• Where to find the operand or operands add r0, r1, r3
• In CPU registers, memory cells, I/O locations, or part of
instruction
• Place to store result add r0, r1, r3
• Again CPU register or memory cell
• Location of next instruction br endloop
• Almost always memory cell pointed to by program counter—PC
• Sometimes there is no operand, or no result, or no next instruction.
Can you think of examples?
Instructions Can Be Divided into 3

Classes
• Data movement instructions
• Move data from a memory location or register to another
memory location or register without changing its form
• Load—source is memory and destination is register
• Store—source is register and destination is memory
• Arithmetic and logic (ALU) instructions
• Changes the form of one or more operands to produce a result
stored in another location
• Add, Sub, Shift, etc.
• Branch instructions (control flow instructions)
• Any instruction that alters the normal flow of control from
executing the next instruction in sequence
• Br Loc, Brz Loc2,—unconditional or conditional branches
Tbl. 2.1 Examples of Data Movement

Instructions
Instruction Meaning Machine

MOV A, B Move 16 bits from mem. Loc. A to loc. B VAX 11
lwzR3, A Move 32 bits from mem. Loc. A to reg. R3 PPC601
li $3, 455 Load the 32-bit integer 455 into Reg. 3 R3000
mov R4, dout Move 16 bits from R4 to port dout DEC DP11
IN A1, KBD Load a byte from port KBD to Accum. Pentium
LEA.L (A0), A2 Load address pointed to by A0 into A2 M68000
• Lots of variation, even with one instruction type
Tbl 2.2 Examples of ALU

(Arithmetic and Logic Unit)
Instructions
Mulf A, B, C Multiply the 32-bit floating point values at mem VAX 11
locations A and B and store in C
Nabs r3, r1 Store abs value of r1 in r3 PPC601
ori $2, $1, 255 Store logical OR of reg 1 with 255 into reg 2 R3000
DEC R2 Decrement the 16 bit value stored in reg R2 DEC DP11
SHL AX, 4 Shift the 16-bit calue in AX left by 4 bits 8086
•Notice again the complete dissimilarity of both syntax and semantics.
Tbl 2.3 Examples of Branch

Instructions

BLSS A, Tgt Branch to address Tgt if the least significant VAX11
bit of mem loc’n. A is set (i.e. = 1)
bun r2 Branch to location in R2 if result of previous PPC601
floating point computation was Not a Number (NAN)
beq $2, $1, 32 Branch to location (PC + 4 + 32) if contents MIPS R3000
of $1 and $2 are equal
SOB R4, Loop Decrement R4 and branch to Loop if R4 ≠ 0 DEC PDP11
JCXZ Addr Jump to Addr if contents of register CX ≠ 0. Intel 8086
CPU Registers Associated with Flow of

Control—Branch Insts.
• Program counter usually locates next inst.

• Condition codes may control branch
• Branch targets may be separate registers
Processor State
C N V Z
Program Counter Condition Codes
•
•
•
Branch Targets
HLL Conditionals Implemented by

Control Flow Change
• Conditions are computed by arithmetic instructions

• Program counter is changed to execute only instructions
associated with true conditions
C language Assembly language
CMP.W #5, NUM ;the comparison

if NUM==5 then SET=7 BNE L1 ;conditional branch
MOV.W #7, SET ;action if true
L1 ... ;action if false
CPU Registers may have a

“personality”
• Architecture classes are often based on how where the
operands and result are located and how they are specified
by the instruction.
• They can be in CPU registers or main memory
Stack Arithmetic Address General Purpose

Registers Registers Registers
Push Pop
Top
Second
• • •
• • •
• • •
•
•
•
St a ck Ma chine Accum ula t o r Ma chine Ge ne ra l Re g is t e r

Ma c h in e
3, 2, 1, & 0 Address ISAs

• The classification is based on arithmetic instructions that have
two operands and one result
• The key issue is “how many of these are specified by memory
addresses, as opposed to being specified implicitly”
• A 3 address instruction specifies memory addresses for both
operands and the result R ← Op1 op Op2
• A 2 address instruction overwrites one operand in memory with
the result Op2 ← Op1 op Op2
• A 1 address instruction has a register, called the accumulator
register to hold one operand & the result (no addr. needed) Acc
← Acc op Op1
• A 0 address instruction uses a CPU register stack to hold both
operands and the result TOS ← TOS op SOS where TOS is Top
Of Stack, SOS is Second On Stack)
• The 4-address instruction, hardly ever seen, also allows the
address of the next instruction to specified explicitly.
Fig. 2.2 The 4 Address Instruction

Memory CPU add, Res, Op1, Op2, Nexti (Res ← Op1 + Op2)
Op1Addr: Op1
Op2Addr: Op2
ResAddr: Res
NextiAddr: Nexti
Instruction format
Bits: 8 24 24 24 24
add ResAddr Op1Addr Op2Addr NextiAddr
Which Where to Where to find
operation put result Where to find operands next instruction
• Explicit addresses for operands, result & next instruction

• Example assumes 24-bit addresses
• Discuss: size of instruction in bytes
Fig 2.3 The 3 Address Instruction

Memory CPU add, Res, Op1, Op2 (Res ← Op2 + Op1)
Op1Addr: Op1
Op2Addr: Op2
ResAddr: Res
Program
NextiAddr: Nexti 24
counter
Where to find
next instruction
Instruction format
Bits: 8 24 24 24
add ResAddr Op1Addr Op2Addr
Which Where to
operation put result Where to find operands
• Address of next instruction kept in processor state register—

the PC (Except for explicit Branches/Jumps
• Rest of addresses in instruction
• Discuss: savings in instruction word size

Memory CPU add Op2, Op1 (Op2 ← Op2 + Op1)
Op1Addr: Op1
Op2Addr: Op2,Res
Program
NextiAddr: Nexti counter 24
Where to find
next instruction
Instruction format
Bits: 8 24 24
add Op2Addr Op1Addr
Which Where to find operands
operation
Where to
put result
• Result overwrites Operand 2
• Needs only 2 addresses in instruction but less choice in
placing data
Fig. 2.5 1 Address Instructions

Memory CPU add Op1 (Acc ← Acc + Op1)
Op1Addr: Op1
Where to find
operand2, and
where to put result
Accumulator
Program
NextiAddr: Nexti counter 24
Where to find
next instruction
Instruction format
Need instructions to load
Bits: 8 24
and store operands:
LDA OpAddr add Op1Addr
STA OpAddr Which Where to find
operation operand1
• Special CPU register, the accumulator,
supplies 1 operand and stores result
• One memory address used for other operand

Instruction formats
Memory CPU push Op1 (TOS ← Op1)
Bits: 8 24
Op1Addr: Op1
Format push Op1Addr
TOS
Operation Result
SOS
etc.
add (TOS ← TOS + SOS)
Bits: 8
Stack
Program Format add
NextiAddr: Nexti 24
counter Which operation
Where to find Where to find operands,
next instruction and where to put result
(on the stack)
• Uses a push down stack in CPU

• Arithmetic uses stack for both operands and the result
• Computer must have a 1 address instruction to push and pop
operands to and from the stack
Example 2.1 Expression evaluation for 3-

0 address instructions.
Evaluat e a = (b+c)*d - e
3 -a d d re s s 2 -a d d re s s 1 -a d d re s s St a c k
add a, b, c load a, b load b push b
mpy a, a, d add a, c add c push c
sub a, a, e mpy a, d mpy d add
sub a, e sub e push d
store a mpy
push e
sub
pop a
• # of instructions & # of addresses both vary
• Discuss as examples: size of code in each case
Fig. 2.7 General Register Machines (1

½ Address
CPU
Machine)
Registers Instruction formats
Memory
load load R8, Op1 (R8 ← Op1)

Op1Addr: Op1 R8
load R8 Op1Addr
R6
R4
add R2, R4, R6 (R2 ← R4 + R6)
add R2 R4 R6
R2
Nexti Program
counter
• It is the most common choice in today’s general purpose

computers
• Which register is specified by small “address” (3 to 6 bits for 8 to 64
registers)
• Load and store have one long & one short address: 1 1/2 addresses
• Arith. instruction has 3 “half” addresses
Real Machines are Not So Simple
• Most real machines have a mixture of 3, 2, 1, 0, 1 1/2

address instructions
• A distinction can be made on whether arithmetic
instructions use data from memory
• If ALU instructions only use registers for operands and
result, machine type is load-store
• Only load and store instructions reference memory
• Other machines have a mix of register-memory (1 or 1 ½
address machine) and memory-memory (2 or 3 address
machine) instructions
Trade-Offs
• The 3-address machines have the shortest code

sequences, but large number of bits per instruction
• The 0-address machines have the longest code
sequences, but small number of bits per instruction
• Even in 0-register machines, you need 1-address
instructions
• General register machines use short addresses in
place of the long memory addresses to address
internal registers
• Load-store machines only include memory addresses
in the data movement instructions
• Register access is much faster than memory access.
• Short instructions are faster!
Addressing Modes
• An addressing mode is hardware support for a useful way of

determining a memory address
• Different addressing modes solve different HLL problems
• Some addresses may be known at compile time, e.g. global
vars.
• Others may not be known until run time, e.g. pointers
• Addresses may have to be computed: Examples include:
• Record (struct) components:
• variable base(full address) + const.(small)
• Array components:
• const. base(full address) + index var.(small)
• Possible to store constant values w/o using another memory
cell by storing them with or adjacent to the instruction itself.
HLL Examples of Structured Addresses
• C language: rec -> count

• rec is a pointer to a record: full address variable Count
• count is a field name: fixed byte offset, say 24 Rec →

• C language: v[i]
• v is fixed base address of array: full address
constant
• i is name of variable index: no larger than array size V[i]
• Variables must be contained in registers or memory V→
cells
• Small constants can be contained in the instruction
• Result: need for “address arithmetic.”
• e.g. Address of Rec -> Count is address of Rec +
offset of count.
Fig 2.8 Common Addressing Modes

a) Immediate Addressing b) Direct Addressing
(Instruction contains the operand.) (Instruction contains Memory
address of operand)
Instr Op'n 3
Instr Op'n Addr of A
LOAD #3, .... Operand
LOAD A, ...
c) Indirect Addressing d) Register Indirect Addressing

(Instruction contains Memory (register contains address of operand)
address of address
of operand) Memory
Operand Instr Op'n R2 . . .
Instr Op'n
Operand Addr R2 Operand Addr.
LOAD (A), ... Operand
LOAD [R2], ...
Address of address of A
e) Displacement (Based) (Indexed) Addressing f) Relative Addressing

(address of operand = register +constant) (Address of operand = PC+constant)
Memory Memory
Instr Op'n R2 4 Instr Op'n 4
+ + Operand
Operand
R2 PC
LOAD 4[R2], ... Operand Addr. LOADRel 4[PC], ... Operand Addr.
Example Computer, SRC

Simple RISC Computer
• 32 general purpose registers of 32 bits

• 32 bit program counter, PC and instruction reg., IR
• 232 bytes of memory address space
The SRC CPU Main memory
31 0 7 0
R0 32 32-bit 0
general 32
2
purpose bytes
registers of
R31 main R[7] means contents
memory of register 7
PC
M[32] means contents
IR 232 – 1 of memory location 32
SRC Characteristics
• Load-store design: only way to access memory is through load

and store instructions
• Only a few addressing modes are supported
• ALU Instructions are 3-register type
• Branch instructions can branch unconditionally or
conditionally on whether the value in a specified register is = 0,
<> 0, >= 0, or < 0.
• Branch-and-link instructions are similar, but leave the value of
current PC in any register, useful for subroutine return.
• All instructions are 32-bits (1-word) long.
SRC Basic Instruction Formats
• There are three basic instruction format types

• The number of register specifier fields and length of the
constant field vary
• Other formats result from unused fields or parts
31 27 26 22 21 0
op ra c1 Type 1
31 27 26 22 21 17 16 0
op ra rb c2 Type 2
31 27 26 22 21 17 16 12 11 0
op ra rb rc c3 Type 3
• Details of formats:
Instruction formats Example
Fig 2.9 1. Id, st, la, 31 27 26 22 21 17 16 0

Id r3, A (R[3] = M[A])
Id r3, 4(r5) (R[3] = M[R[5] + 4])
Cont’d. addi, andi, ori
Op ra rb c2
addi r2, r4, #1 (R[2] = R[4] +1)
Total of 7 31 2726 22 21 0
Idr r5, 8 (R[5] = M[PC + 8])
2. Idr, str, lar Op ra
Detailed c1 Iar r6, 45 (R[6] = PC + 45)
Formats 31 27 26 22 21 17 16 0
3. neg, not Op ra rc unused neg r7, r9 (R[7] = – R[9])
unused
31 27 26 22 21 17 16 12 11 2 0
brzr r4, r0
4. br Op rb rc (c3) unused Cond (branch to R[4] if R[0] == 0)
unused
31 27 26 22 21 17 16 12 11 2 0 brlnz r6, r4, r0

5. brl Op ra rb rc (c3) unused Cond (R[6] = PC; branch to R[4] if R[0] ≠ 0)
31 27 26 22 21 17 16 12 11 0
6. add, sub,
Op ra rb rc unused add r0, r2, r4 (R[0] = R[2] + R[4])
and, or
31 27 26 22 21 17 4 2 0
shr r0, r1, #4
7a Op ra rb (c3)
(c3) unused Count (R[0] = R[1] shifted right by 4 bits
7. shr, shra
shl, shic 31 27 26 22 21 17 16 12 4 0
shl r2, r4, r6
7b Op ra rb rc (c3)
(c3) unused 00000 (R[2] = R[4] shifted left by count in R[6])
31 27 26 0
8. nop, stop Op unused stop
Tbl 2.4 Example Load & Store

Instructions: Memory Addressing
• Address can be constant, constant+register, or constant+PC
• Memory contents or address itself can be loaded
Instruction op ra rb c1 Meaning Addressing Mode

ld r1, 32 1 1 0 32 R[1] ← M[32] Direct
ld r22, 24(r4) 1 22 4 24 R[22] ← M[24+R[4]] Displacement
st r4, 0(r9) 3 4 9 0 M[R[9]] ← R[4] Register indirect
la r7, 32 5 7 0 32 R[7] ← 32 Immediate
ldr r12, -48 2 12 – -48 R[12] ← M[PC -48] Relative
lar r3, 0 6 3 – 0 R[3] ← PC Register (!)
(note use of la to load a constant)
Assembly Language Forms of

Arithmetic and Logic Instructions
Format Example Meaning

neg ra, rc neg r1, r2 ;Negate (r1 = -r2)
not ra, rc not r2, r3 ;Not (r2 = r3´ )
add ra, rb, rc add r2, r3, r4 ;2’s complement addition
sub ra, rb, rc sub r3,r4,r5 ;2’s complement subtraction
and ra, rb, rc and r1,r2,r3 ;Logical and
or ra, rb, rc or r2, r5, r6 ;Logical or
addi ra, rb, c2 addi r1, r3, #1 ;Immediate 2’s complement add
andi ra, rb, c2 andi r1,r2,#128 ;Immediate logical and
ori ra, rb, c2 ori r3,r1,#7 ;Immediate logical or
• Immediate subtract not needed since constant in addi

may be negative
Branch Instruction Format

There are actually only two branch instructions:
br rb, rc, c3<2..0> ;branch to R[rb] if R[rc] meets
; the condition defined by c3<2..0>
brl ra, rb, rc, c3<2..0> ; R[ra] ← PC; branch as above
• It is c3<2..0>, the 3 lsbs of c3, that governs what the branch condition is:
lsbs condition Assy language form Example

000 never brlnv brlnv r6
001 always br, brl br r5, brl r5
010 if rc = 0 brzr, brlzr brzr r2, r4, r5
011 if rc ≠ 0 brnz, brlnz
100 if rc ≥ 0 brpl, brlpl
101 if rc < 0 brmi, brlmi
• Note that branch target address is always in register R[rb].

•It must be placed there explicitly by a previous instruction.
Tbl. 2.6 Branch Instruction Examples

Ass’y Example instr. Meaning op ra rb rc c3 Branch
lang. 〈2..0〉 Cond’n.
brlnv brlnv r6 R[6] ← PC 9 6 — — 000 never
br br r4 PC ← R[4] 8 — 4 — 001 always
brl brl r6,r4 R[6] ← PC; 9 6 4 — 001 always
PC ← R[4]
brzr brzr r5,r1 if (R[1]=0) 8 — 5 1 010 zero
PC ← R[5]
brlzr brlzr r7,r5,r1 R[7] ← PC; 9 7 5 1 010 zero
if (R[1]=0) PC ← R[5]
brnz brnz r1, r0 if (R[0]≠0) PC← R[1] 8 — 1 0 011 nonzero
brlnz brlnz r2,r1,r0 R[2] ← PC; 9 2 1 0 011 nonzero
if (R[0]≠0) PC← R[1]
brpl brpl r3, r2 if (R[2] ≥0) PC← R[3] 8 — 3 2 100 plus
brlpl brlpl r4,r3,r2 R[4] ← PC; 9 4 3 2 plus
if (R[2] ≥0) PC← R[3]
brmi brmi r0, r1 if (R[1]<0) PC← R[0] 8 — 0 1 101 minus
brlmi brlmi r3,r0,r1 R[3] ← PC; 9 3 0 1 minus
if (r1<0) PC← R[0]
Branch Instructions—Example
C: goto Label3
SRC:
lar r0, Label3 ; put branch target address into tgt
reg.
br r0 ; and branch
• • •
Label3 •••
Example of conditional branch
in C: if (X<0) then X = -X;
in SRC:
.org 1000 ;next word will be loaded at address
100010
X: .dw 1 ;reserve 1 word for variable X
.org 5000 ;program will be loaded at location
500010
lar r0, Over ;load address of “false” jump location
ld r1, X ;load value of X into r1
brpl r0, r1 ≥0
;branch to Else if r1≥
neg r1, r1 ;negate value
Over: • • • ;continue
SRC Simulator
• There is a Java-based assembler/simulator for the SRC

that is available from the class web site.
• Run the simulator with the command:
java -classpath SRCTools.jar.zip SRCTools.SRCSim
• This works on both UNIX and your PC.
• On CEC’s UNIX machines, do a “pkgadd mgc” and
then
java -classpath $CLASS/ee362/src/SRCTools_jar.zip SRCTools.SRCSim
• On your own PC, follow the instructions on the
class web page.
Example SRC Simulation
Let’s simulate the conditional branch.

• Use edit to open an editor window.
• Enter your code
• Click on assemble to assemble your code. If all goes
well you will have no errors. If you have errors, fix
them before proceeding.
• Once you have no errors, click on bin->sim to load
your binary file into the simulator.
• Run your simulation by stepping through your code
one line at a time, or click run to run until done.
• Click print to print out the state of the simulator.
RTN (Register Transfer Notation)
• Provides a formal means of describing machine

structure and function
• Is at the “just right” level for machine descriptions
• Does not replace hardware description languages.
• Can be used to describe what a machine does (an
Abstract RTN) without describing how the machine
does it.
• Can also be used to describe a particular hardware
implementation (A Concrete RTN)
RTN Notation (Cont’d.)
• At first you may find this “meta description” confusing,

because it is a language that is used to describe a
language.
• You will find that developing a familiarity with RTN will
aid greatly in your understanding of new machine
design concepts.
• We will describe RTN by using it to describe SRC.
Some RTN Features—

Using RTN to describe a machine’s
static properties
Static Properties
• Specifying registers
• IR〈〈31..0〉〉 specifies a register named “IR” having 32 bits
numbered 31 to 0
• “Naming” using the := naming operator:
• op〈〈4..0〉〉 := IR〈〈31..27〉〉 specifies that the 5 msbs of IR be
called op, with bits 4..0.
• Notice that this does not create a new register, it just
generates another name, or “alias” for an already existing
register or part of a register.
Using RTN to describe

Dynamic Properties
Dynamic Properties
• Conditional expressions:
(op=12) → R[ra] ← R[rb] + R[rc]: ; defines the add instruction
“if” condition “then” RTN Assignment Operator
This fragment of RTN describes the SRC add instruction. It says,

“when the op field of IR = 12, then store in the register specified
by the ra field, the result of adding the register specified by the
rb field to the register specified by the rc field.”
Using RTN to describe the SRC (static)

Processor State
Processor state
PC〈〈31..0〉〉: program counter
(memory addr. of next inst.)
IR〈〈31..0〉〉: instruction register
Run: one bit run/halt indicator
Strt: start signal
R[0..31]〈〈31..0〉〉: general purpose registers
RTN Register Declarations
• General register specifications shows some features of

the notation
• Describes a set of 32 32-bit registers with names R[0] to
R[31]
R[0..31]〈〈31..0〉〉:
Colon separates
Name of statements with
registers no ordering
Register # msb #
in square
brackets lsb# Bit # in
.. specifies angle
a range of brackets
indices
Memory Declaration:
RTN Naming Operator
• Defining names with formal parameters is a powerful

formatting tool
• Used here to define word memory (big endian)
Main memory state

Mem[0..232 - 1]〈〈7..0〉〉: 232 addressable bytes of memory
M[x]〈〈31..0〉〉:= Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]:
Dummy Naming Concatenation All bits in

parameter operator operator register if no
bit index given
RTN Instruction Formatting Uses

Renaming of IR Bits
Instruction formats
op〈〈4..0〉〉 := IR〈〈31..27〉〉: operation code field
ra〈〈4..0〉〉 := IR〈〈26..22〉〉: target register field
rb〈〈4..0〉〉 := IR〈〈21..17〉〉: operand, address index, or
branch target register
rc〈〈4..0〉〉 := IR〈〈16..12〉〉: second operand, conditional
test, or shift count register
c1〈〈21..0〉〉 := IR〈〈21..0〉〉: long displacement field
c2〈〈16..0〉〉 := IR〈〈16..0〉〉: short displacement or
immediate field
c3〈〈11..0〉〉 := IR〈〈11..0〉〉: count or modifier field
Specifying dynamic properties of SRC:

RTN Gives Specifics of Address
Calculation
Effective address calculations (occur at runtime):
disp〈〈31..0〉〉 := ((rb=0) → c2〈〈16..0〉〉 {sign extend}: displacement

(rb≠≠0) → R[rb] + c2〈〈16..0〉〉 {sign extend, 2's comp.} ): address
rel〈〈31..0〉〉 := PC〈〈31..0〉〉 + c1〈〈21..0〉〉 {sign extend, 2’s comp.}: relative
address
• Renaming defines displacement and relative addrs.
• New RTN notation is used
• condition → expression means if condition then
expression
• modifiers in { } describe type of arithmetic or how short
numbers are extended to longer ones
• arithmetic operators (+ - * / etc.) can be used in expressions
• Register R[0] cannot be added to a displacement
Detailed Questions Answered by the

RTN for Addresses
• What set of memory cells can be addressed by direct

addressing (displacement with rb=0)
• If c2〈〈16〉〉=0 (positive displacement) absolute
addresses range from 00000000H to 0000FFFFH
• If c2〈〈16〉〉=1 (negative displacement) absolute
addresses range from FFFF0000H to FFFFFFFFH
• What range of memory addresses can be specified by
a relative address
• The largest positive value of C1〈〈21..0〉〉 is 221-1 and
its most negative value is -221, so addresses up to
221-1 forward and 221 backward from the current PC
value can be specified
• Note the difference between rb and R[rb]
Instruction Interpretation: RTN

Description of Fetch/Execute
• Need to describe actions (not just declarations)

• Some new notation
Logical NOT
Logical AND
instruction_interpretation := (
¬Run∧ ∧Strt → Run ← 1:
Run → (IR ← M[PC]: PC ← PC + 4; instruction_execution) );
Register transfer Separates statements

that occur in sequence
RTN Sequence and Clocking
• In general, RTN statements separated by : take place

during the same clock pulse
• Statements separated by ; take place on successive
clock pulses
• This is not entirely accurate since some things written
with one RTN statement can take several clocks to
perform
• More precise difference between : and ;
• The order of execution of statements separated by
: does not matter
• If statements are separated by ; the one on the left
must be complete before the one on the right starts
More about Instruction Interpretation

RTN
• In the expression IR ← M[PC]: PC ← PC + 4; which value

of PC applies to M[PC] ?
• The rule in RTN is that all right hand sides of “:” -
separated RTs are evaluated before any LHS is
changed
• In logic design, this corresponds to “master-slave”
operation of flip-flops
• Incomplete Specification:
• We see what happens when Run is true and when Run
is false but Strt is true. What about the case of Run
and Strt both false?
• Since no action is specified for this case, the RTN
implicitly says that no action occurs in this case
Individual Instructions
• instruction_interpretation contained a forward

reference to instruction_execution
• instruction_execution is a long list of conditional
operations
• The condition is that the op code specifies a given
inst.
• The operation describes what that instruction does
• Note that the operations of the instruction are done
after (;) the instruction is put into IR and the PC has
been advanced to the next inst.
RTN Instruction Execution for Load and

Store Instructions
instruction_execution := (
ld (:= op= 1) → R[ra] ← M[disp]: load register
ldr (:= op= 2) → R[ra] ← M[rel]: load register relative
st (:= op= 3) → M[disp] ← R[ra]: store register
str (:= op= 4) → M[rel] ← R[ra]: store register relative
la (:= op= 5 ) → R[ra] ← disp: load displacement address
lar (:= op= 6) → R[ra] ← rel: load relative address
• The in-line definition (:= op=1) saves writing a separate

definition ld := op=1 for the ld mnemonic
• The previous definitions of disp and rel are needed to
understand all the details
SRC RTN—The Main Loop

ii := instruction_interpretation:
ie := instruction_execution :
ii := ( ¬Run∧ ∧Strt → Run ← 1:
Run → (IR ← M[PC]: PC ← PC + 4;
ie) );
ie := (
ld (:= op= 1) → R[ra] ← M[disp]: Big switch
ldr (:= op= 2) → R[ra] ← M[rel]: statement
... on the opcode
stop (:= op= 31) → Run ← 0:
); ii
Thus ii and ie invoke each other, as coroutines.
Use of RTN Definitions:

Text Substitution Semantics
ld (:= op= 1) → R[ra] ← M[disp]:

disp〈〈31..0〉〉 := ((rb=0) → c2〈〈16..0〉〉 {sign extend}:
(rb≠ ≠0) → R[rb] + c2〈〈16..0〉〉 {sign extend, 2's comp.} ):
ld (:= op= 1) → R[ra] ← M[

((rb=0) → c2〈〈16..0〉〉 {sign extend}:
≠0) → R[rb] + c2〈〈16..0〉〉 {sign extend, 2's comp.} ):
(rb≠
]:
• An example:
• If IR = 00001 00101 00011 00000000000001011
• then ld → R[5] ← M[ R[3] + 11 ]:
RTN Descriptions of SRC Branch

Instructions
• Branch condition determined by 3 lsbs of inst.

• Link register (R[ra]) set to point to next inst.
cond := ( c3〈〈2..0〉〉=0 → 0: never

c3〈〈2..0〉〉=1 → 1: always
c3〈〈2..0〉〉=2 → R[rc]=0: if register is zero
c3〈〈2..0〉〉=3 → R[rc]≠≠0: if register is nonzero
c3〈〈2..0〉〉=4 → R[rc]〈〈31〉〉=0: if positive or zero
c3〈〈2..0〉〉=5 → R[rc]〈〈31〉〉=1 ): if negative
br (:= op= 8) → (cond → PC ← R[rb]): conditional branch
brl (:= op= 9) → (R[ra] ← PC:
cond → (PC ← R[rb]) ): branch and link
RTN for Arithmetic and Logic
add (:= op=12) → R[ra] ← R[rb] + R[rc]:

addi (:= op=13) → R[ra] ← R[rb] + c2〈〈16..0〉〉 {2's comp. sign
ext.}:
sub (:= op=14) → R[ra] ← R[rb] - R[rc]:
neg (:= op=15) → R[ra] ← -R[rc]:
and (:= op=20) → R[ra] ← R[rb] ∧ R[rc]:
andi (:= op=21) → R[ra] ← R[rb] ∧ c2〈〈16..0〉〉 {sign extend}:
or (:= op=22) → R[ra] ← R[rb] ∨ R[rc]:
ori (:= op=23) → R[ra] ← R[rb] ∨ c2〈〈16..0〉〉 {sign extend}:
not (:= op=24) → R[ra] ← ¬R[rc]:
• Logical operators: and ∧ or ∨ and not ¬
RTN for Shift Instructions
• Count may be 5 lsbs of a register or the instruction

• Notation: @ - replication, # - concatenation
(c3〈〈4..0〉〉=0) → R[rc]〈〈4..0〉〉:
n := (
(c3〈〈4..0〉〉≠0) → c3〈〈4..0〉〉 ):
shr (:= op=26) → R[ra]〈〈31..0〉〉 ← (n @ 0) # R[rb]〈〈31..n〉〉:
shra (:= op=27) → R[ra]〈〈31..0〉〉 ← (n @ R[rb]〈〈31〉〉) # R[rb]〈〈31..n〉〉:
shl (:= op=28) → R[ra]〈〈31..0〉〉 ← R[rb]〈〈31-n..0〉〉 # (n @ 0):
shc (:= op=29) → R[ra]〈〈31..0〉〉 ← R[rb]〈〈31-n..0〉〉 # R[rb]〈〈31..32-n〉〉:
Example of Replication and

Concatenation in Shift
• Arithmetic shift right by 13 concatenates 13 copies of

the sign bit with the upper 19 bits of the operand
shra r1, r2, 13
R[2]= 1001 0111 1110 1010 1110 1100 0001 0110
13@R[2]〈〈31〉〉 # R[2]〈〈31..13〉〉
R[1]= 1111 1111 1111 1 100 1011 1111 0101 0111
Assembly Language for Shift
• Form of assembly language instruction tells whether to

set c3=0
shr ra, rb, rc ;Shift rb right into ra by 5 lsbs of rc

shr ra, rb, count ;Shift rb right into ra by 5 lsbs of inst
shra ra, rb, rc ;AShift rb right into ra by 5 lsbs of rc
shra ra, rb, count ;AShift rb right into ra by 5 lsbs of inst
shl ra, rb, rc ;Shift rb left into ra by 5 lsbs of rc
shl ra, rb, count ;Shift rb left into ra by 5 lsbs of inst
shc ra, rb, rc ;Shift rb circ. into ra by 5 lsbs of rc
shc ra, rb, count ;Shift rb circ. into ra by 5 lsbs of inst
End of RTN Definition of

instruction_execution
nop (:= op= 0) → : No operation

stop (:= op= 31) → Run ← 0: Stop instruction
); End of instruction_execution
instruction_interpretation.
• We will find special use for nop in pipelining

• The machine waits for Strt after executing stop
• The long conditional statement defining
instruction_execution ends with a direction to go repeat
instruction_interpretation, which will fetch and execute the
next instruction (if Run still =1)
Confused about RTN and SRC?

• SRC is a Machine Language
• It can be interpreted by either hardware or software
simulator.
• RTN is a Specification Language
• Specification languages are languages that are
used to specify other languages or systems—a
metalanguage.
• Other examples: LEX, YACC, VHDL, Verilog
Figure 2.10 may help clear this up...
Fig 2.10 The Relationship of RTN to SRC

SRC specification written in RTN
RTN compiler
Generated processor
SRC program Data output

SRC interpreter
and data or simulator
A Note about Specification Languages

• They allow the description of what without having to specify how.
• They allow precise and unambiguous specifications, unlike natural
language.
• They reduce errors:
• errors due to misinterpretation of imprecise specifications
written in natural language
• errors due to confusion in design and implementation - “human
error.”
• Now the designer must debug the specification!
• Specifications can be automatically checked and processed by
tools.
• An RTN specification could be input to a simulator generator
that would produce a simulator for the specified machine.
• An RTN specification could be input to a compiler generator that
would generate a compiler for the language, whose output could
be run on the simulator.
Addressing Modes Described in RTN

(Not SRC)
Target register
Mode name Assembler RTN meaning Use
Syntax
Register Ra R[t] ← R[a] Tmp. Var.
Register indirect (Ra) R[t] ← M[R[a]] Pointer
Immediate #X R[t] ← X Constant
Direct, absolute X R[t] ← M[X] Global Var.
Indirect (X) R[t] ← M[ M[X] ] Pointer Var.
Indexed, based, X(Ra) R[t] ← M[X + R[a]] Arrays, structs
or displacement
Relative X(PC) R[t] ← M[X + PC] Vals stored w pgm
Autoincrement (Ra)+ R[t] ← M[R[a]]; R[a] ← R[a] + 1 Sequential
Autodecrement - (Ra) R[a] ← R[a] - 1; R[t] ← M[R[a]] access.
Fig. 2.11 Register transfers can be

mapped to Digital Logic Circuits.
• Implementing the RTN statement A ← B
B
LOAD
CLK
A
Fig. 2.12 Multiple Bit Register Transfer

• Implementing A〈〈m..1〉〉 ← B〈〈m..1〉〉
Abbreviated notation
Fig. 2.13 Data Transmission View of

Logic Gates
• Logic gates can be used to control the transmission of data:
data gate→data
gate→0
gate
data 1
Data gate
data 2 data1(2),
provided
data2(1)
data 1 is zero
data control→data data 2
control→data Data merge

control
Controlled complement
Fig. 2.14 Multiplexer as a 2 Way Gated

Merge
• Data from multiple sources can be selected for

transmission
x
m
x m
Gx
x y
m
y m
Gy
y
Time
Fig. 2.15 m-bit Multiplexer and Symbol

An n-way gated merge An n-way multiplexer with decoder
m
D0 m
G0 D0
m m
D1
m m
D1 m
G1 m
m
Dn–1
m k
Dn–1
Gn–1 Select
m
(a) Multiplexer in terms of gates (b) Symbol abbreviation
• Multiplexer gate signals Gi may be produced by a

binary to one-out-of-n decoder
Fig. 2.16 Separating Merged Data
x 0
m
x y
m
Gx
Time
• Merged data can be separated by gating at the right time

• It can also be strobed into a flip-flop when valid
Fig. 2.17 Multiplexed Register

Transfers using Gates and Strobes
• Selected gate and strobe determine which RT

←C, and B←
• A← ←C can occur together, but not A←
←C, and B←
←D
Fig. 2.18 Open-Collector NAND Gate

Output Circuit
+V
Inputs Output
0v 0v Open (Out = +V) Out
+V
0v +V Open (Out = +V) o.c.
+V
+V 0v Open (Out = +V)
+V +V Closed (Out = 0v)
(a) Open-collector NAND (b) Open-collector NAND (c) Symbol

truth table
Fig. 2.19 Wired AND Connection of

Open-Collector Gates
+V
+V
Out
a b
o.c. o.c.
(a) Wired AND connection (b) With symbols
Switch Wired AND

a b output
Closed(0) Closed(0) 0v (0)

Closed(0) Open (1) 0v (0)
Open (1) Closed(0) 0v (0)
Open (1) Open (1) +V (1)
(c) Truth table
Fig. 2.20 Open Collector Wired OR Bus
• DeMorgan’s OR by not of AND of nots

• Pull-up resistor removed from each gate - open
collector
• One pull-up resistor for whole bus
• Forms an OR distributed over the connection
+V
D0 D1 Dn–1
o.c. o.c. o.c.
G0 G1 Gn–1
Fig. 2.21 Tri-state Gate Internal

Structure and Symbol
+V
Tri-
Data Out Data Out
state
Enable
Enable
(a) Tri-state gate structure (b) Tri-state gate symbol
Enable Data Output

0 0 Hi-Z
0 1 Hi-Z
1 0 0
1 1 1
(c) Tri-state gate truth table
Fig. 2.22 Registers Connected by a

Tri-state Bus
• Can make any register transfer R[i]←←R[j]

≠j
• Can’t have Gi = Gj = 1 for i≠
• Violating this constraint gives low resistance path from power
supply to ground—with predictable results!
Fig. 2.23 Registers and Arithmetic

Connected by One Bus
Example
Abstract RTN
R[3] ← R[1]+R[2];
Concrete RTN Combinational

Y ← R[2]; Logic—no
Z ← R[1]+Y; memory
R[3] ← Z;
Control Sequence
R[2]out, Yin;
R[1]out, Zin;
Zout, R[3]in;
Notice that what could be described in one step in the abstract RTN took
three steps on this particular hardware
RT’s Possible with the One Bus

Structure
• R[i] or Y can get the contents of anything but Y
• Since result different from operand, it cannot go on the bus that is
carrying the operand
• Arithmetic units thus have result registers
• Only one of two operands can be on the bus at a time, so adder has
register for one operand
• R[i] ← R[j] + R[k] is performed in 3 steps: Y← ←R[k]; Z← ←R[j] + Y;
←Z;
R[i]←
• R[i] ← R[j] + R[k] is high level RTN description
←R[k]; Z←
• Y← ←R[j] + Y; R[i]←←Z; is concrete RTN
• Map to control sequence is: R[2]out, Yin; R[1]out, Zin; Zout, R[3]in;
From Abstract RTN to Concrete RTN to

Control Sequences
• The ability to begin with an abstract description, then

describe a hardware design and resulting concrete RTN
and control sequence is powerful.
• We shall use this method in Chapter 4 to develop various
hardware designs for SRC
Chapter 2 Summary
• Classes of computer ISAs

• Memory addressing modes
• SRC: a complete example ISA
• RTN as a description method for ISAs
• RTN description of addressing modes
• Implementation of RTN operations with digital logic
circuits
• Gates, enables, and multiplexers

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Computer Architecture and

The General Purpose Machine

Alan Turing showed that an abstract computer,

The user sees software, speed, storage

MC68000 Assembly Language Machine Language

MOVE.W D4, D5 0011 101 000 000 100

ADDI.W #9, D2 00000001 10 111 100

Table 1.2 Two Motorola MC68000 instructions

It is the basic operating principle for every computer.

Points to consider when analyzing

Interconnections are very important to

An implementation domain is the collection of

Possible implementation domains:

Relay Computer: 1930s

Chapter 2: Machines, Machine

Instruction sets, SRC, RTN, and the mapping of register

• 2.1 Classification of Computers and Instructions

What are the components of an ISA?

Fig. 2.1 Programmer’s Models of

What Must an Instruction Specify?

Instructions Can Be Divided into 3

Tbl. 2.1 Examples of Data Movement

Instruction Meaning Machine

lwzR3, A Move 32 bits from mem. Loc. A to reg. R3 PPC601

IN A1, KBD Load a byte from port KBD to Accum. Pentium

LEA.L (A0), A2 Load address pointed to by A0 into A2 M68000

• Lots of variation, even with one instruction type

Tbl 2.2 Examples of ALU

DEC R2 Decrement the 16 bit value stored in reg R2 DEC DP11

SHL AX, 4 Shift the 16-bit calue in AX left by 4 bits 8086

•Notice again the complete dissimilarity of both syntax and semantics.

Tbl 2.3 Examples of Branch

Instruction Meaning Machine

CPU Registers Associated with Flow of

• Program counter usually locates next inst.

HLL Conditionals Implemented by

• Conditions are computed by arithmetic instructions

C language Assembly language

CMP.W #5, NUM ;the comparison

CPU Registers may have a

Stack Arithmetic Address General Purpose

St a ck Ma chine Accum ula t o r Ma chine Ge ne ra l Re g is t e r

3, 2, 1, & 0 Address ISAs

Fig. 2.2 The 4 Address Instruction

• Explicit addresses for operands, result & next instruction

Fig 2.3 The 3 Address Instruction

• Address of next instruction kept in processor state register—

Fig. 2.4 The 2 Address Instruction

Fig. 2.5 1 Address Instructions

Fig. 2.6 The 0 Address Instruction

Memory CPU push Op1 (TOS ← Op1)

• Uses a push down stack in CPU

Example 2.1 Expression evaluation for 3-

Fig. 2.7 General Register Machines (1

load load R8, Op1 (R8 ← Op1)

• It is the most common choice in today’s general purpose

Real Machines are Not So Simple

• Most real machines have a mixture of 3, 2, 1, 0, 1 1/2

• The 3-address machines have the shortest code

• An addressing mode is hardware support for a useful way of

HLL Examples of Structured Addresses

• C language: rec -> count

• count is a field name: fixed byte offset, say 24 Rec →