The Design of 13 bits I� ADC for a mutual-capacitance large touch screen controller

Ihsan F. I. Albittar' 2, Jiho Kim', HyungWon Kim'

'
Dept. of Electronics Engineering, Chungbuk National University
Cheongju, South Korea
Mixel Incorporation, California, USA2

Abstract the quantization noise, and push it to even higher frequencies

Touch sensing circuits for large touch screens require high than do the lower-order modulators. Equation (1) is the SNR of
resolution ADCs with high data rate for accurate and fast touch a modulator loop architecture, which is a function of
detection. This paper presents a third-order I� ADC design over-sampling ratio (OSR) ,modulator order (L), and the B-bit
with an input bandwidth of 480 KHz at 61.44 MHz sampling quantizer[2]. For the target ADC, we chose L = 3 to meet the
frequency, the SNR and ENOB are measured to be 85 dB and required SNR specifications.
13 bits respectively. We present an efficient mixed signal
design methodology consisting of circuit design, integration, SNR = (20L+1 O)log OSR + 1Olog(2L+1)+6.02B+1. 76 - 9.94L (1)
and verification with analog and digital simulations. Using the
proposed design methodology, the target I� ADC design is Fig. 3 shows our analog modulator architecture. The

implemented with Dongbu 0.I8-l1m BDCMOS technology. modulator design consists of three parasitic-insensitive

The design results show its suitability for large switched-capacitor integrators, a comparator that serves as a

mutual-capacitance touch screen controller applications. I-bit ADC, and a distributed two-level (I-bit) DAC. The
modulator operates on a two-phase nonoverlapping clock.

Keywords- Sigma-delta ADC, touch screen controller, desgin During phase 1, switches SI and S3 are on, while during phase
methodology. 2, switches S2 and S4 are on [3].
.". .". . ,.,
.

T T T
Introduction
Nowadays, capacitive touch screens are the most popular
touch screen panels (TSP). Among different types of capacitive
TSPs, projected mutual capacitance TSPs are most widely used
for the middle-sized and small-sized mobile products. They
have superior visibility and durability and also exhibit a
multi-touch function. In mutual capacitance TSPs, touch
detection is detennined by measuring the change in the mutual Fig. 3 The proposed third-order analog modulator
capacitance [1] [5] [6] [7] which is susceptible to noise. Such
TSPs, therefore, often have a very low signal-to-noise ratio The modulator output is filtered by a digital decimation filter.
(SNR), and so require high resolution ADCs to distinguish the In our design, we chose a 4th order decimation filter. It has
mutual capacitance changes from their high ambient noise. Fig. multi-functions, which includes to achieve a multi-bit digital
1 shows a TSP and its excitation and sensing circuits with an output by down-sampling the signal, to attenuate the
ADC performing detection operations. Among variety of ADC quantization noise and remove aliases from the side band, and
architectures, Sigma-Delta (I�) ADC is often considered as as a result, to complete the process of analog to digital
K
best for high resolution results. conversion [3]. Sinc filter has area advantage since it
eliminates the needs for digital multipliers [4] lead to a
K
relatively small size. We implemented a Sinc filter by
cascading K stages of accumulators operating at the high
sample rate, followed by K stages of cascaded differentiators
J operating at the lower sample rate[4]. Fig. 4 shows the digital
decimation filter that we implemented for the presented I�
Fig. 1 TSP and its excitation and sensing circuits with ADC ADC design.
M
Archeticture
Fig. 2 shows a general structure of a I� ADC. We designed
the analog modulator with a third-order fully differential Fig. 4 The proposed digital filter block diagram
switched-capacitor implementation, which provides good
common-mode noise rejection and cancelation for the even Proposed Design Methodology
order hannonics. In Fig. 5, we present our design methodology of I� ADC,
� An"Og
Input
Digital
Output
which use two flows of simulations: Analog Simulation and
Signal digital simulation. Analog simulation uses Cadence Spectre for
I� modulator and VerilogA for decimation filter, whereas
Fig. 2. Block diagram of sigma-delta ADC
digital simulation uses Verilog for decimation filter
implementation and MATLAB for verification of the output
Also, switched-capacitor implementation is used for its high
correctness. Using this automated analog-digital mixed signal
resolution superiority. Since the multi-order modulators shape

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design methodology, we can converge the real design and
target spec quickly and shorten the overall design cycles.
is the result of the analog simulation flow of our design
methodology, which integrated VerilogA model of decimation
fIlter with the analog modulator design. The complete ADC
performance is summarized in Table (1).
..... v 5� ........ __...... , <or S,,"",,"_C"__ AOC 0.. ..
,....

..... NC.,
Fig. 10 The output spectrum for the whole system
Fig. 5 The proposed design methodology
Table (1) : Summary of L Ll ADC
Implementation and Simulation Results Parameters Value
We implemented the target III ADC design using Dongbu Signal bandwidth 480KHz
0.18-�m BDCMOS technology, and measured performance
Sampling Frequency 61.44 MHz
Over sampling ratio 128
using Cadence Spectre simulations. Simulation results in Fig. 6
Modulator order 3
show that the third order III modulator can operate at a
Filter order 4
sampling frequency 61.44 MHz for a sin wave input of 800 ENOB 13 bits
mVpp and 480 KHz bandwidth. Fig. 7 shows a frequency SNR 85 dB
domain spectral power analysis of the modulator's output, SINAD 84 dB
which confirms that the quantization noise is shifted towards SFDR 92 dB
higher frequency, which is to be removed by the decimation THD -91 dB
fIlter. Conclusion
We designed a high speed high resolution III ADC design
e;
.......
using an efficient design methodology. We have demonstrated
that the implemented ADC meets the stringent specifications of
target large touch screen (23") controller SoC (Sample rate of
61.44MHz, SNR of 85dB, input B/W of 480 KHz). We also
showed that our design methodology verifies the performance
of mixed signal designs in analog and digital simulations
without converting the whole digital circuits to analog circuits,
and thus allowing fast design cycles. We actually used this III

\ ADC IP in the sensing block of a touch screen controller SoC

implemented in Dongbu 0.18um BDCMOS technology.

Acknowledgment
Fig. 7 Spectral power analysis of the modulator's output This research was supported by the MSIP Korea, under the
Human Resource Development Project for SoC
Fig. 8 shows the digital outputs in decimal numbers. Our (NIPA-20 14-H0601-14-100 I).
proposed design methodology (Digital simulation flow) proved
that these digital outputs (red wave) exactly match the input References
(blue wave) by generating interpolated wave form (black wave) [I] U. Jang, T.W. Cho, H.G. Jang, S. Lee, H.W. Kim, "Architecture of
and compare it with the input. Fig. 9 shows the verification
Multi Purpose Touch Screen Controller with Self Calibration
Scheme", lEEK Fall Conj, pp. 162-166, 2013
process of the digital flow of our design methodology, which
[2] Chris Hutchens, Chia-Ming Liu "Powlbit optimization of 8-I ADCs
proved that the digital output of the whole ADC matches up using multi-bit quantizers", IEEE Conf., 2002.
with the [3] Steven R. Norsworthy ,Richard Schreier ,Gabor C. Ternes,
"Delta-Sigma Data Converters," IEEE Press, 1997.
[4] Texas Instruments ,"Combining the ADSI202 with an FPGA Digital
Filter for Current Measurement in Motor Control
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Domain Concurrent Sensing Technique for Large Touch
Fig. 8 Decimal numbers represent the digital output bits from the
Screen Panels", lEEK Fall., pp. 55'58, Nov. 2013.
decimation filter
--",S'n ___
[6] M.G.A. Mohamed, U. Jang, I. Seo, T.W. Cho, H.G. Jang, S.
-Pig""" 0..0".... RII..
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[7] I. Seo, U. Jang, M.G.A. Mohamed, T.W. Cho, H.G. Jang, S.
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Screen Panels," IEEE Infl Symp. On Consumer Electronics
Fig. 10 shows the spectral power of the decimation filter. This 2014.
978-1-4799-5127-71$31.00 (02014IEEE - 109 - ISOCC2014
Authorized licensed use limited to: ADI Research Library (ARL). Downloaded on August 02,2023 at 06:20:44 UTC from IEEE Xplore. Restrictions apply.