Mekelle University-MIT

Department of Computer Science & Engineering

Computer Organization & Architecture Final Exam Max. Marks: 40% Time allotted: 2:30
Part I: General Questions (8%, 2pts each)
1. The data path issues control signals to the ALU and register sets. (True/False)
2. In fully associative mapping a given line can be permanently dedicated to a particular main
memory block. (True/False)
3. Which of the following statements are correct (choosing more than one is possible)
A) A microinstruction specifies only one micro-operation
B) When each control bit in the microinstruction corresponds to exactly one control line, the
length of microinstruction could get bigger.
C) The length of a microinstruction could be reduced if control lines are coded in specific fields
in the microinstruction.
D) Content of control buffer register loads the control word address to the control address
register
4. Explain the differences between tightly Coupled and Loosely Coupled Systems in
multiprocessors system?
Part II: Design type Questions (32 %)
5. Consider 64kx1 memory is organized as 256x256 array of memory cells. If the memory cell in
the 5039 (decimal number) location is going to be accessed. Determine the row and column
addresses for the selected memory cell. (Give the addresses in hexadecimal representations) [2
pts]
6. Consider 64 bits Virtual address, 4GB RAM and word addressable. Assume one word is 32 bits
wide and one frame is 64K words. [6 pts]
a. Determine the minimum main memory address bus width
b. Determine the number of pages in the virtual memory
c. Determine the number of frames in the main memory
d. If page number 19 is mapped to frame number 36 (consider the page and frame numbers are
decimal numbers) and the page offset is 4D8FH (in hexadecimal), then determine the
physical address and the virtual address?
7. Consider a memory system that uses a 32-bits main memory address to address at the byte level
(one word is one byte), and a cache that uses a 32-byte line size. Assuming a direct mapped cache
and 20 bits are used for identifying specific blocks assigned to each cache line. [6 pts]
a. Determine the number of main memory addressable units (locations)
b. Determine the number of blocks in main memory
c. Determine the number of lines in cache

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July 09, 2019
 Mekelle University-MIT
Department of Computer Science & Engineering
Computer Organization & Architecture Final Exam Max. Marks: 40% Time allotted: 2:30
d. Determine Size of tag field
e. If 4-way set associative mapping is to be used, determine the number of main memory blocks
assigned for each set in the cache memory.
8. Consider three control signals A, B, and C in a two-bus organized CPU. The CPU has three types
of instructions in its instruction set namely inst-x, inst-y, and inst-z. Control signal A is
activated during the first period (step) when instructions inst-x or inst-z are to be executed,
Control signal B is activated in the first period when instruction inst-y is to be executed or during
the second period when inst-x or inst-y is to be executed, and control signal C is activated in the
second period only when instruction inst-x or inst-y is to be executed. [4 pts]
a. Write the Boolean expressions for control signals A, B and C
b. Implement the Boolean expressions for the control signals using logic gates
9. Assume a given computer uses a microprogrammed control unit with 20 bits microinstruction
width divided in to four fields. The fields are two operation fields namely, F1 and F2 with 4 bits
each, condition fields with 4 bits, and the remaining bits for the address field. [6 pts]
a. Determine the number of micro operations that can be specified by F1
b. Determine the maximum number of simultaneous micro operations that can be chosen for a
microinstruction
c. Determine the size of the control memory
10. Consider the following operation in a simple pipelined system.
(Aj-Bj) * Cj+Dj for j=1, 2, .... 5 Assume that the ALU has only one multiplier, one adder and one
subtractor units. [8 pts]
a. Decompose the above operation into a set of segments (sub-operations) so that they can be
processed concurrently.

b. Show the computations in the simple pipelined system.

c. Compare the number of clock periods required for computation in the pipelined and non-
pipelined systems.

d. Assuming the clock periods in the pipelined and non-pipelined are the same, determine the
actual speed –up of the pipeline. If the number of tasks (j is very large say 1000), what will be the
maximum speed-up of the pipelined system?

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