1 Find the octal equivalent for the given decimal number (149)10.

2 Simplify the Boolean function xy+x 'z+yz to a minimum number of literals.

3 What is meant by combinational circuits? Give examples.
4 What is a parity bit?
5 Find the minimum number of flip flops required to build a Modulo N counter.
6 Draw the master slave configuration using D-flip flop.
7 Differentiate between critical and non-critical race in asynchronous sequential
circuits.
8 What is meant by fundamental mode sequential circuit?
9 Define fan in and fan out of a gate?
10 Write the difference between EPROM and EEPROM.
11 Convert the decimal number 431 to binary.
12 State Demorgan’s theorem.
13 What is an encoder?
14 State the difference between parity generator and parity checker.
15 How are the outputs of Mealy model and Moore model decided?
16 What is a universal shift register?
17 When does a race condition exist in an asynchronous sequential circuit?
18 What is the cause of an essential hazard?
19 Define noise margin.
20 List the types of ROMs with their expansion.

Unit 1
1 Minimize the expression (0,1,3,7,8,9, 11, 15) using tabulation method.(13 M)
2 i. Simplify the four variable Boolean function (0, 2, 3, 5, 7, 8, 9, 10, 11, 13,
15) and find the prime implicants and essential prime implicants.
ii. Express the Boolean function F=xy+x'z as Maxterms. (6 M)
3 Simplify the following Boolean Function F = ∑m (0,2,3,5,7,9,11,13,14) using Quine
Mccluskey method and verify the result using K map. (13 M)
4 Simplify the following Boolean expression using K map and implement it using
Gates
I. Y=⅀m (3,6,7,8,10,12,14,17,19,20,21,24,25,27,28) (7 M)
Y=⅀m (1,5,7,13,14,15,17,18,21,22,25,29) + ⅀d (6,9,19,23,30) (6 M)
5 Design the binary to gray code converter and draw the simplified logic diagram in
sum-of-product form. (15 M)
Unit 2
1 i. Explain the working of 3-bit even parity generator and checker. (7 M)
ii. Illustrate the operation of priority encoder. (6 M)
2 i. Design a full adder and implement in sum-of-product form. (7 M)
ii. Construct the 4 x 16 decoder with two 3 x 8 decoders. (6 M)
3 Explain the working of the following circuits with neat diagrams and equations.
I. Decoder. (7 M)
II. Demultiplexer. (6 M)
4 Explain the working of the following circuits with neat diagrams and equations.
I. Full adder. (7 M)
II. Binary parallel adder. (6 M)
Unit 3
1 Elucidate the analysis and design of clocked sequential circuits with a suitable
example. 13 M)
2 List out the capabilities of a universal shift register. Illustrate the four bit universal
shift register with a function table and explain its working. (13 M)
 3 With Neat diagram explain the following
I. Design a 4-bit synchronous Up/Down counter using JK flip Flop and explain
its working? (7 M)
II. Universal Shift Register. (6 M)
4 I. Explain different triggering methods used in flip flops. (7 M)
Draw the circuit of a JK master slave flip-flop with active high clear and active low
preset and explain its operation. (6 M)
5 Design a counter using JR flip flops with the following binary sequence: 1, 2, 5, 7
and repeat. (15 M)
6 A sequential circuit has two JK Flip-Flops A and B and one output X. The circuit is
described by the following flip-flop input equations
JA = x, KA = B, JB = x and KB = A’.
I. Describe the state equations A(t+1) and B(t+1) by substituting the input
equation for J and K variables
II. Draw the state diagram of the circuit. (15 M)
Unit 4
1 Mention the types of hazard that occur in combinational circuits? Demonstrate the
occurrence of static 0-hazard with a suitable example and find the solution to fix the
static hazard in combinational circuits. (13 M)
2 Taking relevant examples, explain the various types of races that occur in sequential
circuits. Also briefly explain about the race free state (13 M)
3 Eliminate the hazards in the following minterms.
I. F (a, b, c, d) = ⅀ (0,2,4,5,6,7,8,10,11,15) (7 M)
F (a, b, c, d) = ⅀ (1,3,4,5,6,7,9,11,15) (6 M)
4 i. Discuss in detail about Races. (7 M)
Explain the race free state assignment. (6 M)
5 An asynchronous sequential circuit is described by the excitation and output
functions, Y=x1x2’+ (x1+ x2’) y and Z=Y. Draw the logic diagram, transition table,
output map and flow table. (15 M)
Unit 5
1 Design the following sum-of-minterms using PAL.
i. W(A,B,C,D) = ∑(2,12,13)
ii. X(A,B,C,D) = ∑(7,8,9,10,11,12,13,14,15)
iii. Y(A,B,C,D) = ∑(0,2,3,4,5,6,7,8,10,11,15)
iv. Z(A,B,C,D) = ∑(1,2,8,12,13)
2 i. Draw and explain the totempole TTL output configuration. (7 M)
ii. Compare characteristics of RTL, TTL, ECL and CMOS logic. (6 M)
3 I. Draw and explain CMOS logic circuits. (7 M)
Explain a TTL gate with totem pole output. (6 M)
4 I. Using 64 x 8 ROM chips with an enable input, construct a 512 x 8 ROM
with 8 chips and a decoder. (7 M)
II. Draw a PLA circuit to implement the functions (6 M)
F1=A’B+AC+A’BC’
F2=(AC+AB+BC)’