Proceedings of the Third International Conference on Trends in Electronics and Informatics (ICOEI 2019)

IEEE Xplore Part Number: CFP19J32-ART; ISBN: 978-1-5386-9439-8

Study and Simulation of Five-Story Elevator

Controller Using VHDL
Tanvi Palekar, Rinitha Tesa Jose, Gandhali Nanche Rashmi Joshi
Student, EXTC dept. Assistant Professor, EXTC dept.
MPSTME, NMIMS MPSTME, NMIMS
Mumbai, India Mumbai, India
tanvipalekar.nmims@gmail.com, rashmi.joshi@nmims.edu
rinithajose.nmims@gmail.com,
gandhalinanche.nmims@gmail.com

Abstract​—Modern technological advancements call for simpler and manageable design cycle and do not need much
efficient usage of space. Connectivity is often achieved in high manual intervention. The software handles much of the
rise buildings with the help of conventional staircases, or routing, placement, and timing automatically to match the
escalators and most commonly used - elevators. Elevators are
programmed specification. Re-programmability and
used on a daily basis in a wide variety of applications
worldwide. The basic mechanism used in an office elevator is reusability of FPGAs make them flexible for faster
also used in dumbwaiters. This work shows the study and prototyping [10].
simulation of one such application - a five-story elevator The elevator control system can be implemented using a
controller. A Field Programmable Gate Array (FPGA) has finite state machine, which is a mathematical model of
been used in this project due to its re-programmability, computation that can be in exactly one of a finite number of
reusability, and faster and less expensive prototyping. The states at any given time [7].
elevator controller system uses a Finite State Machine (FSM) to
take floor inputs from inside the elevator and up and down
calls from outside the elevator, to determine the movement of
elevator from current state to the desired next state. States II. PRELIMINARY STUDY
have been defined floor wise, depending on whether the A. Design Flow
elevator doors are to be opened or closed. Sensors are used to
improve the reliability and safety of the elevator by positioning A digital system may be designed on an FPGA Board
it appropriately. This elevator controller system has been using the following procedure.
successfully implemented on Xilinx Zynq - 7000 FPGA using
Very High Speed Integrated Circuit Hardware Description 1. Design Entry:
Language (VHDL). Design a behavioral register transfer level or a
structural model of the design in HDL, Verilog or
Keywords—FPGA, VHDL, FSM, elevator controller
VHDL.
2. Simulation:
Simulate and debug the design.
I. INTRODUCTION 3. Synthesis:
An elevator or lift is a vertical transport vehicle that Synthesize the design targeting the desired device.
efficiently moves people or goods between floors of a 4. Translate/Mapping:
building and is generally powered by electric motors [1]. Run a mapping/partitioning program. This program
This paper discusses the elevator controller design for will break the logic diagram into pieces that will fit
vertical motion using a digital system. into the Configurable Logic Block (CLB).
The behavior and structure of circuit and system designs 5. Placement and Routing:
are described using hardware description languages (HDLs). Run an automatic place and route program. This
Some commonly used HDLs are VHDL and Verilog. In this will place the logic blocks in appropriate places in
project, VHDL (VHSIC Hardware Description Language) is the FPGA and then route the interconnections
used to design an elevator controller [2]. VHDL is a rich and between logic blocks.
6. Bitstream Generation:
strongly typed language, deterministic and verbose than
Run a program that will generate a bit pattern
Verilog. VHDL ​emphasizes on unambiguous semantics and necessary to program FPGA.
allows portability between tools [8]. 7. Configuration of device:
Conventional elevator controllers use microcontrollers or Download the bit pattern into the internal
PLCs, the major limitation of these systems are limited configuration cells in the FPGA and test the
number of inputs and outputs [9] [12]. In this project, an operation of the FPGA.
FPGA or Field Programmable Gate Array is used to
overcome the constraints of having a limited number of
input or outputs. FPGAs allow for a complex system to be
designed that requires parallel processing [6]. FPGAs have a

978-1-5386-9439-8/19/$31.00 ©2019 IEEE 1270

horized licensed use limited to: AMRITA VISHWA VIDYAPEETHAM AMRITA SCHOOL OF ENGINEERING. Downloaded on March 31,2024 at 18:16:24 UTC from IEEE Xplore. Restrictions app
 B. Basic Structure
The elevator system is controlled by the elevator
controller. Elevators normally work on inputs from the floor
buttons inside the elevator or from the up or down call
buttons outside of the elevator [4]. The proximity sensors
are located to sense the alignment of the elevator at the
respective floors and to sense the obstruction between the
elevator doors while it is closing [5]. This ensures increased
safety and reliability of the elevator [1].
C. Program Development
More often than not, Verilog is used for implementation
of the elevator controller, due to its compactness of the code
[1]; however, VHDL has been used in this work for its
familiarity. The Finite State Machine (FSM) of the elevator
controller defines the various states of the elevator and
transitions between the states. It is programmed according to
the algorithm to control the operation of the system. The
control signals are used for movement of the elevator from
the current state to the desired next state [3].
B. State Diagram
The state diagram of the five-floor elevator controller
consists of 10 states: open1, close1, open2, close2, open3,
close3, open4, close4, open5 and close5, corresponding to
the open-door and closed-door states of the elevator at the
given floor. That means, if the elevator in this system is on
the first floor with doors open, it can be said to be in open1
state, and when the doors close, it enters the close1 state.
The controller takes the input from the user through the
‘flr’, ‘up’ and ‘down’ signals. The ‘awf1’, ‘awf2’, ‘awf3’,
'awf4’ and 'awf5’ are alignment sensor signals that will
control when and how the door of the elevator will open.
That means, if the awf1 signal is high the lift has reached
and aligned at first floor and it is ready to open. The ‘obs1’,
‘obs2’, ‘obs3’, ‘obs4’, and ‘obs5’ are obstruction sensor
signals that will reopen the elevator doors on the occurrence
of any obstruction between the doors while it is closing.
The state diagram in Fig.1 shows how the states change with
the change in input and the notations used in the state
diagram are tabulated in Table II.

III. IMPLEMENTATION OF THE ELEVATOR CONTROLLER

A. Proposed Algorithm
The proposed model of the controller uses VHDL. It is
designed to work for five floors, and can be extended for a
higher number of floors or reduced to fewer floors if
required. Table I lists the input and output signals used by
the elevator controller in this design, and what function each
of the signals aims to achieve in the model.

TABLE I. LIST OF INPUTS, OUTPUTS, AND THEIR DESCRIPTIONS

I/O Signals Significance

Input signal from inside the elevator
flr
(floors 1, 2, 3, 4, and 5)
Input signal from up buttons outside
up
the elevator on floors 1, 2, 3, and 4

Input signal from down buttons

down outside the elevator on floors 2, 3, 4,
and 5
awf1, awf2,
Alignment with floor sensors for
awf3, afw4,
floors 1, 2, 3, 4 and 5 respectively Fig. 1. FSM state diagram
afw5
obs1, obs2, Obstruction sensors between the
obs3, obs4, doors for floor 1, 2, 3, 4 and 5
obs5 respectively
TABLE II. NOTATION TABLE FOR STATE DIAGRAM
Door open output signal. It is high
when the door is open and low when
do Notations in State Significance
the door closes and lift is ready to
Diagram
move
Output signal, which displays f 1, f 2, f 3, f 4, f 5 Floor signals i.e. flr1, flr2,
flr_display
current floor of the elevator flr3, flr4, flr5.
clk Input Clock signal
u 1, u 2, u 3, u 4 Up call signals i.e. up1,
Input reset signal will reset the
up2, up3, up4.
reset elevator to the default state: open
state of the first floor (open1)
d 2, d 3, d 4, d 5 Down call signals i.e.
down2, down3, down4,
down 5.

1271
horized licensed use limited to: AMRITA VISHWA VIDYAPEETHAM AMRITA SCHOOL OF ENGINEERING. Downloaded on March 31,2024 at 18:16:24 UTC from IEEE Xplore. Restrictions app
 When the elevator and the floor are aligned, the door opens door to reopen. The doors will then remain open for as long
at that floor, and after the specified time period T the as the obstruction is present in the doorway. The transition
elevator door will be closed. This is detected by using the of the elevator is exemplified using a timing diagram in
awf signals which are the alignment with floor sensors. Fig.2.
When no floor calls are received, the elevator must remain
For testing how the model handles two calls at once,
at the same floor’s closed state. As soon as a change is
consider a situation where two people call the lift at the
encountered in any of the inputs, the elevator will proceed to
same time, when the elevator is presently on the third floor,
reach the destination floor. For this, the elevator must
as shown in Fig. 2. One person on the fifth floor wishes to
gradually pass through the floors in between because an
go down. At the same time, another person standing on the
elevator cannot physically jump from a lower floor such as
first floor calls for the elevator to go up. The elevator
floor 1 to a higher floor such as floor 4. Therefore, the state
therefore registers both these calls and first executes the up
diagram represents transitions to intermediate floors without
call from the first floor, then goes to the fifth floor. This
opening the door on those floors to move to the destination
portrays that the elevator will store an input signal till its
floor. An example is explained for the same in Section C -
purpose is fulfilled, and only then it will proceed to reset all
Simulation and Results.
inputs. It will also prioritise the direction in which it is
already travelling before accepting a call in the opposite
direction. This means that if the elevator is moving upwards,
C. Simulation and Results
it will accept and execute all calls which comply with that
Simulation is execution of hardware models in software direction before it accepts and executes the calls in the
environment at any level of abstraction. Simulators are used opposite direction. This is in line with practical elevators in
to simulate the Hardware models, to test if the RTL code use today. The RTL schematic of elevator controller is
meets the functional requirements of the specification and shown in Fig. 3.
all the RTL blocks must be functionally correct. A testbench
is created which initiates ‘clk’, ‘reset’, and the required test
vectors and verifies the behavior of the system. In this
model, the elevator behavior is observed on receiving
certain inputs in a certain order, in terms of the ‘flr_display’
signal and ‘do’ signal. Fig. 2 shows the timing diagram of
the elevator controller designed. The model was simulated
in Xilinx Vivado 2017.4 version. Fig. 2. Timing Diagram

Initially, the reset condition was tested, and as observed,

when ‘reset’ is high, the elevator is in default state ‘open1’,
which means it is on the first floor with doors open. As soon D. RTL Schematic
as the ‘reset’ signal goes low, the clock cycles are detected
and according to the input provided the elevator will
transition between floors. The doors shall only open if the
alignment sensors detect that the lift has aligned with the
desired floor. The desired floor can be fed to the elevator
controller through the floor inputs inside the elevator, and
the up and down call signals from outside the elevator. All
possible transitions and calls have been tested in the
testbench and the elevator behaves as expected. An input of
number ‘0’ indicates no input from that input source, while
the numbers 1 – 5 indicate the floor to which the elevator Fig. 3. RTL Schematic
must reach, or simply put, the destination floor.
IV. CONCLUSION
For example, the lift is in default state on 1​st ​floor and an
input of down 3 is detected, which means that a person calls A. Conclusion
for the lift on the third floor to go downwards. In the next We have studied and simulated a five-floor elevator
two clock cycles, the elevator makes a smooth transition controller model using VHDL. We have successfully
from floor 1 to floor 3 while passing floor 2. The elevator implemented the model on Xilinx Zedboard Zynq 7000
does not stop at floor 2 but instead it continues moving FPGA board. It is observed that the proposed model
towards floor 3. The same behaviour is observed in elevators resource utilization is very low, with very low power
in general. This mechanism allows for a safer and a more consumption. The model offers various advantages as
pleasant ride. Since the ‘awf3’ signal is high when the compared to the conventional microcontroller-based
elevator reaches floor 3, the third floor is aligned and the elevator system; it is more efficient and offers low cost.
door can be opened. The door open signal ‘do’ remains high
for one clock cycle, i.e., the door is open for one clock
cycle. However, if the elevator door is about to close, and
someone tries to enter in the car, the obstruction sensors
between the doors will detect the obstacle and cause the

1272
horized licensed use limited to: AMRITA VISHWA VIDYAPEETHAM AMRITA SCHOOL OF ENGINEERING. Downloaded on March 31,2024 at 18:16:24 UTC from IEEE Xplore. Restrictions app
 B. Future Scope
While the elevator designed meets all intended
requirements, there is always some room for improvements.
A few possible developments could be the following:
● A weight sensor can be added to the elevator to
detect and avoid overloading on the elevator. In
cases of overloading the elevator will not enter
closed state and display a message on the LCD
panel until the load has been reduced.
● A timer can be added to the elevator to adjust the
duration of opening and closing of the elevator
doors. It may also be used for adding a delay in
floor-to-floor transitions.
horized licensed use limited to: AMRITA VISHWA VIDYAPEETHAM AMRITA SCHOOL OF ENGINEERING. Downloaded on March 31,2024 at 18:16:24 UTC from IEEE Xplore. Restrictions app
REFERENCES
[1] S. Ekanayake, R. Ekanayake, S. Sanjayan, S. Abeyratne and S.
Dewasurendra, "FPGA Based Elevator Controller with Improved
Reliability", in UKSim 15th International Conference on Computer
Modelling and Simulation IEEE, 2013.
[2] M. Kumar, P. Singh and S. Singh, "A VLSI Implementation of
Four-Phase Lift Controller Using Verilog HDL", in International
Conference on Materials, Alloys and Experimental Mechanics, India,
2017.
[3] J. Varghese, L. Philip, S. Mammen, Y. Thomas and R. Cheriyan,
"FPGA Implementation of Elevator Controller", in International
Conference on Emerging Trends in Technology and Applied
Sciences, 2015.
[4] M. Siddiqui and K. Hasan, "Synthesis & Simulation Model of Parallel
Lift Controller Using Verilog", International Journal of Engineering
Development and Research, vol. 3, no. 3, pp.1-5, 2015.
[5] P. Kiran Babu and H. Rao, "A VLSI Implementation of Three-Lift
Controller Based on Verilog", International Journal of Engineering
Trends and Technology, vol. 6, no. 1, pp.43-47, 2013.
[6] N. Sulaiman, Z. Assi Obaid, M. Marhaban and M. Hamidon, "Design
and Implementation of FPGA-Based Systems - A Review", Australian
Journal of Basic and Applied Sciences, vol. 3, no. 4, pp. 3575-3596,
2009.
[7] B. Vaidya and D. Anupam, "A Study of different Finite state machine
design and efficient coding techniques", Journal of Information,
Knowledge and Research in Electronics and Communication
Engineering, vol. 2, no. 2, pp. 493-496, 2008.
[8] I. Chiuchisan, A. Potorac and A. Graur, "Finite State Machine Design
and VHDL Coding Techniques", in 10th International Conference on
Development and Application Systems, Suceava, Romania, 2018.
[9] M. Bhuyan, M. Haque, M. Rauf and M. Khan, “Design and
Implementation of a Microcontroller Based Elevator Control
Systems”, Proceedings of the Conference on Engineering Research,
Innovation and Education 2011, pp. 504-507, 2011.
[10] M. Ullah and M. Saeed, “Design and Implementation of Efficient
Elevator Control System using FPGA”, International Journal of
Innovation and Applied Studies, Vol. 9 No. 4, pp. 1541-1546, Dec.
2014.
[11] S. Huseinbegovic, S. Kreso and O. Tanovic, “Design and
Implementation of the CAN Based Elevator Control System”, 2009
XXII International Symposium on Information, Communication and
Automation Technologies, Bosnia, pp. 1-6, 2009.
[12] O. Shete, D. Shete and S. Pise, “A Survey Paper on Design & Control
of an Elevator for Smart City Application”, International Journal of
Advanced Research in Electrical, Electronics and Instrumentation
Engineering, Vol. 6 No. 2, pp. 3021-3027, Apr. 2017.
1273