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Study and Simulation of Five-Story Elevator Controller Using VHDL
Study and Simulation of Five-Story Elevator Controller Using VHDL
Abstract—Modern technological advancements call for simpler and manageable design cycle and do not need much
efficient usage of space. Connectivity is often achieved in high manual intervention. The software handles much of the
rise buildings with the help of conventional staircases, or routing, placement, and timing automatically to match the
escalators and most commonly used - elevators. Elevators are
programmed specification. Re-programmability and
used on a daily basis in a wide variety of applications
worldwide. The basic mechanism used in an office elevator is reusability of FPGAs make them flexible for faster
also used in dumbwaiters. This work shows the study and prototyping [10].
simulation of one such application - a five-story elevator The elevator control system can be implemented using a
controller. A Field Programmable Gate Array (FPGA) has finite state machine, which is a mathematical model of
been used in this project due to its re-programmability, computation that can be in exactly one of a finite number of
reusability, and faster and less expensive prototyping. The states at any given time [7].
elevator controller system uses a Finite State Machine (FSM) to
take floor inputs from inside the elevator and up and down
calls from outside the elevator, to determine the movement of
elevator from current state to the desired next state. States II. PRELIMINARY STUDY
have been defined floor wise, depending on whether the A. Design Flow
elevator doors are to be opened or closed. Sensors are used to
improve the reliability and safety of the elevator by positioning A digital system may be designed on an FPGA Board
it appropriately. This elevator controller system has been using the following procedure.
successfully implemented on Xilinx Zynq - 7000 FPGA using
Very High Speed Integrated Circuit Hardware Description 1. Design Entry:
Language (VHDL). Design a behavioral register transfer level or a
structural model of the design in HDL, Verilog or
Keywords—FPGA, VHDL, FSM, elevator controller
VHDL.
2. Simulation:
Simulate and debug the design.
I. INTRODUCTION 3. Synthesis:
An elevator or lift is a vertical transport vehicle that Synthesize the design targeting the desired device.
efficiently moves people or goods between floors of a 4. Translate/Mapping:
building and is generally powered by electric motors [1]. Run a mapping/partitioning program. This program
This paper discusses the elevator controller design for will break the logic diagram into pieces that will fit
vertical motion using a digital system. into the Configurable Logic Block (CLB).
The behavior and structure of circuit and system designs 5. Placement and Routing:
are described using hardware description languages (HDLs). Run an automatic place and route program. This
Some commonly used HDLs are VHDL and Verilog. In this will place the logic blocks in appropriate places in
project, VHDL (VHSIC Hardware Description Language) is the FPGA and then route the interconnections
used to design an elevator controller [2]. VHDL is a rich and between logic blocks.
6. Bitstream Generation:
strongly typed language, deterministic and verbose than
Run a program that will generate a bit pattern
Verilog. VHDL emphasizes on unambiguous semantics and necessary to program FPGA.
allows portability between tools [8]. 7. Configuration of device:
Conventional elevator controllers use microcontrollers or Download the bit pattern into the internal
PLCs, the major limitation of these systems are limited configuration cells in the FPGA and test the
number of inputs and outputs [9] [12]. In this project, an operation of the FPGA.
FPGA or Field Programmable Gate Array is used to
overcome the constraints of having a limited number of
input or outputs. FPGAs allow for a complex system to be
designed that requires parallel processing [6]. FPGAs have a
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When the elevator and the floor are aligned, the door opens door to reopen. The doors will then remain open for as long
at that floor, and after the specified time period T the as the obstruction is present in the doorway. The transition
elevator door will be closed. This is detected by using the of the elevator is exemplified using a timing diagram in
awf signals which are the alignment with floor sensors. Fig.2.
When no floor calls are received, the elevator must remain
For testing how the model handles two calls at once,
at the same floor’s closed state. As soon as a change is
consider a situation where two people call the lift at the
encountered in any of the inputs, the elevator will proceed to
same time, when the elevator is presently on the third floor,
reach the destination floor. For this, the elevator must
as shown in Fig. 2. One person on the fifth floor wishes to
gradually pass through the floors in between because an
go down. At the same time, another person standing on the
elevator cannot physically jump from a lower floor such as
first floor calls for the elevator to go up. The elevator
floor 1 to a higher floor such as floor 4. Therefore, the state
therefore registers both these calls and first executes the up
diagram represents transitions to intermediate floors without
call from the first floor, then goes to the fifth floor. This
opening the door on those floors to move to the destination
portrays that the elevator will store an input signal till its
floor. An example is explained for the same in Section C -
purpose is fulfilled, and only then it will proceed to reset all
Simulation and Results.
inputs. It will also prioritise the direction in which it is
already travelling before accepting a call in the opposite
direction. This means that if the elevator is moving upwards,
C. Simulation and Results
it will accept and execute all calls which comply with that
Simulation is execution of hardware models in software direction before it accepts and executes the calls in the
environment at any level of abstraction. Simulators are used opposite direction. This is in line with practical elevators in
to simulate the Hardware models, to test if the RTL code use today. The RTL schematic of elevator controller is
meets the functional requirements of the specification and shown in Fig. 3.
all the RTL blocks must be functionally correct. A testbench
is created which initiates ‘clk’, ‘reset’, and the required test
vectors and verifies the behavior of the system. In this
model, the elevator behavior is observed on receiving
certain inputs in a certain order, in terms of the ‘flr_display’
signal and ‘do’ signal. Fig. 2 shows the timing diagram of
the elevator controller designed. The model was simulated
in Xilinx Vivado 2017.4 version. Fig. 2. Timing Diagram
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B. Future Scope REFERENCES
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