3118 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.

9, SEPTEMBER 2010

Highly Efficient Single-Phase Transformerless

Inverters for Grid-Connected Photovoltaic Systems
Samuel Vasconcelos Araújo, Student Member, IEEE, Peter Zacharias, Member, IEEE, and
Regine Mallwitz, Member, IEEE

Abstract—Driven by worldwide demand for renewable sources,

the photovoltaic market saw in the last years a considerable
amount of innovations regarding the construction and operation
of inverters connected to the grid. One significant advance, among
some that will be here discussed is, for example, the abolition of
the galvanic isolation in inverters installed in Germany. There,
transformerless topologies, like the H5 and Heric, can reach very
high levels of efficiency and allow the best cost–benefit ratio for
low-power grid-tied systems. This paper will follow this direction
and propose a single-phase transformerless inverter circuit being
composed of the association of two step-down converters. Each
one modulates a half-wave of the output current, as the correct
polarity of the connection to the grid is provided by low-frequency
switches. Due to its straightforward design, reduced amount of
semiconductors, and simple operation, it is possible to achieve Fig. 1. Overview of the grid-connected PV system concepts showing from the
a high level of efficiency and reliability. These and some other left to the right: module integrated, string, minicentral, multistring, and central
characteristics will be benchmarked against other existing circuits, inverter concepts.
being followed by a theoretical analysis on the properties of the
proposed solution. The project of a laboratory prototype will be evaluate the inherent potential on the relatively large system
presented, along with a discussion about the obtained experimen-
framework that includes parameters like system voltage levels,
tal results.
compatibility with cell technologies, efficiency-curve charac-
Index Terms—Photovoltaic (PV) power systems, pulsewidth- teristic, grid regulations, and some others. Such framework
modulated (PWM) inverters.
will be presented in the next item and then employed for the
discussion of the state-of-the-art developments of single-phase
I. I NTRODUCTION PV inverters.
Afterward, a new single-phase topology will be proposed,

I NVERTERS in grid-connected photovoltaic (PV) systems

have nowadays a relatively low impact in the initial invest-
ment cost, responding for approximately 10% of the total in
comparison with 70% for the modules and 20% for installation
and planning [1]. They nevertheless play an important role
in achieving an effective system with reduced total cost of
ownership given an optimized design. This can be observed,
for example, by a possible reduction in installation costs with
the employment of string technique and higher input voltages.
In addition, energy yield and, hence, payback time is greatly
influenced by the converter electric efficiency and reliability.
Given such conditions, it is necessary to not only observe the
electrical characteristics of a topology in new designs but also
Manuscript received December 31, 2008; revised May 16, 2009 and July 31,
2009; accepted September 8, 2009. Date of publication December 4, 2009; date
of current version August 11, 2010.
S. V. Araújo is with the Center of Competence for Distributed Electric Power
Technology (KDEE), University of Kassel, 34121 Kassel, Germany (e-mail:
s.araujo@uni-kassel.de).
P. Zacharias is with the Center of Competence for Distributed Electric Power
Technology (KDEE) and also with the Institute for Electrical Power Supply
Systems (IEE-EVS), University of Kassel, 34121 Kassel, Germany (e-mail:
peter.zacharias@uni-kassel.de).
R. Mallwitz is with SMA Solar Technology AG, 34266 Nietestal, Germany
(e-mail: regine.mallwitz@sma.de).
Digital Object Identifier 10.1109/TIE.2009.2037654
0278-0046/$26.00 © 2010 IEEE
followed by the theoretical analysis. Experimental results ob-
tained with a prototype will be presented and discussed.
II. F RAMEWORK
A. System Concepts
PV systems are modular by nature and can therefore be
erected in a wide power range. An initial category can be
identified as module-integrated devices that range to a maxi-
mum power of approximately 300 W [Fig. 1(a)]. They show, as
highlights, reduction of installation costs through elimination
of dc cabling, flexible expansion, system design with different
types of modules, and practically no maximum power point
tracking mismatch losses. Drawbacks are the high specific cost
that relies on mass production to reach competitiveness, lower
electrical efficiency in comparison with larger converters, and,
finally, difficult maintenance and harsh ambient conditions that
require a highly reliable design [2].
Nonintegrated designs, on the other hand, allow the series
and parallel connection of several panels for achieving a higher
peak power through, respectively, a higher voltage or current.
Here is the string concept [Fig. 1(b)], i.e., a single-phase
inverter for one series association of modules, which is the most
ARAÚJO et al.: SINGLE-PHASE TRANSFORMERLESS INVERTERS FOR GRID-CONNECTED PHOTOVOLTAIC SYSTEMS
common one, allowing lower installation costs and reduced
conduction losses due to higher input-voltage levels for a power
up to 4.6 kVA in Germany [3] or 30 kW in the U.S. [4].
For higher power levels, three concepts are available. The
first one is to connect string inverters together forming a three-
phase output in the so-called minicentral design [Fig. 1(c)]. As
a consequence, single-phase topologies can still be found up
to 50 kW per unit. One reason for this kind of association is
the reduced input voltage required to feed the grid in relation
to three-phase circuits, which allows a more efficient design.
The two other concepts rely on three-phase inverter topologies
that have either separated input dc/dc stages for each string—
the so-called multistring concept [Fig. 1(d)], or a single, or
most commonly, no input stage—corresponding to the central
inverters [Fig. 1(e)] that are mostly applied in systems rated
above 200 kWpeak , according to a market research performed
by the authors.
B. Local Grid Regulations and Standards
The influence of grid regulations and standards can be mainly
divided into two classes: operational and design issues, as will
be described in details in the next items.
1) Operational Issues: In this category are the requirements
regarding output-current regulation, total harmonic distortion
(THD), islanding-detection techniques, and dc component lim-
its, among others. This last one deserves special attention as
it strongly depends on the use of an isolating transformer. As
presented in [5], the dc currents in transformerless commercial
inverters are almost three times higher than the ones observed
in their counterparts with transformers. Limits established in
worldwide standards are diverse and range in absolute values
from 5 mA in the U.K. [6] to 1 A in Germany [7], and in relative
values of the rated current of the device from 0.5% in the U.S.
[8] to 1% in Japan [9]. In order to not surpass such limits,
special care is taken in transformerless systems regarding the
control and measurement implementation to avoid asymmetries
between the two generated half-waves. Parameter variation
from semiconductors and filter elements may also be a factor
increasing the dc component, although modern fabrication tech-
niques reduce such influence to admissible levels.
2) Design Issues: Of greater interest here are design issues,
meaning that some special requirements of local regulations
limit the applicability of specific topologies. At this point, it
is important to observe the great diversity of such standards,
which leads to the conclusion that no single optimized solution
is applicable in the whole world.
A major design issue is the necessity of galvanic isolation.
The insulation can be achieved through low-frequency trans-
formers in the output that also generally perform voltage step-
up. Due to critic weight and cost of such approach, several
topologies with high-frequency isolation were developed, al-
though here, higher losses due to multiple stages are a severe
drawback. The transformerless concepts, on the other hand,
display not only lower cost and size but also higher European
efficiency (Fig. 2), which is the weighted efficiency of a given
circuit for different power levels, as it will be explained in detail
in Section II-E of the paper.
3119
Fig. 2. European efficiency as a function of output power for inverters with
and without transformerless topology along with the respective trend lines [24].
Since the galvanic isolation is not a requirement in Germany
in the low-voltage grid [3], transformerless inverters are nowa-
days the market mainstream there. Spain [10] and Great Britain
[11] literally require the isolation in all applications, while in
Italy, this is necessary for power levels above 20 kW [12].
In the U.S., the use of galvanic insulation is widespread not
because it is directly required but as a consequence of the
necessity of grounding one of the panel outputs [13], which
leaves few alternatives for the use of transformerless topologies,
aside from a few specially developed circuits [14], [15].
Another important issue arising from new standards, particu-
larly in Germany [16], is the requirement for static grid support
through injection of reactive power by converters directly con-
nected to the medium-voltage level. This requisite is also being
discussed there for inverters in low-voltage grid, although the
implementation and control methods are not yet clear. Mean-
while, most other countries have not yet displayed intention to
impose such requirements on low-power PV inverters.
C. PV Module Compatibility and Related Issues
While crystalline silicon cells are by far the most employed
in the market, thin-film cells are in fast ascension and expected
to respond for 20% of the overall production capacity by the
end of 2012. Such increasing significance comes mainly as
a consequence of the lower specific price (roughly 20% less
in comparison with silicon modules) although as a drawback,
larger areas are necessary due to lower cell efficiency [17]. In
addition, it was observed that some of such cells require a cer-
tain voltage gradient across the module in relation to the ground
for proper operation [18]. This can be achieved either artificially
by means of a special operating condition or by grounding
one of the array terminals. Examples are the thin-film cells
based on superstrate technology (a-Si and CdTe) that require
a positive voltage gradient or negative-terminal grounding in
order to avoid the corrosion of the transparent conductive oxide
layer [18]. Similarly, highly efficient backside contact cells
from the manufacturer Sunways demand a negative voltage
gradient or grounded positive terminal so that the polariza-
tion effect and subsequent reduction of the efficiency can be
avoided [19].
3120
Fig. 3. Voltage ratios for silicon modules available in the market [25].
The leakage currents to ground constitute another important
issue if one of the terminals of the array cannot be grounded,
particularly regarding transformerless concepts. Due to their
structure, PV modules naturally form a parasitic capacitance
between the cells and the grounded frame [20], [21]. High-
frequency variations of the cell potential in relation to ground
shall therefore be avoided in transformerless circuits since
this leads to large charge/discharge currents partially flowing
through the circuit to the ground, resulting in an increase of the
harmonic content, higher losses, and also, safety and electro-
magnetic interference problems [22], [23]. Special single-phase
transformerless topologies with reduced oscillations have been
developed for such purpose and will be later discussed. In addi-
tion, the introduction of frameless panels further contributed to
the reduction of such problem.
D. Input Voltage Levels
Unlike other applications employing inverters, PV systems
have as unique characteristic a certain variation on the input
voltage, also known as the maximum power point (MPP)
voltage range. The lower limit can be defined under worst
case conditions with a minimal radiation level and high cell
temperature (100 W/m2 and 50 ◦ C), while the inverse would be
valid for the higher limit (1000 W/m2 and 20 ◦ C). Considering
the silicon crystalline modules available in the market [25] and
the aforementioned conditions, a factor of approximately 0.7
for the division of such limits is obtained.
During system start-up, a higher voltage level, namely, the
open-circuit voltage, is impressed in the input of the inverter.
From the performed analysis and for a radiation level of
1000 W/m2 and −10 ◦ C, cell temperature can reach up to
two times the minimal MPP voltage. The calculated ratios are
shown in Fig. 3, as a function of the module rated power.
For the design of PV inverters, it is therefore necessary to
consider the factors aforementioned not only for operation but
also when choosing the voltage rating of the semiconductors.
As stated before, when transformers are employed, they pro-
vide some sort of voltage step-up allowing, at the same time,
flexibility in choosing an optimal input voltage.
For highly efficient transformerless topologies composed of
a single stage, the minimum input-voltage level is tied to the
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 9, SEPTEMBER 2010
TABLE I
PV A RRAY L EVELS FOR A G IVEN G RID VOLTAGE AND T OPOLOGY R ATIO
maximum grid voltage, i.e., nominal value plus 10% [26] and
the topology specific ratio between input and output voltages.
As an example for this factor, a half-bridge or single-phase
multilevel inverter requires a two times higher input voltage
in relation to the traditional full-bridge configuration for the
same output voltage. The necessary array voltage for European
single-phase grid levels (230 V ± 10%) and modulation reserve
of 5% values are given in the Table I.
What is important to observe here is that in order to operate
with a single stage, multilevel inverters would require a rather
large voltage in the input that, for the maximum open-circuit
value, is out of the scope of most manufacturers’ specifications
and current standards in Europe [27], [28]. Initial discussions
for the expansion of such limits are nevertheless already taking
place in Germany [29]. If the American voltage levels were
considered, a maximum array voltage superior to 600 V would
be necessary for multilevel converters, falling out of the low-
voltage category and, consequently, requiring more complex
installation equipment [13].
E. Electric Conversion Efficiency
This characteristic is sometimes regarded as the most signif-
icant in PV converter circuits, as it directly affects the payback
time of the facility.
Under the necessity of directly comparing different system
concepts and converter topologies with a single value rather
than using efficiency curves, the weighted efficiency concept
with factors directly related to local radiation levels was de-
fined. An example is the so-called “European efficiency” [30],
suitable for countries with low radiation levels like Germany
(1000 kW · h/m2 · year), while for regions with higher radi-
ation levels, like the southeast of the U.S. (over 1800 kW ·
h/m2 · year), other factors were defined under the normally
called “U.S. efficiency” [31].
The project of converters for PV applications are, as a
consequence, strongly influenced by such factors, as the peak
efficiency in a good design is specified to reach a maximum
value around 50% and 75% of the nominal input power for,
respectively, the European and American values.
Such characteristic is achieved by a good balance between
semiconductor switching and conduction losses along with the
optimization of current freewheeling paths in such a way that
the efficiency is not prejudiced by the operation at different
input voltage levels. Of great importance is also the design
of the magnetic elements in order to attain reduced core
losses and, consequently, good performance in the lower power
region.
ARAÚJO et al.: SINGLE-PHASE TRANSFORMERLESS INVERTERS FOR GRID-CONNECTED PHOTOVOLTAIC SYSTEMS
Fig. 4. Full-bridge inverter with the module parasitic capacitances.
F. Semiconductor Technologies
From the previous items was observed that transformerless
inverters operate with higher input voltages when compared
with their counterparts with transformers, which infers the use
of semiconductors with higher blocking voltages. The design
of such circuits with reduced losses has been made possi-
ble mainly due to recent developments toward high-efficiency
semiconductor technologies at higher voltage classes.
Regarding silicon switches, a first example are the insulated-
gate bipolar transistors with Trench-Gate and Field-Stop tech-
nologies, characterized by a good balance between conduction
and switching losses [32], [33]. The superjunction technology
(also known as CoolMOS) made MOSFETs with blocking volt-
ages of up to 900 V a very interesting option due to the reduced
on-resistance values and high switching speeds, surpassing the
theoretical limits of vertical Si MOSFETs.
The recent development of silicon carbide (SiC) switches like
MOSFETs and JFETs has also served as an indication of further
advances toward high blocking voltages together with very low
losses [34].
III. S INGLE -P HASE T RANSFORMERLESS T OPOLOGIES
Taking into consideration the presented framework, highly
efficient single-phase inverter topologies that will most likely
reach a high level of efficiency at low cost are the ones consti-
tuted by a single-stage without transformer.
The classic full-bridge circuit as shown in Fig. 4 would
constitute a first example, although the performance and ap-
plicability are strongly influenced by the employed modulation
scheme and the resultant voltage across the parasitic capacitors
Cp1 and Cp2 between the panels and the ground.
The bipolar modulation [36], also known as two level, [37]
uses a single sinusoidal reference for one group of diagonal
switches, with the other group using the complementary signal.
As a result, two voltage levels are modulated in the output,
leading to a high current ripple across the inductors. A further
drawback is that the current freewheeling happens through
the antiparallel diodes to the dc-link capacitors, resulting in
3121
Fig. 5. Reference output voltage and resultant voltages across the parasitic
capacitors for different modulation strategies in a full-bridge inverter.
additional losses due to the internal reactive-power flow inside
the inverter. The occurrence of leakage current due to PV array
oscillations to ground is not a critic issue here, given the use
of a divided output inductor filter, as shown in Fig. 4. The
resultant voltage across each parasitic capacitor follows the
output voltage with half the amplitude and offset that is
equal to half of the input voltage, as shown in Fig. 5. An
example of a commercial device using such approach is the
SolarMax 4000 [35].
The use of unipolar modulation [36], also known as three
level [37], employs two sinusoidal references dephased by
180◦ to modulate each phase leg. Such strategy allows an
additional voltage level with ripple reduction, along with no
internal reactive-power flow due to the freewheeling through
only two antiparallel diodes. In addition, the output-voltage
levels change effectively with the doubling of the switching fre-
quency that leads to a further reduction of the filter size. Despite
such advantages, it cannot be employed in transformerless PV
inverters since the PV array voltage to ground will oscillate at
the switching frequency, as shown in Fig. 5, generating high
level of leakage currents.
One final alternative to both classical strategies is the use of
the single-phase chopping scheme, where one leg is switched
at high frequency and the other at grid frequency for each half-
wave. Of advantage here is not only the additional voltage level
but also the reduced switching losses and no internal reactive-
power flow. Only one single-output filter inductor may be used
in this case. The PV array voltage oscillations to ground take
the form of a square wave with grid frequency, as shown in
Fig. 5, which may require complex filtering solutions to reduce
the occurrence of high temporary peaks of leakage current.
Several new single-phase topologies found in the market deal
with the issues discussed earlier, such as the following.
3122
Fig. 6. Analyzed single-phase high-efficiency PV inverters—from left to right: Heric, H5, Karschny, and Extended input-voltage circuits.
A. HERIC [38] [Fig. 6(a)]
This topology is constituted by a normal full-bridge cir-
cuit with each group of diagonal switches being operated at
high frequency during one half-wave of the output voltage.
An additional branch placed in parallel with the filters and
load has two switches in opposite directions, each one active
during one whole half-period of the grid waveform. The current
freewheeling now happens through such switches, eliminating
the internal flow of reactive power, allowing an additional
voltage level, and finally reducing the occurrence of leakage
currents, since the PV array is decoupled from the grid during
the freewheeling phase. The drawbacks here are the increased
amount of semiconductors and the incapability of processing
reactive power with the default switching strategy. Examples of
commercial products with such topology are the NT-series of
inverters from the manufacturer Sunways [35].
B. H5 [39] [Fig. 6(b)]
This inverter basically consists of a full-bridge with the
upper switches operating at grid frequency and the lower ones
operating at high frequency. Such strategy is similar to the
already presented single-phase chopping and, hence, shares
some of its advantages. The main difference is the addition of a
switch operating at both half-waves together at high frequency
with the modulating one from the lower part of the full bridge.
Its main functions are to electrically decouple the PV array
from the grid, avoiding the incidence of high-frequency voltage
components across it. The disadvantages of this topology are
the higher conduction losses due to the series association of
three switches during the active phase, and operation with re-
active power is only possible with modified switching strategy
characterized by increased losses. This circuit is employed by
the manufacturer SMA on the Sunny Mini Central series and
the new SunnyBoy TL series (above 3.2 kW) [35].
C. NPC
Although the Neutral-Point-Clamped (NPC) inverter can be
considered a mature solution in traction applications, it has
only been recently applied in PV systems. It shares most of
the advantages of the previously presented circuits, namely, no
internal reactive-power flow, output voltage with three levels,
and minimized voltage oscillations of the PV array to ground
[21], [40]. A serious drawback for the single-phase application
is the requirement for a high input-voltage level; the double in
comparison with the previous circuits. As stated before, since
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 9, SEPTEMBER 2010
such high levels are not yet covered by the actual standards, a
boost stage has been so far applied in the input for commercial
products, like, for example, the Triple Lynx Series from the
manufacturer Danfoss [35]. Consequently, the total efficiency
of the topology is significantly reduced.
Another critical point regarding the application of such cir-
cuit in grid-connected appliances is the higher transient voltage
across the middle switches, already observed in commercial
applications. This is mainly justified by the fact that these
switches are not clamped to the dc-link capacitors like the
external ones and are also under direct influence of parasitic
components in the system layout [41], [42].
As a conclusion, a single-stage transformerless solution of
the NPC inverter could also be an interesting option in the near
future only if such problems were addressed, together with a
revision of the standards toward higher system voltage levels.
D. Flying-Inductor (Karschny) Topology [Fig. 6(c)]
The basic topology [14] allows a direct connection between
the output neutral and the negative terminal of the PV array,
eliminating any voltage oscillations and, in addition, allowing
the operation with special thin-film panels. The basic structure
here consists of a circuit capable of operating as a buck and
boost stage with auxiliary switches defining the output polarity.
The large amount of semiconductors in the current path and
the necessity of storing the whole energy in the inductor lead,
respectively, to high amount of losses and higher construction
cost and size. The inverters belonging to the series, Sitop
Solar from the manufacturer Siemens, employ the referred
circuit [35].
E. Inverter for Expanded Input Voltage [Fig. 6(d)]
A common limitation of the previous single-stage topologies
is the necessity of keeping the PV array voltage above a critical
level for directly feeding the grid. In order to deal with such
problems, a special topology was developed [43] with the main
idea of employing a single-stage circuit when the input voltage
is high enough, and only resorting to step-up function when it
drops below a predefined level. The advantages of such hybrid
approach in comparison with the traditional two stages is the
reduced amount of losses as the step-up stage is active during
only a small interval of time and the higher efficiency of such
stage, as it is designed for a smaller power level. The drawbacks
are the large amount of semiconductors and complex operation.
The Refusol 11 k from the manufacturer Refusol employs such
concept.
ARAÚJO et al.: SINGLE-PHASE TRANSFORMERLESS INVERTERS FOR GRID-CONNECTED PHOTOVOLTAIC SYSTEMS
Fig. 7. Proposed inverter circuit.
IV. N OVEL T OPOLOGY
A highly efficient single-phase circuit composed of a single
stage is here proposed. The basic idea behind it is to associate
two parallel step-down converters with the output connected
to the load using opposite polarities. It is derived from [44]
and [45], where one of the discussed power-factor correction
circuits was modified to get a reverse power flow. This way, one
half-wave of the output voltage is modulated at high frequency
by a single switch, while the correct connection to the load is
effectuated by another switch commutated at low frequency.
This circuit can be considered as a voltage-source-inverter
(VSI) approach, with the current being directly modulated in
the output as a result of the voltage difference between the
inverter and the grid.
The resultant circuit is shown in Fig. 7, where the group of
components of each step-down converter responsible for the
positive and negative half-waves can be respectively identified
as T1 − L1 − D1 − T3 and T2 − L2 − D2 − T4 . Vin represents
a PV array as the input source and Vout as the utility grid in the
output.
In combination with the impedances of the low-voltage grid,
only a few filtering effort here represented by the inductors L1
and L2 is required to satisfy common grid regulations. The
necessity of two inductors operating during each half-wave is
the main drawback of the topology, although this significantly
affect the final cost but not the efficiency, given a proper design.
The use of different inductors also increases the possibility of
asymmetry between each half-wave, leading to the presence of
dc components in the output current. The construction of such
inductors may therefore be made within tight parameter control.
The proposed circuit is characterized by a high level of
reliability since the danger of leg short circuit exists only at
the moment of zero crossing instead of at every commutation
of the high-frequency switches like in other circuits. Reliability
is further increased along with cost reduction due to the fact
that the output-current measurement does not require galvanic
isolation and can be performed by a simple resistive shunt as is
shown in Fig. 7 by Rshunt .
Leakage currents are avoided due to the absence of high-
frequency oscillations since the negative output of the PV array
is directly connected to the neutral and to the phase output,
respectively, during the positive and negative half-waves.
Being naturally a single-phase circuit, applications are ex-
pected to power levels of up to 4.6 kVA for single-string
concepts and up to 50 kW in the case of minicentral approach.
3123
Fig. 8. Variant of the proposed inverter circuit.
TABLE II
C OMPARISON R EGARDING S EMICONDUCTOR C OMPLEXITY
Similar to some of the previous circuits, it is also not possible to
process reactive power, as the current freewheeling is separated
from the dc-link capacitance.
A. Variant of the Circuit
Given the fact that the high-frequency switches (T1 and T2 )
on the proposed circuit require galvanic-isolated driver circuits,
a variant of the topology is proposed, as shown in Fig. 8. Here,
the low-frequency switches are the ones with such require-
ment, which leads to a reduction in costs and increased relia-
bility. The diodes D3 and D4 were added to clamp the voltage
across the switches T3 and T4 in case of transients to the input-
voltage level and hence do not play any role in the case of
normal operation.
The most significant difference in comparison with the orig-
inal circuit is that, now, the positive terminal of the PV array is
connected to the phase output during the positive half-wave and
to the neutral during the negative half-wave. Likewise, as in the
original circuit, there are no high-frequency oscillations to the
ground.
B. Comparison With Other Topologies
The attained simplicity not only regarding operation but also
regarding construction becomes evident when comparing some
aspects of the previous topologies, as shown in Table II.
In addition, all the high-frequency switches in the variant of
the proposed circuit do not require high-side drivers, which,
as already stated before, reduces the costs and increases sig-
nificantly the reliability of the circuit. In order to compare
the semiconductor losses of each circuit, the methodology
presented in [46] is employed as follows.
The semiconductor voltage-stress factors normalized with
the output voltage Vout are calculated in (1) and (2). The
semiconductors T1 , T2 , D1 and D2 have a maximum voltage-
stress equal to the input voltage Vin , while for T3 and T4 , it is
3124 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 9, SEPTEMBER 2010
Fig. 9. Plotted curves for (top) the weighted conduction-losses factor and
(bottom) weighted switching power-stress ratio for the analyzed circuits.
equal to the output voltage. M represents the output to input
voltage ratio of the converter for a given moment
Vin 1 to the group of converters with the lowest switching losses.
ε̂2_T 1,T 2,D1,D2 = = (1)
Vout M
Vout
ε̂2_T 3,T 4 = = 1. (2)
Vout
The rms current conduction factors represented by the sym-
bol ξ˜x can be directly obtained by the interval of time during
which each semiconductor is active, and are equal to the square
root of D, 1 − D, and 1 for, respectively, the high-frequency
switches (T1 , T2 ), freewheeling diodes (D1 , D2 ), and low-
frequency switches (T3 , T4 ). In this case, D represents the
instantaneous value of the duty cycle of the high-frequency
switches. With the already presented factors, it is now possible
to calculate the weighted conduction losses factor in (3). Given
the fact that the inverter operates as a step-down converter, the
instantaneous values of the duty cycle D can be substituted
by M in
 at the discontinuous conduction mode.
Ξ̃∗2 = ε̂2_T 1,,T 2 · ξ˜T2 1 + ε̂2_D1 · ξ˜D1
2 + ε̂ ˜2
2_T 3,T 4 · ξT 3,T 4
 
1 1 M +1
= ·D+ · (1 − D) + 1 · 1 = . (3)
M M M
At the top of Fig. 9 are traced the curves representing the
factor calculated with (3) as a function of the normalized output
voltage for the proposed and for the other previously analyzed
topologies. It becomes clear that the new topology achieves
the minimum conduction losses among all circuits due to the
reduced amount of switches in the current path.
The switching losses can be estimated with the weighted
switching power-stress ratio (Π∗S ) that is calculated by dividing
the switching voltage and current values (considering no ripple
in the current) of a semiconductor by the output power, and then
Fig. 10. Operation of the variant circuit: the (a) negative half-wave and
(c) positive half-wave with (b and d) the respective freewheeling stages.
multiplying the value by the inherent normalized voltage-stress
factor. The weighted switching power-stress ratio is calculated
in (4) for the high-frequency switches only
 
Iout · Vin 1
Π∗S _T 1,T 2 = ε̂2_T 1,T 2 · = 2. (4)
Iout · Vout M
On the bottom of Fig. 9 are presented the curves obtained by
tracing the factor calculated in (4). The proposed circuit belongs
As a conclusion, from the factors representing the conduction
and switching losses, the proposed circuit presents the highest
potential for reaching a high level of efficiency with the lowest
amount of semiconductors among all the other circuits.
C. Principle of Operation
The basic operation of the variant circuit is shown in Fig. 10.
The negative half-wave for both circuits is modulated by the
high-frequency switching of T1 following a sinusoidal refer-
ence, while T4 remains turned on. When T1 is deactivated,
the diode D1 provides the current freewheeling path, while the
energy from the PV array is stored in the dc-link capacitors.
Similarly, the positive half-wave is provided with T2 switching
at high frequency, while T3 remains activated. Freewheeling
occurs through D2 . Depending on the current value and partic-
ularly, around the zero-crossing instant, the converter operates
V. T HEORETICAL A NALYSIS
A. Semiconductors
The switches operating at high frequency (T1 and T2 ) are
under a maximum voltage stress equal to the input voltage. The
effective current through them is calculated in (5), where Tg
is the grid period, Iout (t) the output current, and D(t) is the
duty cycle of the referred switch, which ranges from zero to
one following the amplitude of a sinusoidal reference


 Tg
 2
1 2 (t) · D(t)] · dt.
Irms_T 1 = [Iout (5)
Tg
0
ARAÚJO et al.: SINGLE-PHASE TRANSFORMERLESS INVERTERS FOR GRID-CONNECTED PHOTOVOLTAIC SYSTEMS
The freewheeling diodes need to block the input voltage and
have an average current given by
Tg
2
1
Iavg_D1 = [Iout (t) · (1 − D(t))] · dt. (6)
Tg
0
The switches operating at the grid frequency (T3 and T4 ) are
rated for the maximum grid voltage. The effective value of the
current through them is calculated in

 Vout · ΔIfactor
 Tg
 2
1 2 (t)] · dt.
Irms_T3 =  [Iout (7)
Tg
0 A higher ripple value will reduce the size and inherent
B. DC Link
The dc link functions as an energy buffer and is dimensioned
to allow stable operation at the MPP considering the fact that
the current extracted by the inverter follows a rectified sinus.
The required capacitance is calculated in (8), considering the
approach presented in [47]. Pout represents the nominal output
power, Δ% Uin_ min is the percentage of the ripple on the input
voltage, Uin_ min is the minimum input voltage (used for a worst
case calculation), and fg is the grid fundamental frequency
Pout
Cpv = . (8)
2 · Δ% Uin_ min · Uin
2
_ min · 2 · π · fg
Since the dc link also buffers the energy during the free-
wheeling stage at high frequency, it is also advised to employ
some low-inductance film capacitors with reduced value of
equivalent series resistance (ESR) for reduced high-frequency
voltage ripple.
C. Output Filter
Knowing that this topology operates similarly to VSIs, it is
only necessary to employ inductors in the output to provide
filtering of the output waveform. To reduce the inductor size,
usually, an additional capacitor is added in parallel with the
load. The complete solution could be considered equivalent to
the use of an LC filter. The problem regarding the capacitor
charging current at start-up can be addressed by either using
a limiting resistor that is afterward shunted with a relay or by
synchronizing the grid connection at the zero-crossing instant.
The required inductance value is calculated by considering
the moment when the ripple in the output current reaches the
maximum value. The factor representing such instant depends
on the modulation factor and is determined by the maximum
value of (9), where M represents the voltage gain of the circuit
(division of the output voltage by the input value) and wg the
grid angular reference
ΔIfactor (M, t) = sin(wg · t) − M · sin2 (wg · t). (9)
The required inductance is then calculated in (10) by choos-
ing a limit for the ripple in the output current (ΔIL ). Vg
3125
TABLE III
P ROTOTYPE S PECIFICATIONS
represents the output voltage and fsw the switching frequency
L1 = L2 = . (10)
fsw · ΔIL
losses of the inductors, although it will also increase the rms
current through the semiconductors and also the switching and
conduction losses. A value not higher than 20% is therefore
recommended.
The output capacitor can afterward be calculated in (11) by
selecting a cutoff frequency (fc ) for the filter in the range be-
tween 30 times the grid frequency and one-tenth the switching
frequency [49]
1
Cf = . (11)
4 · π 2 · fc2 · L1
Depending on the local-grid characteristic, a damping resis-
tor shall be used in order to avoid possible resonance with the
grid impedance.
VI. E XPERIMENTAL R ESULTS
A. Specifications and Project
In order to evaluate the performance of the variant of the pro-
posed circuit, a prototype was built following the specifications
given in Table III.
1) Semiconductors: Given the maximum MPP voltage and
assuming a derating factor of 60% in order to achieve a high
level of reliability [48], the switches operating at high frequency
need to have a blocking voltage of at least 900 V. The maximum
rms current is equal to 11.9 A. The freewheeling diodes have
the same voltage rating and an average current of 4.6 A.
By considering the same derating factor, the switches oper-
ating at low frequency shall have a blocking voltage of at least
550 V. Since these switches are clamped to the maximum input
voltage by the diodes D3 and D4 in case of faults or transients
in the grid side, a slightly higher voltage class of 600 V was
chosen. The maximum rms value of the current through them is
13.84 A.
2) DC Link: Applying in (11) the values from the specifi-
cation results in a dc-link capacitance of at least 1.7 mF. The
voltage rating is specified to be 1000 Vdc . In parallel to the
electrolytic capacitors is applied a metallized polypropylene
film capacitor with 20μF, rated for 1000 V that has a reduced
value of ESR and equivalent series inductance.
3) Filter: In Fig. 11 are shown the curves of ΔIfactor from
(9) for both minimum and maximum modulation indexes based
on the specified input-voltage range. The highlighted maximum
3126 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 9, SEPTEMBER 2010

Fig. 12. Gate signals of the switches.

Fig. 11. Graph of ΔIfactor for the maximum and minimum modulation
indexes highlighting the maximum value.

factor of approximately 0.41 is applied in (10) together with a

ripple across the inductor of 10%, resulting in an inductance
value of approximately 3 mH.
Given the low switching frequency and also limited flux
swing due to small current ripple, copper losses are expected
to be much more significant than core losses. This way, an in-
ductor already available with a powder iron core was employed.
The windings were constructed with a normal cable.
Given the selected cutoff frequency, the required filter capac-
itance was calculated with (11), and a minimal value of 3.3 μF
was used.
Fig. 13. Output current and current in one of the inductors with respective
high- and low-frequency switch gate signals.

B. Control Implementation
The output current is controlled by following a sinusoidal
reference with the angle being extracted from the grid by a
simple phase-locked loop algorithm. The result of the error
between the reference and measured current values is processed
by a proportional–integral plant that afterward goes through
normalization considering the input-voltage value. The whole
algorithm was implemented on a DSpace system.
A small deadband between the signals of the low frequency
switches (100 μs) shall be added to avoid grid short circuit.
Unlike other inverters where both filter inductors are always
active, it is necessary to observe here the requirement of reach-
ing a current equal to zero on one inductor before turning off the Fig. 14. Gate voltage of the switch T1 along with the blocking voltage
waveform and current through the respective inductor.
respective low-frequency switch (so that no overvoltages across
the switch will happen). For such purpose, a dead time between For the initial investigation, the DSpace system was em-
the positive and negative polarities of the reference current ployed to generate all the necessary PWM signals. In Fig. 12 are
waveform was added. This was done by taking the reference shown the gate signals measured in the output of the respective
signal and, respectively, adding and subtracting a certain offset drivers.
value from the negative and positive polarities. Fig. 13 shows the output current along with the current
through one of the inductor filters and the gate signal for the
respective high- and low-frequency switches. For the shown
C. Experimental Waveforms and Curves
waveform, a deadband of 500 μs was employed at the zero-
All the switches were chosen from the CoolMOS Technology crossing instant. On later investigations, a value of 100 μs
(IPW90R120C3 for T1 –T2 and IPW60R045CP for T3 –T4 ), as was employed. The THD of the current waveform for such
by this power level, they are characterized by the lowest pos- conditions was calculated using simulation results and reached
sible conduction and switching losses among all technologies approximately 2%.
employing silicon. Silicon carbide diodes were then employed In Fig. 14 is shown the switching characteristic of one of the
for the D1 –D4 so that the switching losses from the converter high-frequency switches along with the drain-to-source voltage
could be further reduced due to the absence of the reverse and current through the respective inductor. The different rise
recovery effect. and fall times of the gate voltage are explained by different
ARAÚJO et al.: SINGLE-PHASE TRANSFORMERLESS INVERTERS FOR GRID-CONNECTED PHOTOVOLTAIC SYSTEMS
Fig. 15. Efficiency curve of the power stage for an input voltage of 375 V.
values of turn-on and turn-off resistances (22 and 10 Ω, re-
spectively) that were applied for further optimization of the
switching losses.
The electric efficiency measured with a LEM wideband
power analyzer of the circuit reached 99% for the most impor-
tant part of the load curve as shown in Fig. 15. The European
efficiency value was approximately 98.8% for an input voltage
of 375 V.
VII. C ONCLUSION
Transformerless PV inverters for grid-connected applications
are the devices on the market with the fastest payback time,
mainly due to higher efficiency and lower specific cost. Such
advantages come nevertheless at the cost of more complex
design and operation. Based on such framework, this paper
has reviewed the most efficient concepts presently available in
the market and proposed a new inverter circuit. The operation
of the circuit was evaluated in experimental results, and a
very high level of efficiency was achieved with an optimized
semiconductor configuration.
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Samuel Vasconcelos Araújo (S’05) received the
B.S. degree in electrical engineering from the Fed-
eral University of Ceará, Fortaleza, Brazil, in 2006,
and the M.S. degree in renewable energies and en-
ergy efficiency (RE2) from the University of Kassel,
Kassel, Germany, in 2007. He is currently working
toward the Ph.D. degree at the University of Kassel.
He is currently working in the Center of Com-
petence for Distributed Electric Power Technology
(KDEE), University of Kassel, and is responsible for
the development of power electronic circuits in part-
nership with industry. His main fields of interest are the design and optimization
of power circuits and the investigation of innovative semiconductors based on
silicon carbide.
Peter Zacharias (M’06) received the Dipl.-Ing.
and Dr.-Ing. degrees in electrical engineering from
the “Otto-von-Guericke” University Magdeburg,
Magdeburg, Germany, in 1979 and 1981, respectively.
During 1983–1984, he was a Postdoctoral Re-
searcher at the Polytechnical Institute of Kiev, Kiev,
Ukraine, in power laser engineering. He was with the
University of Magdeburg until 1990 as an Associate
Professor of power electronics in the research fields
of power electronics for high-voltage applications
and pulsed power. From 1990 to 1995, he was with
Lambda Physik GmbH, Goettingen, Germany, responsible for power systems
development for excimer lasers. In 1995, he was with the Institute for Solar En-
ergy Technology (ISET), Kassel, Germany, and headed the Power Electronics
Department until 2001. In 2001, he was with eupec GmbH, Warstein, Germany,
as Manager of power assemblies. Since 2005, he has been with the University
of Kassel, Kassel, Germany, as a Professor of electric power supply systems.
Additionally, he is a member of the Board of ISET, e. V., Kassel.
Regine Mallwitz (M’08) was born in Guestrow,
Germany, in 1970. She received the Dipl.-Ing.
degree from the “Otto-von-Guericke” University
Magdeburg, Magdeburg, Germany, in 1994, af-
ter working on pulse power problems in excimer
lasers. After developing gas and solid-state lasers at
Lambda Physik GmbH, Goettingen, Germany, and
LISA Laser Products OHG, Lindau, Germany, she
received the Ph.D. degree from the University of
Kassel, Kassel, Germany, in 1999.
In 1999, she was with eupec GmbH, Warstein,
Germany, as an R&D Engineer and was responsible for the development of
the 1700-V IGBT module family, until 2004. Since 2005, she has been with
SMA Solar Technology AG, Nietestal, Germany. Her special scientific interest
is integration of power electronic devices.