© JAIN ONLINE Self-Learning Material Semester: 1 Course Name: Computer Organization & Architecture Course Code: 21VMCOC105 Unit Name: Input/Output (1/0) Organization Proprietary content. All rights reserved. Unauthorised use or distribution prohibited This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,Table of Contents UNITS 1 Overview 1 Objectives 1 Learning Outcomes 1 Pre-Unit Preparatory Material 2 3.1 Introduction 2 3.2 Accessing I/O Devices 2 3.3 Interrupts: Interrupt Hardware 3 3.1. ‘Types of Interrupts 4 3.4 Direct Memory Access 4 3.4.1 DMA Controller 5 3.5 Buses 6 3.5.1 ISA Bus 6 35.2 BISA Bus 6 3.6 Standard 1/0 Interfaces 6 37 PCE 3.8 SCSI Bus 8 3.8.1 Bus Arbitration 9 3.9 Universal Serial Bus (USB) 9 3.9.1 Port Limitation 10 3.9.2 Device Characteristics 10 3.9.3 Plug and Play 10 Proprietary content Al Hants JeRrvat MBAS ARPES AM putin Prohibited. ‘Sharing or publishing the contents in part or full is liable for legal action,3.9.4 USB Architecture ul 3.9.5 Addressing ul 3.10 Conclusion I 3.11 Glossary Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,UNIT 3 INPUT/OUTPUT (1/0) ORGANIZATIO! Accessing 1/0 Devices, Interrupts: Interrupt Hardware, Direct Memory Access, Buses, Standard I/O Interfaces — PCI Bus, SCSI Bus, Universal Serial Bus (USB). 3.3.1 Overview The /O architecture of the computer system its external interface. This architecture is designed to provide the operating system with the knowledge required to control the F/O operation efficiently, to monitor communications with the outside world. Three key approaches are used for I/O programming; VO programming under the direct supervision of the application requiring /O operation; I/O interrupting-driven programming with the 1/0 instruction and persistent execution before the I/O hardware interrupts to signal ends of VO operations; and Direct Memory access (DMA), with specialized 1/0 technology. /O technology. 3.3.2 Objectives You'll learn in this unit — 1. Computer instructions and execution of the program including call and return branching and subroutines transactions. Computer commands, data and applications assembling language. Input/output programs managed. 2 3. 4, Address register and memory operand control processes. 5. Exploring in-depth /O organization 6. Capability to evaluate the device and interface hardware and software challenges. 3.3.3 Learning Outcomes At the end of this Unit, you would - ¥_ Understand the various Program-controlled I/O Operations ¥ Understand the data transfer interfaces Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. Sharing or publishing the contents in part or ful is liable for legal action,3.3.4 Pre-U: Preparatory Material > “COMPUTER SYSTEM ARCHITECTURE, MORRIS M. MANO, 3RD EDITION, PRENTICE HALL INDIA”. > Mano, M. Morris (October 1992). Computer System Architecture (3rd ed.). Prentic Hall, ISBN 0-13-175563-3 3.1 Introduction The arrangement of input & output depends on the size of the computer and the relevant device. The computer's I/O subsystem guarantees an effective style of contact among the central device & the external world, The most used input-output devices are Printer, Keyboard, Monitor, Mouse & ‘Magnetic tapes. The computers which are operated directly by the computer shall be linked online. The Input-Output Interface offers a way to transfer information between external I/O devices and internal storage. Peripherals of device connections need to be interfaced with the central processing unit through specific networking connections, The contact link helps to overcome gaps between the central computer and each peripheral computer 3.2 Accessing I/O Devices ‘A single bus configuration is basic preparation for linking /O devices to a computer. The bus allows the sharing of information between all the connected devices. It consists usually of 3 lines used to relay signals, data & power. A single set of addresses is allocated to each /O unit. The unit, which identifies this address, replies to the instructions given by the surface known when the processors place a certain address on the address line. The processor needs a reading or writing procedure and the demanded information is transmitted over data lines, and the arrangement is called memory-mapped I / O because I/O machines & the memory share the same address space. With the memory-mapped 1/0, you can use all device commands that can reach the memory to regular channels from or to I/O devices. For instance, the instruction if DATAIN is the keyboard input buffer address, Proprietary content. Alll rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,Move DATAIN, RO Reads and stores the DATAIN data in the RO processor register. Likewise, the instruction Move RO, DATAOUT Directs the RO register fillings to DATAOUT position that may be a display unit or printer output data buffer. The bulk of computers use VO mapped to memory. In and out instructions for conducting V/O transfers are given by some processors. When designing a computer machine grounded on these processors, the creator has the choice to connect 1/0 devices to the special VO address space or directly insert them into the address space. To see how they can respond, the I/O devices examine the low band bits of the address bus. The necessary hardware to connect an I/O to the bus. The address translator helps the machine to accept its address when this address is placed on the address lines. The archive includes the data to or from the processor. The I/O system operating status registry provides information, The data and status registers are all associated and allocated to the data bus. The interface circuit of the eystom consists of the address transmitter, the data & status records & the control circuit needed for VO transfer synchronization. 3.3 Interrupts: Interrupt Hardware An interrupt is a warning for the computing architecture that indicates an incident that requires urgent attention to the processor issued by hardware or software. Our processor helps to track the coordination in the software for the SIN & SOUT bits. The processor then does little more than run the endless loop. The principle of interrupts can be used to prevent this condition by input/output systems. The processor could be indicated on a different line named the interrupt request line when the input/output unit is prepared. The processor reads the input-output equipment & thus eliminates the mechanism for waiting for an endless loop upon receipt of the interrupt. Proprietary content. All rights reserved, Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,3.3.5 Types of Interrupts Even though interrupts have a top importance than additional signals, interrupts of several kinds occur but interruptions of basic form are > 1) Hardware Interrupts: Hardware interrupts are named when the signal to the processor is from other equipment or hardware. Two types of hardware interrupts can be grouped into > © Maskable Interrupt ¢ Non-Maskable Interrupt 2) Software Interrupts: Interrupt applications may also be separated into 2 forms > © Normal Interrupts © Exception 3.4 Direct Memory Access Data is transmitted through the memory bus in and out of the direct memory access (DMA) interface, Data transmission among a quick storage mechanism like a magnetic disk & the memory is always inadequate by CPU sp ed. Removal of the CPU from the route & memory bus direct control will improve communication speed on the peripheral computer. Direct Memory Access is this transfer technology The CPU is idle and has no memory bus power during the transmission of the DMA. A DMA controller moves the buses directly between the I/O and the memory. In several cases, the CPU may be put idle. The deactivation of the bus by complex control signals is a common approach used extensively in the microprocessor: © Bus Grant (BG) © Bus Request (BR) The 2 control signals in the CPU enable the propagation of the DMA. The DMA controller uses the Bus Request (BR) feedback to query the CPU. The CPU stops the execution of the current Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,directive while this entry is active and sets a high impedance on the address bus, data bus, and reading lines. This implies that the output is isolated by high Impedance conditions, asus }¢——> Address Bus Bus Request ————>} BR os pBus }———> Data Bus High Impedance (disable) when BG isenable RD |-——> Read BusGrant_ <———]_ BG WR -}———> write Fig. 1: CPU bus signal for DMA transfer To notify external DMA the CPU allows the Bus Number (BG) output to handle buses now without, a memory transfer processor. As the transmission stops, the Bus Order (BR) thread is deactivated. The CPU deactivates the Bus Grant (BG), takes over the buses & goes back to the usual service. In many ways, the transition can be carried out: 1) DMA Burst: A block categorization composed of a few memory words is transmitted into the nonstop explosion in DMA Burst, while the memory bus master is a DMA controller. 2) Cycle Stealing: the DMA controller will relay one data word at a time by cycle stealing and must then retum the bus power to the CPU. DMA Controller: DMA controller has to connect to the CPU and I/O machine on the standard interface circuits. 3.4.1 DMA Controller To connect with the CPU & 1/0 modules, the DMA controller requires the normal interface circuits, There are three registers in the DMA controller: Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or ful is liable for legal action,1) Address Register: The address box provides an address for the desired location of the memory. 2) Word count Register: WC includes the transferable number of terms. For each word shift, the register is inereased/deet .ed by one, internally checked for none, 3) Control Register: Register Control Determines the transfer mode. 3.5 Buses Each bus has three separate communication networks. The Address Bus, a one-way route that makes the information in only one direction, offers information about where data is stored in memory. The data bus is a symmetric route to and from the main memory of the real data. The control bus holds the timing and control signals used to organize the entire computer's operations. Consider that as a policeman in traffic. 3.5.1 ISA Bus Most of the oldest buses currently in use are the Industry Standard Architecture bus (ISA). While replaced by faster buses, ISA still has many conventional devices, such as cash registries, CNC machines, and barcode scanners, connected to it. 3.5.2 EISA Bus An update to ISA is an Extended Standard Architecture or EISA. It doubled 16-32 data channels and permitted the bus to be shared by more than 1 CPU. And if it is deeper than the ISA, it has the same width and can be attached to older computers. 3.6 Standard I/O Interfaces The bus that indicates the chip problem is the processor bus. Devices that need a very fast connection, such as the principal memory, are directly connected to the processor. This requires only a few computers to be electrically wired in this manner. Usually, a different bus with more applications is available in the chipset. Both coaches are linked to a circuit called the bridge which decodes the signals of one bus to the other. Telephones connecting to the expansion bus are Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,normally directly linked to the processor bus. The biggest distinction is that the bridge circuit creates a slight difference between the data transfer system and the PC. A norm for the processor bus cannot be specified. This bus arrangement is directly related to the processor architecture, The electrical properties of the processor chip, such as clock speed, are also important, This does not influence the expansion bus, and a generie signaling method can also be used, There have been many guidelines established, Some have been created by necessity since a certain concept has worked commercially. For example, [BM built a bus that was then referred to as ISA by PC AT for its personal computer (Industry Standard Architecture). Certain standards have been established through industrial collaboration, even among rivals who share a shared interest in incompatible goods. In some cases, institutions such as the IEEE, the ANSI, and international associations such as the ISO have blessed and accorded these norms official status. More than one bus standard can be used on a given device. A standard Pentium machine has both PCI & an ISA bus, which helps the user to select an extensive variety of appliances. Main Memory Processor Bus Processor Bridge PClbus Additional scst a use Isa memory controller interface Controller Interface Fig. 2: Block diagram of computer system using different interface standards Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp>@gmail.com only. Sharing or publishing the contents in part or ful is liable for legal action,3.7 PCI (Peripheral Component Interconnect) The PCI bus is a prime instance of a system bus that originated from a standardization neces It supports a common CPU bus bit feature, independent of any individual processor. It supports features. CPU devices connected to the PCI bus are normally linked directly to the processor board. In the memory of the CPI J, addresses are allocated. The PCI meets a series of bus specifications that have mostly been used on IBM computers. Early PCs were using the XT 8-bit bus, which roughly mirrored the Intel processors’ signals 80x86. Later, on PC the 16-bit bus was recognized as the ISA bus on computers. The 32-bit expanded form of the EISA coach is known. The microchannels used on IBM PCs and the NuBus used on Macintosh computers were both built in the eighties with similar features. The PCI is configured as a low-cost bus and is genuinely independent of the CPU. Its architecture expected an increasingly rising requirement on bus bandwidth to accommodate high-speed disks, video, graphic & multiprocessor advanced needs. As a consequence, nearly a decade after its inception in 1992 the PCI remains popular as an industry standard. A plug-& -play functionality for linking /O devices is one of the significant pioneers of the PCI. The user essentially attaches the interface board of the computer to the bus to attach a device. The rest is protected by the software 3.8 SCSI Bus Small Programming Device Interface is the acronym SCSI. It refers to a standard bus specified under designation X3.131 by the American National Standards Institute (ANSI). Devices such as disks can be linked to a device with a 50-wire cable, can reach 25 meters, and can transport data in the original standard specifications at speeds of up to 5 megabytes The SCSI bus typically has undercut various modifications & has improved quite quickly, almost ‘he SCSI-2 & SCSI-3 have been clarified and every two years, its data transmitting capabilities. each option has a number. A SCSI bus could have a narrow bus with 8 lines and data transmission ata time of one byte. Otherwise, there are 16 data lines in a wide SCSI bus, and 16 bits of data are transmitted at a time. The electrical signaling system used also provides many alternatives. Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,Controller devices connecting to the SCSI bus are not the same as devices linked to the processor bus. The SCSI bus is linked by a SCSI controller to the processor bus. This controller uses DMA for data packets to be passed from the main memory into the computer. A packet may contain data blocks, processor-to-controller commands, or device status information. A SCSI bus-related controller is a two-type one - an initiator or a target. An initiator is capable of choosing a certain target for the operation and transmitting commands. The processor-side interface, including the SCSI control, certainly can serve as the initiator. The disk controller is a goal. The commands the initiator receives are executed. The initiator links the desired objective logically. After this link has been created, commands and data bursts may be suspended and restored when required, During the suspension of a certain link, other devices may use a bus to transfer information. One of the main advantages of the SCSI bus is its ability to overlap data transfer demands. 3.8.1 Bus Arbitration If the -BSY signal is inactive, the bus is open. In this state, every controller can request the use of the bus. Since a request can be created at a time by two or more controllers, an arbitration scheme is required. The bus is ordered by the controller to insert the -BSY signal and confirm its corresponding data line. The SCSI bus uses a distributed, straightforward arbitration method where the controllers run the bus at the same time. 3.9 Universal Serial Bus (USB) It was developed by numerous networking firms such as compaQ, Intel Microsoft, Hewlett Packard, ete. 2 link rates are provided by USB: -> Low speed (1.5 megabit/s) ~> Full speed (12 megabits/s) Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,‘A 3rd speed termed high speed (480 Megabits/s) has been added in the new bus update (USB 2.0). The USB has several main goals for this purpose: ~ It gives a simple, low-cost intercomnection scheme that overcomes problems because of the small number of 1/0 ports on a device. > It adapts to a broad variety of /O computer data transfer functionality, including telephone and internet access. > Improving usability with a plug-and-play operating mode. 3.9.1 Port Limitation The parallel and serial port provide a general link when linking a range of low to medium-speed devices to a computer. There are just a few ports on a computer, ‘The customer should also know how to set up the system and applications and connect new ports, open the machine box and then load new interface cards. The purpose of a USB is to connect a lot of devices without opening a computer box to the computer machine. 3.9.2. Device Characteris s The system that is attached to the machine has several features, i.c., © Speed e Volume © Data transmission scheduling limits. In this sense, the sampling process produces a constant stream of the di x tized sample, aligned h the sample clock, which is considered isochronous, which results in the isolation of consecutive events by the same amount of time. For video and image data transmission, greater bandwidth is needed, Larger storage devices like CD-ROM and hard disk have to deliver a transmission speed of 40mbps or SOmbps on their system connections Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,3.9.3 Plug and Play Playing and plugging means a new gadget can be attached anywhere, such as an extra speaker, while the machine runs. The machine automatically senses the presence of the new computer, recognizes the required device driver software and other requisite facilities to connect with it. It can be used from hardware through to the OS and the application program on any level of the device. 3.9.4 USB Architecture The bandwidth is low cost, scalable and wide The attached 1/0 devices need to be placed somewhere away from the computer. An extensive bus of 8, 16, 32 or more bits can be used for higher bandwidth. The serial transmission format for USB is used because the serial BUS is low cost and versatile. HUB is a mid-point of influence between I/O devices and the host. The Root HUB ties the whole tree with the host. Simple point-to-point connections are created. The USB functions solely on a voting basis. ‘A message can be sent by both devices only in response to a poll that cannot be sent by the two devices simultaneously. 3.9.5 Addressing When a USB is linked to a host device, the root hub of the USB is attached. The host program communicates through the transmission of data packets to the appropriate device in the USB tree for each of the devices connected to the USB Each USB device, whether its HUB or I/O device, will be provided with a 7-bit address. This address is a local USB tree that is not connected at all to the processor bus address. 3.10 Conclusion There are 3 fundamental methods to /O transition. The easiest strategy is programmed 1/0, in which the processor carries out all essential functions managed directly by program instructions. The second method is focused on interrupt use. The third I/O method requires DMA, and without Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,persistent processor interference, the DMA controller transfers the dataset with an /O unit and main memory. The DMAQ controller and the processor share memory access. There are three SCSI, PCI & USB. They serve diverse approaches that common protocols for connectednes fulfill the needs of the different devices and demonstrate the growing importance of plug-in technologies to improve user experienc: 3.11 Glossary Interrupt — A signal transmitted to the processor by an I/O system if an error occurs, or if support to complete the 1/0 is required. The execution of the current program is normally interrupted by an interrupt. Input/Output — instructions or information is passed to or from the memory or secondary storage (e.g., disk drive). Memory ~ a list of records and storage devices that store the statechart of your machine. User Interface and I/O Management — Included is the control of the configuration and display specifications of windows, e.g, feedback from the pointing instruments, mouse, and user-input went from the keyboard, in which application software is managed. Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or full is liable for legal action,Proprietary content. All rights reserved. Unauthorised use or distribution prohibited. This file is meant for personal use by nandinibj.hp@gmail.com only. ‘Sharing or publishing the contents in part or ful is liable for legal action,