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 A subroutine is a special segment of program that can be called for

execution from any point in a program.
 An assembly language subroutine is also referred to as a
“procedure”.
 Whenever we need the subroutine, a single instruction is inserted
in to the main body of the program to call subroutine.
 To branch a subroutine the value in the IP or CS and IP must be
modified.
 After execution, we want to return the control to the instruction
that immediately follows the one called the subroutine i.e., the
original value of IP or CS and IP must be preserved.
 Execution of the instruction causes the contents of IP to be saved
on the stack. (this time (SP) = (SP) -2 )
 A new 16-bit (near-proc, mem16, reg16 i.e., Intra Segment) value
which is specified by the instructions operand is loaded into IP.
 Examples:
CALL 1234H
CALL BX
CALL [BX]

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•Generally modify CS:IP
•Causes modification in execution sequence (of
instructions)
• When such a program flow change occurs:
a) Instructions in the BIU inst. queue become invalid
b) BIU directly fetches CS:IP instruction from
memory
c) While EU executes new instruction, BIU
flushes/refills inst. queue
 Two types of program control transfer
instruction
 Unconditional transfer instructions e.g.
 CALL, RET, interrupt, JMP instructions

 Conditional transfer instruction e.g.

 Jump conditional, loop (un)conditional

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• Group of instructions that perform single task
– (can be used as) a SUBROUTINE

call - invokes subroutine - pushes ip

ret - returns from subroutine - pops ip

• Uses assembly directives: PROC and ENDP

• Must specify

NEAR - intrasegment
FAR - intersegment

• Difference is op-code of ret

NEAR - pops IP
FAR - pops CS, pops IP
• Differs from jmp since return address on stack

NEAR call: 3 bytes - 1 opcode and 2 for IP

FAR call: 5 bytes - 1 opcode, 2 for IP and 2 for CS

• call with operand - can use 16-bit offset in any register

except segment registers

Example:
call bx ;pushes ip then jumps to cs:[bx]
8
 mov si, OFFSET COMP
call si
.
.
.
COMP PROC NEAR
push dx
mov dx, 03f8h
in al, dx
inc dx
out dx, al
pop dx
ret
COMP ENDP
 NEAR - pops 16-bit value places in
IP
FAR - pops 32-bit value places in
CS:IP
• Type is determined by PROC directive
 Allows programmer to skip program sections and branch
to any part of memory for the next instruction.
 A conditional jump instruction allows decisions based
upon numerical tests.
 results are held in the flag bits, then tested by conditional
jump instructions
 LOOP and conditional LOOP are also forms of the jump
instruction.
 SYNTAX
JMP - unconditional jump
JMP operand
 Three types: short jump, near jump, far jump.
 Short jump is a 2-byte instruction that allows jumps or
branches to memory locations within +127 and –128
bytes.
 from the address following the jump
 3-byte near jump allows a branch or jump within ±32K
bytes from the instruction in the current code segment.
 5-byte far jump allows a jump to any memory location
within the real memory system.
 The short and near jumps are often called intrasegment
jumps.
 Far jumps are called intersegment jumps.
Called relative jumps because they can
be moved, with related software, to
any location in the current code
segment without a change.
The short jump displacement is a
distance represented by a 1-byte signed
number whose value ranges between
+127 and –128.
A near jump passes control to an instruction in
the current code segment located within ±32K
bytes from the near jump instruction.
 Near jump is a 3-byte instruction with opcode
followed by a signed 16-bit displacement.
 Signeddisplacement adds to the instruction pointer (IP)
to generate the jump address.
 because signed displacement is ±32K, a near
jump can jump to any memory location within
the current code segment
 Obtains a new segment and offset address
to accomplish the jump:
 It has 5-byte instruction
 bytes 2 and 3 of this 5-byte instruction contain
the new offset address
 bytes 4 and 5 contain the new segment
address
16
 Always short jumps in
 limits range to within
+127 and –128 bytes
from the location
following the
conditional jump
 Allows a conditional
jump to any location
within the current
code segment.
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• Task: Jump to a label if unsigned AX is greater than BX
• Solution: Use CMP, followed by JA

Mov ax, 56h

Mov bx, 34h
cmp ax,bx
ja Larger

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 Conditional Jumps based on more than one flag are
used after a CMP (compare) instruction.
 JBE - Jump if Below or Equal
 JNA - Jump if Not Above

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 JNBE - Jump if Not (Below or Equal)
 JA - Jump if Above

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 JLE= Jump if Less than OR Equal
 JNG = Jump if Not Greater than

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 JNLE- Jump if Not (Less than OR Equal)
 JG = Jump if Greater than

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 JL- Jump if Less than
 JNGE - Jump if Not (Greater than OR Equal)

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 JNL - Jump if Not Less than
 JGE = Jump if Greater than OR Equal

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A combination of a decrement CX and the JNZ
conditional jump.
 LOOP decrements CX.
 if CX != 0, it jumps to the address indicated
by the label
 If CX becomes 0, the next sequential instruction executes
 Syntax:
LOOPE destination
LOOPZ destination
 Logic:
 CX  CX – 1
 if CX > 0 and ZF=1, jump to destination
 Usefulwhen scanning an array for the first element
that does not match a given value.

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 LOOPNZ (LOOPNE) is a conditional loop instruction
 Syntax:
LOOPNZ destination
LOOPNE destination
 Logic:
 CX  CX – 1;
 if CX > 0 and ZF=0, jump to destination
 Useful
when scanning an array for the first element
that matches a given value.

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 HLT instruction – HALT processing
 HLT instruction will cause the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The only way to get
the processor out of the halt state are with an interrupt signal on
the INTR pin or an interrupt signal on NMI pin or a reset signal on
the RESET input.
 NOP instruction
 This instruction simply takes up three clock cycles and does no
processing. After this, it will execute the next instruction. This
instruction is normally used to provide delays in between
instructions.
 ESC instruction
 whenever this instruction executes, the microprocessor does NOP
or access a data from memory for coprocessor. This instruction
passes the information to 8087 math processor. Six bits of ESC
instruction provide the opcode to coprocessor. when 8086 fetches
instruction bytes, co-processor also picks up these bytes and puts
in its queue. The co-processor will treat normal 8086 instructions
as NOP.
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 LOCK instruction
 This is a prefix to an instruction which makes sure that during
execution of the instruction, control of system bus is not taken by
other microprocessor, in multiprocessor systems, individual
microprocessors are connected together by a system bus. This is
to share the common resources. Each processor will take control
of this bus only when it needs to use common resource. The lock
prefix will ensure that in the middle of an instruction, system bus
is not taken by other processors. This is achieved by hardware
signal „LOCK‟ available on one of the CPU pin. This signal will be
made active during this instruction and it is used by the bus
control logic to prevent others from taking the bus. Once this
instruction is completed, lock signal becomes inactive and
microprocessors can take the system bus.
 WAIT instruction
 this instruction takes 8086 to an idle condition. The CPU will not
do any processing during this. It will continue to be in idle state
until TEST pin of 8086 becomes low or an interrupt signal is
received on INTR or NMI. On valid interrupt, ISR is executed and
processor enters the idle state again.
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 Interrupt is a procedure that interrupts whatever the CPU
program is currently executing.
 Interrupts are particularly useful when interfacing
 I/O devices that provide or require data at relatively low data-
transfer rates , eg a keyboard.
 During an interrupt, the CPU will perform pre-defined
operations according to the interrupt nature so the
microprocessor can execute other software before the
interrupt occurs
 8086 can implement 256 different types of
interrupts
 The interrupts are divided into 5 groups
 external hardware interrupt,
 software interrupts,
 internal interrupts,
 nonmaskable interrupt, and
 reset
 The interrupt routines for external hardware,
software, and nonmaskable interrupts can be
defined by user (you can write your own ISR)

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 Type 0 – highest priority
 Type 255 – lowest priority
 Example – an internal interrupt, divide error, is a
type 0 interrupt
 Divide error : divide by zero
 Overflow is type 4
 When a CPU is performing an interrupt service
routine, it can be interrupted by a higher priority
interrupt. If a lower priority occurs, the newly
occurred interrupt must wait

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 For 8086 the table is stored in memory location
(address) 00H – 3FFH (1K)
 Address pointers identify the starting locations of
their service routines in program memory For the
8086, each pointer requires two words (4 bytes)
 The higher address word is the base address and
will be loaded into the CS register
 The lower address word is the offset address and
loaded into the IP register

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 INT performs as a far CALL
 not only pushes CS and IP onto the stack, also pushes the
flags onto the stack
 The INT instruction performs the operation of a
PUSHF, followed by a far CALL instruction.
 Software interrupts are most commonly used to call
system procedures because the address of the
function need not be known.
 The interrupts often control printers, video displays,
and disk drives.
 INTreplaces a far CALL that would otherwise be
used to call a system function.
 INT instruction is 2 bytes long, whereas the far CALL is 5
bytes long
 Each time that the INT instruction replaces a far
CALL, it saves 3 bytes of memory.
 This can amount to a sizable saving if INT often
appears in a program, as it does for system calls.
 When a software interrupt executes, it:
 pushes the flags onto the stack
 clears the T and I flag bits
 pushes CS onto the stack
 fetches the new value for CS from the interrupt vector
table
 pushes IP onto the stack
 fetches the new value for IP from the vector
 jumps to the new location addressed by CS and IP
 Used only with software or hardware interrupt service
procedures.
 IRET instruction will
 pop stack data back into the IP
 pop stack data back into CS
 pop stack data back into the flag register
 Accomplishes the same tasks as the POPF followed by a far
RET instruction.
 When IRET executes, it restores the contents of IF and TF
from the stack.
 preserves the state of these flag bits
 If interrupts were enabled before an interrupt service
procedure, they are automatically re-enabled by the IRET
instruction.
 because it restores the flag register
 8086 operates in single processor (minimum mode)
or multi processor (maximum mode) configurations
to achieve high performance.
 The 8086 signals can be categorized in 3 groups.
 Signals having common functions in minimum as well as
maximum mode.
 Signals which have special functions for minimum
mode.
 Signals which have special functions for maximum
mode.

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 AD15 – AD0
― Acts as address bus during the first part of the machine
cycle and data bus for the remaining part of the machine
cycle
A19/S6 – A16/S3
During first part of machine cycle these are used as most
significant address lines for memory.
During remaining part these are used to output the status
(type of operation performed in the cycle)
S5 – gives the current setting of interrupt flag (IF)
S6 – always zero

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 S4 and S3 – together indicates which segment register
is presently being used for memory access.

 BHE/S7: Bus High Enable/Status

 The bus high enable signal is used to indicate the transfer
of data over the higher order (D15-D8) data bus.
 If BHE is low then D15-D8 used to transfer data.

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BHE A0 Indication
0 0 Whole word i.e AD15 – AD8

0 1 Upper byte from odd address AD15-AD8

1 0 Lower byte from or to even address AD7-AD0

1 1 None

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 READY – If the signal is low then the 8086 enters into
wait state and it is used primarily to synchronize slower
peripherals with the processor
 INTR: Interrupt Request - Sampled during the last
clock cycle of each instruction to determine the
availability of the request. If any interrupt request is
pending the processor enters the interrupt service
routine.
 TEST – Used by „WAIT‟ instruction. If TEST=0, execution
will continue, else processor remains in an idle state.

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 NMI Non Maskable Interrupts - Causes an
interrupt request to the processor and is not
maskable internally by software
 RESET -This input causes to processor to
terminate the current activity and start
execution.
 Clears the FLAGS, IP, DS, SS, ES and Instruction
queue and then sets CS to FFFFH.
 Signal must be high for at least 4 clock cycles.
 When RESET is removed, 8086 will fetch its next
instruction from FFF0H

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CLK: Clock Input -provides the basic timing for
processor operation and bus control activity (External
crystal generator )
 Vcc -5V power supply for the operation of the internal
circuit
 GND - Ground for the internal circuit
 MN/MX - Decides whether the processor is to operated
in either minimum or maximum mode.

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 INTA: Interrupt Acknowledge - signal is low, the
processor has accepted the interrupt
 ALE: Address Latch Enable - Signal provided by 8086 to

demultiplex the AD0 – AD15 into A0 - A15 and D0 – D15

 DEN - Data Enable – informs the transceivers that the
processor is ready to send or receive data
 DT/R - Data transmit/Receive - used to decide the
direction of data flow
 DT/R = 1(HIGH) Processor sends out data
 DT/R = 0 (LOW) Processor receives data

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 M/IO – used to distinguish memory data transfer (HIGH)
and I/O data transfer (LOW)
 WR – Write Output – WR is low whenever the 8086 is
writing data into memory or an I/O device
 HOLD input, HLDA output – If Hold is high, indicates to
the processor that another master (DMA) is requesting
the bus access. After receiving the HOLD request, issues
the hold acknowledge signal on HLDA pin.

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54
 QS0,QS1 (Output) – reflects the status of the
instruction queue

 S2,
S1,S0 – status signal indicates the type of transfer
taken place

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 LOCK – (output) - indicates that other system bus masters
will be prevented from gaining the system bus, while the
LOCK=0.
 RQ/GT0, RQ/GT1 (Bus Request/Grant)– By using bus
request signal another master can request for the system
bus and processor communicate that the request is
granted to the requesting master by using grant signal
 RQ/GT0 has higher priority than RQ/GT1

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 The 8086 has a combined address and data bus
commonly referred to as a time multiplexed address
and data bus.
 Basically, all the processor bus cycles consist of at least
4 clock cycles referred to as T1, T2,T3 and T4·
 The address is transmitted by the processor during T1.
It is present on the bus only for one cycle.
 During T2, i.e. the next cycle, the bus is tristated for
changing the direction of bus for the following data
read cycle.

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 The data transfer takes place during T3 and T4. In case,
an addressed device is slow and shows 'NOT READY status
the wait states T w are inserted between T3 and T4.
 These clock states during wait period are called idle
states or wait states.
 The processor uses these cycles for internal housekeeping.
 The address latch enable (ALE) signal is emitted during
T1, by the processor (minimum mode) or the bus
controller (maximum mode) depending upon the status of
the MN/MX input.
 The negative edge of this ALE pulse is used to separate
the address and the data or status information.

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