(CHUONG 2 KIEN TRUC PHAN CUNG HQ AVR ATMEL - ATmega324P- 2.1 TONG QUAN HQ AVR AVR co ban dirge thiét ké béi 2 sinh vién ctia Hoe vign céng nghé Na Uy (Norwegian Institute of Technology) li AIEgil Bogen va Vegard Wollan, Sau dé duge cng ty Atmel mua Jai va phat trién vao nm 1996. AVR la vi diéu khién 8 bit dang RISC (Reduced Instruction Set Computer) theo kién tric Harvard, Ngoai trir AVR32 la vi digukhign 32 bit, Tén goi AVR khong 6 khai niém nhat dinh, nhung thudng duge hiéu [a viét tit tén cia 2 nguoi thiét ké: AVR - Alf and Vegard RISC. 2.1.1 D§e tinh chung AVR = B6 nhé chuong trinh ROM: khéng gian b§ nhé cé thé lén téi 8MB, tuy nhién khéng phai tat ca déu duge dat mite dé. Khi ghi ROM, kich thurée cia ROM cé thé tir 1KB dén 256KB ty theo loai. AVR sir dung bé nhé Flash on-chip cé thé ya nhanh trong vai gidy. - BO nhé dir ligu gm RAM va EEPROM: AVR cé khofigjgian RAM thightla 64KB, tay theo loai. BO nhé RAM chia thinh 3 phan: cdc thanh ghi lam vige d& dui (gereral purpose working registers), b6 nhé 1/0 (/O memory), va\b9,nllG SRAM bén teeing, Tat ca cde loai AVR deu c6 32 thanh ghi kim vige da dung, nhiting sé khéomhau\é kich thuée ela SRAM va bd nhé 10. AVR ding EEPROM chifa etext ligu 06 inh. = Cae chan I/O: c6 tir 3 dén 86 chan dé ynit/nhap tity leat = Ngoai vi: cdc ngoai vi chuan got'B6 bién ddi ADO, b§ dinh thdi va cdc loai giao tiép ndéi ép USART (Universal($ynehrdhous Asynthrohous Receiver Transmitter), I2C (TWD) va SPI. Ngodi ra mdi loai'eo th¢6 them ngogi Wr Sho mhigm vu rigng, 2.1.2 Cac nhom trong ho Wi diéu khién AVR Ho AVR chiathanh 4 nhorits Classic, Mega, Tiny va nhom mue dich dae biét (special purpose) - Classic AVR WAT9OSxxxx): 1a nhom vi diéu khién géc, hign khong cdn duge str dung. - MegdaVR (ATmegaxxxx): 1a nhom ungoai vi khéc fibétu. Do vay nhém nay c6 nhigu img dung réng rai cho cae thiét ké Khéc hau. Bang 2.1 Cac chip tiéu biéu trong nhom ATmega 1C ROM ‘So chan chuong trinh i Logi vo ATmega8 8K TOQFP32, PDIP28 ATmegai6, 16K c TOFP44, PDIPAO 32K c TOFP44, PDIP4O GaK s TOFP64. MLF64 128K TQFP100. CBGA Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM 1~ Tiny AVR (ATtinyxsxx): e6 it Ignh va kioh thude nhé so véi A Tmega. = AVR cho mue dich die biét: cde IC nay ciing thude cae nhém trén nhumg duge trang bj thém dé thiét ké img dung cu thé. Vi dy nhu b6 diéu khién USB, b6 dicu khién LCD, b@ digu khién mang cue bé. IC AVR c6 ma sé bit diu 1a chi AT (Atmel) va tén nom, theo sau la di Hau hat ede truémg hgp theo day sé nay cé thé cho biét dung Iuong ROM eta AVR. Quy tae 1a tir trai sang phai, lay s6 c6 gia tri lon nhat 6 dang 2". Vidy 21: — ATmega324 thi gid tri diing theo quy tic li 32, vay 06 32KB ROM. ATtiny44 thi c6 4KB ROM Trong gido trinh nay, ching ta sit dung ATmega324P do e6 nhigu tmg dung rong rai Ngoai ra n6 c6 dang PDIP dé ding thye hign vige Lip rap mach thye té, iu héi on tip 1. Cho biet tén cde nhém thuéc ho AVR. 2, Nhom nao c6 kich thurée nho nit, 3. Cho biét kich thuée ROM chuong trinh cla: (aATtiny25 (b)ATmega324_—(c)A Timegal 280 4. Cho biet kich thuée RAM cia: (a)ATmega8 —_(b)ATmega32 (@ATmegal 280 22 VI pU KHIEN ATmega324P 2.2.1 Dic tinh ky thugt ATimega324P Li vi digu KhigiS bit CMOS,cdug suat thi AVR. Bing vige thue hign Wenhvchi trong 1 chy KY Rung mhip, d6 1 MIPS (trigu Ignh nf9iia9) theo timg Mhz, theo kién trac RISC nang cao digu khién c6 thé dat duge te * Kién tric RISC nang cao + C6 131 enh ~ Da sé cde lénh thue thik] chiky xung nhip. ~ 32 thanh ghi Kim vig@da dung & bi ~ C6 thé dat t6i 20 MIPS W6i tin sé 20MEHz. ~ B6 nhan 2 ciyky on-chip * Cac thanh phan bé nhé- + BO nhé chug trinh Flash 32KB - BO nhé EEPROM 1KB - BO nhé SRAM 2KB © Cie ngoai vi ~ 32 during 1/0 lip trinh duege ~ 2.6 dinh thi/b@ dém 8 bit v6i bG chia tan riéng bigt va ché d9 so sinh = 16 dinh thi/b9 dém 16 bit véi b6 chia tan riéng bigt, ché d6 so sinh va ché d6 capture. - Bé dém thoi gian thy vai bO dao dong riéng biet. 6 kénh diéu ché dé réng xung PWM. Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM 2+ 8kénh ADC 10 bit, ngé vao don,ng6 vao vi sai lap trinh dirge 49 lgi (PGA) ~ Gio tiép n6i tiép 2 day 12C. - 2b§ USART lap trinh duge. iép SPI. ~ Bé dinh thi watchdog lap trinh duoc v6i bé dao déng on-chip riéng biét. ~ BG so sinh turong tr on-chip. ~ Nefit va wake-up trén cae chfin. + Cie tinh niing die biat + Mach khoi dong Power-on va bd phat hi ~ B6 dao ding RC didu chinh bén trong, = Cé nhiéu nguén ngat bén trong va bén ngoai. = C66 ché 46 ngii tid kigm nang hrong nguén. sut 4p nguén Brown-out lap trinh duge. + Die tinh kite + C6 cde dang déng g6i PDIP 40 chan, TQFP 44 chan va YOFN/QFN/MLE.44 chan, ~ Bign ip hogt dong 2.7V — 5.5V. = Tan 6 lam viée 0 - 20MHz. + STAG chuan IEEE 7149.1 jap nap chong trimh frye tiép trén hé théng\tang sir dung. 2.2.2 So d6 khoi Bara ce oscarer Toatvece — PeSo pore ‘Himh 2.1 So dé khéi AVR (a Tra 2 5p Chasm 2 BO Mn Eten Tie DEBTPHCM 32.2.3 So’ dé chan (PowsTsixcxo7T0) Pe 4 40. pao (ADcOPCINTO) (POINTICLKOIT®) P81 Cl 2 39 pat (ADcUPCANTI) (PONTIONNT2/AINO) PB2 C} 3 38 B Paz (AnczmCaT2) (POINT HVOCOVAN:) PBS Cl 4 37 B Pas (ADCSPCNTS) (PONTI20c08KS) PEE C] 5 36 B pas (ancaPcNTs) (PaINTiaMos) Pes Cl 6 35 B PAs (ADCSPCINTS) (PaNTtanuso) P86 | 7 34 B pas (ancePenTe) (PanTissax) ps7 C3 33 5 par (anc7PcNT?) RESET {9 32 B AREF voc 10 315 oxo ow gt 30 B avec, xtaz 12 29 5 Per (rosczairzs) xtai 1328 B Pes croscupaintz22) (Pawr2aRxo0) POO Cc] 1427 Pos (TOLPCINT21) (Powr2srxD0) Po] 1528 Ps (rOOPCINTZ0) (ONTZERXOUINTO) PO2 C16 25 BPC (IMSPCINTIO) (PeINTarxoUINT!) POs ]17 24 fa Pee (TCKIPGNTIB) (PonTaaxcKtioctB) Pot C18 23 BPC (SDAPCINTI7) (PoNT290C1A) POs] 19-22 fa Peo (SCLPCINTIO} (PoINTsOIOCzB/CP) POS | 20 2B (a) Dang, 6 at (aDouPoNTs) Pas (ADCSPCNTS) as (ADCOPCNTS) Par (ADETPGNT) bree or (roscacmrzs) Pos (roscuPCINTZ2) bs cbvecivr23) Pot (orPcIT20) urxo0) POO » TOUT TOUoToT (PenT2400%8) PDS (roiranocearcr) De (PomTeri0025) & i z 2 (b) Dang vé TOFP/VQFN/QFL/MLF Hinh 2.2 So dé chan ATmega324P = VCC: dign ap nguén. La chan cung cp dign 4p nguén cho chip. Dign 4pngudn tiy2.7V dén 5.5V. - GND: chan ndi dit ibe Taah i Xie 1 Cuoomg 2 59 Mn Dif ie DUBETPHCH- RESET Ngo vao reset. Khi chan nay 4 mute thép dai hon dé dai xung t6i thidu thi st reset MCU. - XTALL,XTAL? Chin ké: néi véi mach dao dng thach anh hay mach dao ding RC tao xung clock hoat dong cho AVR. Khi dimg mach xung nhip ngoai thi néi vao chan KTAL1 - AVEC La chan dién ap ngudn cho b ADC - AREF Lachan dién 4p tham chiéu analog cho b6 ADC. - Port A (PA7:PAD) Port Ala port /O 8 bit 2 chidu cd dign tro kéo lén bén trong, o6 thé Lap tinh riéng cho ting bit, Khi reset cc chain port la 3 trang thai Port A cling cé chite nang khac nbuy sau: Bang2.2 Cac chite nang khac ciia chn Port A Chan port | Chirc nang luan phién ae ‘ADG7 (ADC input channel 7). PCINT7 (Pin Change intertupt ae ‘ADCS (ADC input channdbéy PCINTE (Pin Change Interrupt 6) a ‘ADCS (ADC iffput channel 5) PCINTS (PiniGhanee Interrupt 5) ad ADG4 (ADC "input channel 4) POINTS (Riff Change interrupt’) eel ADE3 (ADC input chgner's) PGINTS (Pin, Change interrupt 2) pao »€DC2 (ADC input channel 2) PCINT2 (Pig Change Interrupt2) x ‘ADG? YADG input channel 1) ‘ECINTA (Pin Change interrupt 1) we ‘ADCO (ADC input channel 0) PEINTO (Pin Change Interrupt 0) ADCT:0 06 chitc ndnglim & kénh ag6 vio cla ADC PCINT7:0 cé chic nang lam € ngubnngat Pia Change. - Port B (FB7:FBO) PortB la port UO 8 bit 2 chidu 05 dign trd kéo 1én bén trong, o¢ thé 1p trink riéng cho ting bit Khi reset cfc chain port la 3 trang thai Port oting thwe hién cae chive nang khac nb sau Gio Trinh TELS Cawemg 2 28 Mba Ein THDERETPHCM 5Bang 2.3 Cac chire nang khac cia chan Port B Chite nding luan phién ‘SCK (SPI Bus Masier clock input) PST | POINTS (Pin Changs Interrupt 18) poe | MISO (SPI Bus Master InputiSiave Output PCINT#4 (Pin Change Interrupt 14) pas _ | MOSI (SPI Bus Master Ourpuistave Input PCINT13 (Pin Change Interrupt 13) ‘SS (SPI Slave Select put) Pe4 | OCOB (Timor/Countor 0 Output Compare Match 8 Output) PCINT12 (Pin Chango Intorrupt 12) AIN! (Analog Comparator Negative Input) P83 | OCOA (Timet/Co ner 0 Cutput Compare Match A Output) PCINTH1 (Pin Changs Interrupt 11) ‘AINO (Analog Comparator Posttive Input) Pe2 | INT? (External Interrupt 2 Input) PCINTIO (Pin Change Interrupt 10) Tt (Timer/Gounter t External Counter Input) PBI | CLKO (Divided System Clock Output) PCINT® (Pin Change Interrupt 9) TO (Timer/ounter 0 External Counter Inpul) pao | XCKO (USAATO External Ciock inpuv@utput), PCINTS (Pin Cnange interrupt 8) + PBT: SCK/PCINTI5 SCK: 14 ngé ra xung clock khi lim master vitltng, vie xung clock khi lim slave trong giao tiép SPL PCINT15: nguén ng it Pir Change 15. - PB6: MISO:PCINTI4 ‘MISO: 18 ngowao’ due Ligu kthi ldimmaster va 1a ngo ra di ligu kthi lam slave trong giao tigp SPI. PCINT14,nguén ngat Pin Change 14. - PBS: MOSL-PCINT13 MOSE- 1a ng réid@ligwkhi lim master va la ng@ vao dit ligu khi lam slave trong giao tiép SPL. PCINT13: nguéwtigit Pin Change 13. - PBA: 5$/0COB/PCINT12 ‘SS: ngo vio Iya chon cdng slave ding trong giao tiép SPI. OCOB: ngs ra so sinh ngé ra Mateh B cita BG dinh thi/B@ dém 0. Chan nay ciing La ngé ra khi b@ inh thi & ché dg PWM. PCINT12: nguén ngit Pin Change 12 - PB3: AINV/OCOA/PCINTI1 AINI: ng6 vio im cita b6 so sinh tuong ty (analog comparator). OCDA: ngé ra so sinh ngé ra Mateh A cita BG dinh thi/BG dém 0. Chin nay efing 1a ngo ra khi b@ dinh thi 6 ché dé PWM. PCINT11: nguén ngit Pin Change 11. (Gea Think 19 Ly Chaos 2 5 Mon Bien Te BEB IPHICM 6- PB2: AINOANT2/PCINT10 AINO: nga vae duong cita bé so sénh tuong tr (analog comparator). INT2: ngit ngoai 2. PCINT10: nguén ngét Pin Change 10. + PBL: TUCLKO/PCINTS T1: ng@ vao bé dém cita B6 dinh thé dém 1. CLKO: ngé ra tir b6 chia xung nhip. PCINT9: nguén ngét Pin Change 9. + PBO: TOXCKOPCINTS TO: ngé vao bé dém cita BS dinh thi/Bé dém 0. XCKO: xung nhip bén ngoai cho USART 0 khi dung ¢ ché 46 déng 6. PCINTS: nguén ngat Pin Change 8. - Port C (PC7:PCO) Port C li port VO 8 bit 2 chiéu cé dign tro kéo len bén trong, co thé lap tinh figng cho ting bit. Khi reset cfc chan port Ia 3 trang thai. Port C cing thuc hign céc chic nang khac nhu sats Bang 2.4 Cac chute nang khae cia chin Port C Chén port] Chirc nang luan phién TOSC2 (Timer Oscilator pin 2) PCINT23 (Pin Chang Interrept 23) poe | TOSCH (Timer Ostilalonpin 1) PCINT22 (PiryChanga Interrupt 22). pes | TDIUTAGTESData input) PCINT21 (PinChahge Intemupt 20, pos | TROWTAG Test Data Ouputy EINT20 (Pin Chango Interrupt 20) TMS\JTAG Test ModaiGelect) PCINT19 (Pin Chane Irterrupt 19) poo | TOK (TAG Test clack) PCINT18 (Pin Change Interupt 18) por | SDA Gite Serial Bus Data InpulOutpt Line) PQINT17 (Pin Change Interrupt 17) poo | SCL W2-wire Serial Bus Clock Line) PCINT16 (Pin Change Interrupt 16) Por Pcs + PCT: TOSC2/PCINT23 TOSC2: chan 2 bé dao déng dinh thi, PCINT23: ngudn ngét Pin Change 23. - PC6: TOSCVPCINI22 TOSCL: chan 1 b6 dao dng dinh thi, PCINT22 nguén ngat Pin Change 22. - PCS: TDI/PCINT21 Chto Tink Me Ds Claseng? 25 Min Dign Te DHBETPHCM 7‘TDL ngé vao dif ligu kiém tra JTAG. PCINT2L: ngudn ngét Pin Change 21 - PC4; TDIPCINT20 TDO: ngs ra dit ligu kiém tra JTAG. PCINT20; ngudn ngat Pin Change 20. - PC3: TMS‘PCINT19 TMS: chon ché dé kiém tra JTAG. PCINT19: nguén ngit Pin Change 19. - PC2: TCKPCINTIS TCK: xung nhip kiém tra TAG. PCINTI8; nguon ngat Pin Change 18. - PCL: SDAPCINTI7 SDA: dutimg dif ligu trong gino tiép ndi tigp 2 diy¢f2C). PCINTI7: ngudn ngét Pin Change 17 - PCO: SCLPCINTI6 SCL; xung nhip trong giao tigp ndi tigp 2MayxT2C) PCINT16: nguén ngat Pin Changed6, - Port D (PD7:PD0) Port D A port 1/0 8 bit 2 chidu (6 dign tre kéo lén bén tFong, e6 thé Lap trinh ring cho timg bil. Khi reset cfc chin port [3 trang thai Port D cing thyre hign eff chive nang khéc Hay Sau Chan port ig 2.5 Ce chite ning khapeia chan PortD {Chircinang luan phi Po? ‘Ocak (TimeyCountéxe Output Compare Match A Output) PCINTSI (PirhGhange Interrupt 31) PDS CPt (timieyCouftert Input Capture Tigger) (C28 (TimertOGunter2 Output Compare Match B Output) PCINT30 (Pin Change Interrupt 30) PDS ,0C14 (TimeriCountert Output Compare Match A Output) PGINT29 (Pin Change Interrupt 20) Da (OCB (Tamer/Countert Output Compare Match B Output) XCK1 (USART! Extornal Clock Input/Output) PCINT28 (Pin Change Interrupt 28) PDS INT# (External Interrupt? Input) ‘TXD1 (USAT! Transmit Pin) PCINT27 (Pin Change Interrupt 27) Po INTO (External Interrupt0 input) XD! (USART1 Rocaive Pin) PCINT26 (Pin Change Interrupt 26) Pot ‘TXDO (USARTO Transmit Pin) PCINT25 (Pin Change Interrupt 25) PDO XDO (USARTO Rocaive Pin) PCINT26 (Pin Change Interrupt 24) Bbo Trinh Meg Ohasong 2 BB Moy Digu Te BABKDPUC- PDT: OC2A/PCINT31 OC2A: ngd ra so Sanh ngd ra Match A eta BO dinh thi/B6 dém 2. Chin nay cfing 1a ng® ra khi bé dinh thi & ché 4 PWM. PCINTS31: nguén ngit Pin Change 31 ~ PDG: ICP1/OC2B/PCINT3O ICP1: chan input capture cia BO dinh thoi/B6 dém 1 OC2B: ngd ra so sinh ngd ra Match B cia BO dinh thi/B6 dim 2. Chin nay ciing 1a ng@ ra khi bd dinh thi ché 45 PWM.. PCINT30: nguén ngit Pin Change 30. ~ PDS: OCLA/PCINT29 OCIA: ngé ra so sinh ngé ra Match A cla B6 dinh thi/B6 dém 1. Chin nay efing 1 ng6 ra khi b§ dinh thi & ché dj PWM. PCINT29: nguén ngit Pin Change 29. - PD4: OCIB/XCKI/PCINT28 OCIB: ngd ra so sinh ngd ra Match B cha BO*Ginh thYBS déml. Chi nay cing 1a ng ra khi bé dinh thi & ché dg PWM. XCK1: xung nhip bén ngoai cho USART | khidithg 6 ché, do dong bé. PCINT28: nguén ngat Pin Change 28. ~ PDS: INT1I/TXD1/PCINT27 INT1: ngiit ngoai 1 TXDA1: ngé ra phat dit ligucta USART 1 PCINT27: nguén ngit Pin Chiatige 27, = PD2: INTORXDUPEINT26 INTO: ngit ngdai0. TXDI1: ng6 vio thu dit ligu cta USART 1. PCINT26%ugudn ngit PiCharige 26. - PD1: TXDO/PCINT25 ‘TXDO: ng@ ra phit dtediGu tia USART 0. PCINT25: ngudn ngit Pin Change 25. ~ PDI: RXDOMPCINT24 RXDO: ng6 vao thu dit ligu cua USART 0. PCINT24: nguén ngit Pin Change 24. Cfiu héi 6n tip 1. Cho biét dung lngng cde bé nhé trong etia ATmega324P. 2. Lidt ké 3 thanh phan ngoai vi cé trong ATmega324P. 3. Chan port nio Li ng® vao eta cae b6 Timer? Port nio li 8 kénh vio ciia bp ADC? Cho biét cde phurong thite giao tigp néi tiép cla ATmega324P. Chan port nado tong tmg véi ngd vao ede ngit ngoai INTO, INT1 va INT2? ane Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM °2.3 LOLCPU(CPU CORE) Chite nang chinh cia CEU 1A dam bao viée thuc thi ding chwong triah. CPU pha cé kha ning truy xvat cdc b3 abd, thve hin cdc phép todn, diéu Khién cde ngoai vi vaxil¥ che ngét Data Bus 8-bit Program Status Fish |__| Ke Pope Counter and Control Memory |«——— Intertupt I af S2x8 Unit Tnstructon General Register Purpose Spr 1 Regisirers Ogt Tnstructon Watchdog Decoder al ‘mee | 1 \@ = Contral Lines 3 2 Comparator = z 3 £ a = = HO Modulet any HO Module 2 +L PD spam VO Module n EEPROM VO Lines Hinh 2.3 So dd kchdi cd tric AVR ~ Thanh ghi quléa trong nbét trong 1éi AVR 1a thanh ghi PC— Program Counter (66 dém chwong trinh). BS dém chuong tinh dwec CPU sir dung dé trd dén dia chi cia lénh tiép theo 68 duce thuc thi. Khi CDU lay mi lénk tir ROM chweng tainh, 6 dém cheng trink sé ny déng tang 18n dé trd dén léah tiép theo. Trong vi diéu khifn AVR, mi vi tr b§ nhé Flash cé chiéu réng 1a 2 byte, AT mega324P cé Flash ROMA 32K byte. Flash diroc t8 chite 1a timg world2 byte, 32K x 8= 16K x 16, Nhu vay b6 dém chwong trinh cé 14 bit (24 = 16K vi tri b3 nhd). Khi reset hay cp nguin hoat déng, gidtri déu cha PC = 0000, do way iGnh dau tién thyc hign1aléah chitatai vi tri 00000 cha Flash - Cac léah trong 68 ahd chong trinh duoc thue thi v6: kj thuat dung dng dom cp Trong khi 1 1énh dang duoc thie thi (execute), thi 1énh ké tiép dior lay ma Getch) tnrds tir b8 nhé chwong tink, Khai aiém aay cho phép céc lénh dos thuc thi trong Gio Trinh TELS Cawemg 2 28 Mba Ein THDERETPHCM 10méi chu ky xung hip. Bé nhé chuong trinh Ja Flash Rom co thé tai l4p trinh agay trong héthéng ma khong cin phai thao chip ra khdi hé théng. Non-pipetine 7 Pipeline | | i | i i i i Hinh 2.4 X¥ thuit during éng (pip eline) va khong durong éng (non-pipline) - Tap thanh ghi truy auét mhanh g6m 32 thanh ghi dé dig 8 bit (GPRS Oehteral Purpose Registers) v5i thé gian tray svat 1 chu lay mung’Viée nay nay chophép ALU thre hign phép ton irén 2 toar hang tirtip thanh ghi wa lt qud ct Iai ve.t€p thanh ghi chi trong 1 chu ky sung mhip. Cé 6 thanh ghi troag t@p, thant ghi coth® diinginh 12 3 thanh ghi 16 bit X, Y va Z (sé duoc mé tA trong. phiaft’sau). + BO ALUTHB tree phép ton s6 hoe waJogic gida dhe Baath ghihay gitra thank ghi va hing s8. Céc phep ton alia ALU/éuce chia think bahhSm chinh: phép ican 56 heo, phép toda logiova mir ly. bik ALU cung ofp Ingt b3 Fin menh AB tro phép nin o} déu khing diva inh dang ps4 San bRatlvte hign phép tran shoo, 1 thenh ghi trang thai sé cap nhat thong, snk 8 qui cla prep tan General Purpose wast ~ ee ALU Hinh 2.5 ALU va tip thanh ghi = Khéng gian bé nho Flash chuong trinh chia thanh 2phan: chuong trinh khoi déng hoot program) v4 chong trinh ung dang (aplication program) Gio Trin B Sely Chaweng 2 BS Mn Eig Te DUBETPECM rr- KEhi ngét hay goi chuong trinh con, néi dung thanh ghi PC dye cét vac ngéia xép (stack). Ngan xép doc phan 64 higu qua troag ving dif ligu SRAM, do dé kich thyéc ngén xép chi bi giéi hen béi kich thiréc SRAM va cach ding SRAM. Tét c& cdc chong trink mg dung phai khdi tzo SPtrong phan khdi dong (treée khi cae chwong trink con hay ngit duoc thye thi) + Khéng gian bé nhé 1/0 gém 64+ 160 éiachi cho céc chite nang diéu khién CPU hay ngoai vi ahw céc thanh ghi trang thai, thanh ghi diéu khién SEI va cée chtio ning YO khae 2.4 BONHO AVR Bonhs AVR cé 2khOng gian b6 nhd 1A b6 nhd dif Liéa va b6 nhd chwong trinh, 2.4.1 BG nhé chuong trinh Flash ATmega324P c6 32KB b6 ahé Flash dé lam bonhé thwongtriah. Tat call@nh AVR cd di} dai 1a 16bit hay 32 bit BA nhéFlash dior t8 chite thy! EIA 16 bit Byte) B6 ohé Hash 32KB = 16K x 2B. do vay S&cd02) vi tri, Ta 86 dia chi ti: 00000 - 0235 FF, BG nhé chuong trinh Flash chita 2 fhm dung (Application) wa khdi déng Boot), Rich thudc mdi ving oé thé thy chon. BS ahSBlesh cting chad Ligu nhw bang hing 93 Bé ahd Flach 06 th’ chin doe 16,000 chu.de} ghilgéa. Viée nap chwong trink vao bd nhé Flash cé thé dugc lap trinhsobgsong hodcndi Pep qua giao tidp JTAG hay SPL 90000 Applieation Flash Section Boot Flash Section OSFFF Hinh 2.6 Bin 43 b@ nko chong tink Gio Trinh TELS Cawemg 2 28 Mba Ein THDERETPHCM 122.4.2 BO nhé divligu SRAM BG nhé dit ligu gdm 32 thanh ghi lam vige da dung, 64thanh ghi VO, 160 thanh ghi 0 m6 réng va 2KB SRAM néi. Dia chi b§ nho SRAM cia ATmega324P tir 0x0000 dén OxO8FF. Data Memory 32 Registers 0x0000 - 0x001F 64 I/O Registers 0x0020 - 0x005F 160 Ext 1/0 Reg. 0x0060 - Ox00FF 0x0100 Internal SRAM (2048 x 8) Ox08FF Hinh 2.7 Ban dé b6 nhé dit ligu ofla ATmeg324P 2.4.2.1 Tap thanh ghi da dyng (GPRs:General Purpose Registers) CPU str dung cae thanh ghi 8 bit nay dé chifa, dt ligu tam théiding trong cdc phép todn sé hoe va logic. Céc thanh ghi nay 1a RO d8n°R31 6 digehibOnhs tuomg img 0x00 dén OxIF cho tit ca ho AVR. Tap thanh ghi@uge"@hid than 2 phn, méi phan ¢6 16 thanh ghi: RO + R15 va R16 + R31. Adar. General Purpose Registers Ox1A X-register Low Byte oxi8 X-ragistar High Byte oxic Y-register Low Byte od Y-ragistar High Byte OxIE Zeregister Low Byte OxtF register High Byte Hinh 2.8 Tp thanh ghi da dung(GPRs) ‘Trong tp Ignh AVR quy dinh 6 1 s6 Inh chi duge str dung thanh ghi R16+R31 nhur LDL Vi dy 2.2 Céc lénh sit dung thanh ghi da dung LDI R16, 0x25 map gid tri 25H vao thanh ghi R16 Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM BLDI R17, 125 ADD R10, R16 nap gid tr] 125 vio thanh ghi R17 ; cOng gid trj trong thanh ghi R10 va R16, ket qua chita lai vio thanh ghi R10 INC R4 ;ling néi dung R4 thém 1 OUT PORTB,R20 ;xuat ni dung R20 ra PortB Cé 1 sé thanh ghi cé c6 chire ning bé sung rigng.Vi du nhw két qua phép nhan 2 sé nhi phan 8 bit la s6 nhi phan 16 bit mac dinh tra v8 RI:RO (R1 byte cao, RO byte thap) C6 6 thanh ghi R26 dén R31 duoe ghép thinh 3 thanh ghi 16 bit la thanh ghi X. Y va Z. Cée thanh ghi nay la con tré thanh ghi dia chi gidn tigp diing d3 truy xudt bO nhé dir ligu. woe Eo OF Hinh 2.9 Cic thanh ghi X,Y, Z 2.4.2.2 BO nhé 10 (VO Meinory) B6 nh 1/0 1a céc\thanighi 8 bit cO“Wia chi bé nhé tir 0x20 dén OxFF. Cac thanh ghi /O nay 6 chite ning riépgWe digu khién vidietfkhién hay ngoai vi. Ta sé xem xét chite ning cy thé ota | sé thanh ghi trong mpc 2.5. BG nhé 1/0 chia lam 2 phan: thanh ghi VO chuan (Standard /O registers) va thanh ghi 1/0 mé rong. = Thanh ghi 1/O chyahtagém 64 thanh ghi co dia chi b6 nhe tir 0x20 — OxSF. Cac thanh ghi nay ngodihdia chi b9 nhé con c6 dia chi VO tir 0x00 ~ Ox3F (chénh Igch 020 s v6i dia chi bé niétuong tmg). Dia chi nay ding khi sir dung eae nh IN, OUT dé lam: vige véi thank ghi. Ngoai ra cae thanh ghi I/O 6 dia chi 1/0 tir 0x00 — OxIF e6 thé truy suit bit true tiép trong eae Iénh sit ly bit nh CBI, SBI, SBIS, SBIC. = Thanh ghi VO mé rong: gdm 160 thanh ghi e6 dia chi b6 nhé tir 0X60 — OxFF. Dé truy xuit eae thanh ghi /O m@ rong phai ding ee Ignh ST/LD nur truy xuat true tigp dia chi true SRAM. Néi chung, cic thanh ghi I/O 6 thé trao d6i dit ligu véi tip thanh ghi lim vige da dung bing cae 1énh LD/LDS/LDD va ST/STS/STD. Khi dé ding dia chi bé nhé khi truy xuat thanh ghi VO. Trong chuong 3 sé trinh bay chi tiét van dé nay. Trong ving bd nhé /O cdn c6 mot sé dia chi danh riéng (reserved) dé tuong thich véi cdc thiét bj phat trién trong trong lai. Gio Trinh VIX LS Chuomg 2 26 Men Dign Ti DHBKTPHCM “Dja chi Ten Ten Dja chi Ten BO nhs | VO | Thanh ghi Thanh ghi| |Bonhs | VO | Thanh ghi 0520_| 000 | PINA MCUSR O83, Reserved 0x21 [0x01 | DDRA MCUCR x84 TCNTIL va 0x22 [0x02 | PORTA, Reserved Os85 TCNTIH (0x25 [0s03_[ PINB) SPMCSR_| [086 TCRIL va (0x24 [0x04 | DDRB. Ox87 ICRIH 0325 [0x05 | PORTB Reserved 588 OCRIAL va 0326 [0x06 | PINC OxSA 0x89 OCRIAH 0x27 0x07 | DDRC 0xsB_| 0x38 |_RAMPZ Ox8A ‘OCRIBL va 0x28 [0x08 | PORTC OxSC Reserved Ox8B OCRIBH, (0x29 [0x09 | PIND 0 OxB7 Reserved Ox3A 0x68 PCICR OxBS TWBR 0x38 | Ox1B | PCIFR 0x69 EICRA’ xB9 TWSR 0x3C_[OxIC [EIR Ox6A Reserved | OxBA TWAR 0x3D_[Ox1D | EIMSK Ox6B PCMSKO_|*|0xBB TWDR Os3E | OxIE | GPIORO Ox6C PeMskT | [“0sBC TWCR OxIF | EECR 0x60" PEMSK2_| [“OxBD TWAMR 020 | EEDR. Os6E TIMSKO_| [70xBE Reserved Osi [0521 | ERARL va OXOF TTIMSK1 OxBF Reserved Oxd2_[0x22 | BEAR TIMSK2 OxCO TICSROA 0x43 [0523 |" GTGGR. 6 Reserved OxCI UCSROB oxdd [0x24 | TECROA Reserved OxC2 UCSROC 0x45 [0x25 | TCCROB OxTS PCMSK3_| [“0xC3. Reserved (0x46 | 0x26 | TCNTO OxT4T OxCa) UBRROL va 0x47 [0x27 | OGROA Reserved OxC5 UBRROH Os48 [0x28 | OCROB x77 OsC6 UDRO Oxd9) Reserv x78 ADCL va | [Toxc7 Reserved ‘xt _[Ox2A | GRIORT 0x79 ADCH OxCR UCSRIA 0x48 | 0s28 | GPIOR? Ox7A ADCSRA_| [“0xco ‘UCSRIB OxdC SPCRO Ox7B ADCSRB_| [OxCa UCSRIC ‘Ox4D SPSRO Ox7C ‘ADMUX OxCB Reserved OsdE SPDRO 0<7D. Reserved OxCC UBRRIL va OxaF | Ox2F | Reserved OxTE DIDRO OxCD. UBRRIH 0s50_[ 0x30 | ACSR OxTF DIDRI OxCE UDRI 0x51 0x31 | OCDR. 0x80 TCCRIA_| [~OxcF 0s52__| 0x32. | Reserved Ox81 TCCRIB ae Reserved 0x53 [0x33 | SMCR. Ox82 TCCRIC OxFF Hinh 2.10 Céc thanh ghi /O Xem thém phy Ive t6m tit ede thanh ghi trong b§ nhé /O eda AVR ATmega324P. Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM2.4.2.3 SRAM nd ATmega324P cé 2KB Ram nGi c6 dia chi tir 00100 —Ox08FF. Ving nhé nay cé thé duge truy xual truc tiép hofe gidn tiép. BO nhd nay cing dege ding 1am ngin xép Khi ding chuong trinh con hay chong trinh ngjt 2.4.3 BG nhé dé Iigu EEPROM ATmega324P cé IKB 6 nhé di ligu EEPROM 6 dia chi tir 0x0000 - Ox03EF. EEPROM chiu duge it nhat 100,000 chu ky ghi/xéa, BO nho EEPROM duge sit dung dé lu ttt dit figu ft Khi bj thay adi va khéng bj mét khi tit ngudn, bé truy svat ving nhé nay, st dung céc thanh ghi chiic ning trong viing bé nhé YO (irinh bay trong myc 2.5.4), Bénho nao cia ATmeg324P c6 16 chute li 8 bit? 16 bit? Bénhd SRAM cé ting céng bao nhign Byte? (néu tinh Iuén tip thanh ghi va thanh ghi 1/0) ‘Tap thanh ghi lim vige da dang GPR cé dia chi b6 nhé 1a bao nhiéu? Thanh ghi R23 66 dja chi bd nh6 18 bao nhigu? Che thanh shi 16 bit X, ¥,Z croc ghép tir cfc thantgtinnao® Lim cach nao dé tim dia chi bé nhe tir dia chi VO,clia 1 thanh ghi WO, Che lénh IN/OUT chi duge ding trén cfc thanh ghi HO Yio? (néu dia chiB6 nhé, da chiT/0) Céc thanh ghi VO nao c6 truy xuat bit? (néu dia Chitbé nhé,diachil'O)? ‘Neu tén 3 thanh ghi 1/0 c6 dia chi/O va ghanh'ghi khong cd dia chi VO. chi cudi cia ving SRAM 18 bao nhigue 2.5 CHUC NANG THANH GHIVO Phin niy sé khio sit mét 86 fi phi ViCithéhg thu dng. Cc thanh ghi Khic sé duoe dé cap trong cdc chuong tiép theo. 2.8.1 Thanh ghi trang thai —SREG (staitisRéuister} ‘Thanh ghiftratig thai chita théng fin vé ket qua cua lénh s6 hoc/logic hodc diéu kién duge thuc hign gln.nhét. Théng Yin‘niyrchi bao trang thai két qua hove duge ding lam thay d6i huéng chay chuéng trin de thie hién cae phép tofn diéu kign. Céc bit trong thanh shi SREG thuong digc g9i lavcdc ey bao trang thai. Vige cAp nhat cae ci nay theo sau timg len 8€ duge trinh biy chi tiétrotgéhuong 3. st z : : ‘ 3 2 1‘ ° A peaainne TR imavaus ° 0 ° ° 0 ° ° Hinh 2.11: Té chite thanh ghi SREG * Bit 7 — 1: Cho phép ngat toan cuc (Global Interrupt Enable) Bit I bing 1 d8 cho phép chong trinh c6 sit dung cfc ngit va bing 0 thi cfm sit dung cic ngit, Méi ngudn ngit Igi dugc diéu khién riéng (dé cap chi tiét trong chong, 10). Bit Tsé bi x6a vé 0 bang phin cing khi chuong trinh ngét thuc hign va sé dat len 1 khi thuc hign 1énh RETI d8 cho phép céc ngat tiép theo. Bit T cling duoc dft lén 1 bing 1énh SET va xéa vé 0 bang lénh CLI. * Bit 6 — 1: bit sao chép (Copy Storage) (Calo Trich VM 29 Checoreg 2 Bb Min Bide Tie DHBETPHOM 16Cae Ignh sao chép bit sit dung bit T dé chita gid tri. Lénh BLD (Bit Load) cho phép sao chép bit T vio 1 bit bit ky trong 1 thanh ghi thude tap thanh ghi GPRs, Lénh BST (Bit Store) cho phép sao chép 1 bit bat ky trong 1 thanh ghi thudc tap thanh ghi GPRS vio bit T © Bit 3H: Co nhé phan nita (Half Carry Flag) Co H la cd nhé phan nia trong cde phép toan sé hoe. Co H=1 khi e6 trin tir bit 3 sang bit 4. Thuong ding khi ding phép ton sé hoc trén s6 BCD. © Bit 4—S: Ca dau (Sign Flag) Ca 8 bio dau chinh xae ciia két qua, C6 thé xem $ = N@Y (xem phan sau) 0 bio két qua durong, S=1 bao két qua am. Bit 3 — V : Ci tran ba 2 (Two's Complement Overflow Flag) Ca V=1 khi két qua cia 1 phép toan sé c6 dau In hon pham vi biéu dign ciia nd goi la tran sé c6 dau dang bi 2. Hay néi cach khac, c& V=Lkhi mét trong haistrudng hop sau xy ra (xem cd C phan sau): qua e6 tran tir bit 6 qua bit 7, nhumg’khoyg cB tran irbit (C40) t quai o6 tran tt bit 7 (C=1), nhumg khong e6 tran wr bir qua bit 7 Nhu vay néu két qua ding thoi cd wan tir bit 6 qua bit va tah tir bit 7 (C=1) thi co V0. © Bit 2—N : Ci am (Negative Flag) CaN cho biét két qua am trong phép toan sé hoc. CG N66 gia tri nhur bit 7 cua két qua CaN = 0 thi két qua 18 s6dutong, N= 1 thi kbgua 12's am # Bit 1 Z: Co khong (ZetOF lag) Co Z cho biét két quinbiing 0 trong, cée'phép toan sé hoe va logic. Két qua bing 0 thi co Z = 1, nguge Jai R&t qua khac 0 thiZz™0. # Bit 0—C : Coxahie (Carry Flag) Co C la bit nh tir bit 7 Ri the hign phép toan cng hay trit, Coy C=1 khi két qua tran tir bit 7 sang. Vi dy 2.3 Xéc dinlingi dung ctia SREG sau khi thy hign xong doan chuong trinh LDI R2050x54 LDI R25, 0x4 ADD R20, R25 Vi tri bit Bit nh Pooorood S@ co dau R20 TLdL 01 oo 84 R25 1Tioooldd -60 R20 <— R20+R25 oootrldédda +24 |. co H=0, vad N=0. Thue hign phép cng 2 s6, ta c6 cat C a i oF V=0. Xet s6 06 du thi két qua khong bj tri Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM nvDo dé cd $= 0 (S = N@Y) 2.5.2 Con tré ngin xép — SP (Stack Pointer) Nain xép la 1 phan bd nhé thurong la RAM, durge sir dung dé chtta dit ligu tam thoi, Nagin xép thing duroe ding khi e6 chuong trinh ngit va khi goi chong trinh con, Ngoai ra con durge sir dung khi ding Ignh PUSH va POP. ‘Thanh ghi SP udn tro dén dinh ngan x Top Of Stack). Noi dung thanh ghi SP chita dia chi cla 6 nhé dang la dinh ngin xép. Khi c6 Ignh PUSH dit lig sé duge diy ngiin xép lic d6 dinh ngan xép tng; vGi AVR thi dong nghia véi viée lam giam ngi dung con tro SP. Khi cé lgnh POP thi dir liga duge lay ra khoi ngan xp va dinh ngin_xép giam xuéng; dong nghia véi vige ting n6i dung con tré SP, Luu ¥ ring AVR ngin xépGuotthue hign tir dia chi cao dén dia chi thdp hon. "ao Ngan xép 6 cau trac LIFO — Last In First Out DWligu dua vao Sait cling sé nim dinh ngin xép, do dé khi duge lay ra thi dir ligu d6.séditee lay ra ted, GO AVR, thanh ghi SP la 2 thanh ghit§,bit SPH (StackPéinter High) va SPL (Stack Pointer Low) két hgp lai. SPH va SPL thyéc ving thanhghf PO. er 6 “4 ‘3 2 fj 10 ° 8 Or (OnE) WE fi SPIO oe _ org0 so) _sr7_ | shoe Fars | sry [srs | sre | ort sro 7m > = z 7 7 Reaawite R a a a Rw RW RWW WA Bw ok hw wR RW Inia Vaive ° ° ° ° 1 ° ° ° 1 1 1 1 1 1 1 Hinh2,12:-76 chite thanh ghi SP ATmega324P Sngin xép trong viing SRAM 2KB, c6 dia chi tir 0x0100 dén OxOSPF. Do dé thanh ghi SR,chivding 12 bit: SP11.. SPO dé chita dia chi dinh ngan xép. ‘trd bai ndi dung SP Chit ¥ la ngain xép ctia AVR Khi cét dtr ligu vao (lénh PUSH) 6 nho dia chi dung SP xong, ndi dung SP sé gidm . Cdn khi léy dot ligu te ngin xép (Iénh POP), tang 1 rdi mdi Lay dit ligu tir 6 nhé dia chi tro boi SP. Ving ngan xép phai durge xac dinh trong chuong trinh truée khi goi chong trinh con hay ngit direc cho phép. Véi ATmega324P sau khi reset, gid tri diu ca thanh ghi SP 1a OxO8FF, biing dia chi cao nhat cua ving SRAM, nén khéng can khéi d6ng lai ving ngiin xép. Vi du 2.4 Voi néi dung céc thanh ghi SP = Ox08FF, R20 =0x2A. R21 = 0x95, R22 = OxdC. Cho biét ni dung ngin xép va ede thanh ghi sau khi thue hign tuan ty cde lenh. Ngan xép LENT Ngan xép ‘Thanh ghi Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM Istruge khi thye hign enh sau khi thye hign Iénh 8FD PUSH R20 | &FD R20=$2A. SFE SFE «sp | R21=$95 8FF Chi ¥: trong ho AVR c6 mot sé MCU satitkhi/teset thaith ghi,SP = 0x0000. Do vay khi sir dung ving ngin xép dé thye hign chuong trinh con hay Healy can chuyén SP toi dja chi cao nhit ca ving SRAM. Téng quaf, dé cd thé dingchun’\cho cac loai AVR c6 dung long. SRAM khée nhau, str dung doa chong trinh sau; -ORG 0 eluong trinh bait du tir dja chi 0x0000 LDI R16, HIGH(RAMEND) snap SPH gid tri byte cao ca RAMEND OUT SPH, RIG : LDI R16, LOW(RAMEND) ; nap SPL gid tri byte thip cia RAMEND OUT SPL,RI6 Ky higu RAMEND 1a dja‘ehi cui cia ving SRAM tuong durong voi mdi AVR. 2.53 Cae thanh ghi cdi xulit nh4ip (1/0 Port) - DDRx, PORTx, PINx ATmega324P c6"4 port: PortA, PortB, PortC vi PortD. Cae chin port niy 6 nhiéu chite naing rigng dé Tash vige voi ngoai vi. Néu khdng diing ede chute ning nay thi ede chin port 6 thé diing lim chan suat/nhap s6. Dé str dung cic port nay, thi can phai lap trinh chire nang cho méi chan port. Mai port 6 3 thanh ghi lién quan li DDRx, PORTS, PINK (v6i x la A, B,C, D). Chii ¥ la méi chan cui méi port c6 thé diéu khién xudt/nhap riéng le. Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM 19Pin n of Xen brome port x J L____p] PINxn Inside the AVR chip Outside the AVR chip cre ee lle re Hinh 2.13: Cau trac eo ban ehiin port xuat nhdp (The /O Port) Ky higu efe bit xn v6i x 1A tén ede port (A, B, C, D) va nla sé thi ty ebiin trong port @1..% 2.5.3.1 Thanh ghi huéng dit ligu— DDRx (Data Direction R ster) ATmega324P c6 4 Port, méi Port o6 & durongeVO lain higu 2 chigu. ‘Puy nbign tai méi thoi diém cae ding nay chi nhap Gnpud hay.xuat)(output) Do véy truse Ishi ding ching oan phai chen eau hinh la nhap hay xuat bing, thath ghi DDR. ot 0321) [CUBR BORO TT COROT CONT TSO) aesavins EW aR wmiavaxe ° 2 ce 3 of 8 3 1 o ovo ccen CEL SRT pear oa TL ELL] ne a mavens =o CNM ot ° ¢ ¢ ait 2 1 Q sor een SRE Ta TEL SLB] one Rese ATR widvaw 0 2 8 ¢ s&s Bi 2 ‘ 3 ‘ 3 2 ' ‘ 104 (28) [R57 BRE BseE Toons] Bes] Sse] aa FEHT] pon. eaitwrie RWW intervous 0 > ° ° ° ° ° ° Hinh 2.14; TS chite cae thanh ghi huéng dit ligu YO Ghi cic gia tri 1 vao thanh ghi DDR tai vj tri nao thi bit tuong ting eita chan port dé sé la chan xuat (output), nguge lai ghi gid tri 0 thi chan port sé la chan nhap (input), Gia tej ban dau cita cdc thanh chi nay 1a 0x00 nén ede port déu sin 1a chin nhép (input) Vidw 2.5: Chon chite ning suit cho Port A vi nhdp cho Port C LPI R16,0xFF —; R16 =OxFF=Ob11111111 OUT DDRA, R16 ; Port A duge chon la xuat LDI R16,0x00 —; R16 =0x00 = 000000000 OUT DDRC, R16; Port C duge chon la nhap Gedo Trinh ¥ Mey Ctaaome 2 BS Min Bien Tie DEDKTPHCM a2.5.3.2 Thanh ghi dit liga Port — PORT (Data Register) Khi cde chan port duge chon 1a xudt (output).viée ghi 1 gid tri vao thanh ghi PORT thi gid tri do sé See ‘xuat ra chan port trong ting. ai ‘ 5 4 3 1 S202) ALR LL RAAT] ron poatwite ER imal vee 0 ° 0 ° ° ° ° ° 305 25) [Ferrer | Fontes | Fonres| ponte | pores | pores Forme | Pome] Ports eadWite imalvae 0 oo ° ° 0 ° 8 7 ° 5 ‘ 3 2 : ° vos ox) [FORTE | Forres | Ponce] Ponrer | Pones | Ponrez | Pont | Fone] Rena IntelVobe 0 ° ° ° ° 0 ° a z ° 5 ‘ 3 2 4 ° 103 x28) [FORTET | PORTIS] FORTEE | PORTOR | PORTER] PORTE? [PORTUL[-PORTOD] PORTO oadtwitg EE BRT intalveue 0 ° 0 9 9 ° Hinh 2.15: Té chive cdc thank ghiPort /Q, Vi dy 2.6: Xut gid tr] $55 ra port B LDI R16, 0xFF |: R1G=OxFF=ObILIIITIL OUT DDRB. R16 \; PoifB duoc thon 1dxnét LDI R16, 0x85); R16 = Ox55%,0601010101 OUT PORTB, RIG; gid tri $55 diye suat raPort B 2.5.3.3 Thanh ghf cae\chiin nhap Port ~PINx (Port Input Pins Register) Khi cde Ghin port dirgc chin knhip (input, thi vige doc ngi dung thanh ghi PIN sé cb duge gid tri nhap vé tir Cae chanl'port trong img. at 7_4\ so a2 ° 100 (0:20) RR PA pecawto RW = aT immalvaue = WRN ONA WANA OA WRN ot 2 6 ss : 0 seit Ceeer[rme oeee eve [sree] ete eee] Oi eae oT Tr Intl Vaue = «NACA NANA ONAN OWN at ‘ 0x08 028) Cae ae me er er er ee] pwc reaaite a intl Vue = «WANA CNA NA NANA NAA ac Tin VA Nie sp cng 2 BB Ain fig Te OHBSCTPHSCNS a2 2 ‘ ss 3 2 1 ° x02 020) [FARO PROT] [PROS FRO FRO] FROT] eno ease ER iotaVaue «WANA KONA NANA ONAN Himh 2.16: T6 chite ede thanh ghi Pin 70 ‘Vi dy 2.7: Nhap dit liéu 8 bit tir port C va xudt ra port D LDI R16,0x00 — ; R16 = OxFF = 000000000 OUT DDRC, R16 ; Port C duge chon li nhfp LDI R16,0sFF — ; R16=OxPF=Ob11N11111 OUT DDRD, R16 ; Port D duge chon la xudt IN R16,PINC _ ; nhap dit ligu tir Port C va cat vao thanh ghi R16 OUT PORTD, R16 ; xuét gid tri m Port D Cée chan port cha AVR déu c6 dién tré kéo lén. Viée sti dung diénird kéo lén dam bao cate ngé vao dn dinh tgi mic logic mong yi néu caé tht bj ben ngodi khong c6 két ndi hay 6 trang thaitré khang cao, Dé si dung céc dién t¥6 nly thi'ghi cde"gia tei L440 thanh ghi Portx tong tng, Néu ghi gidtrj 0 thi khong cho phép.st dung cde Giga 16 kéo len. vi ‘A= Close 1 1 1 i i pen i 1 ‘ Hi 1 pinot ‘port x PINKN J Buisideshe Dh, “side the ‘AVR chip” 1° AVR chip Tinh 2.17: Bign trékéo lén (The Pull-up Resistor) ‘Vidy 2.9 Tuong\ty nit vi du 2.7, nhumg 6 cho phép Port C 6 dién tré-kéo len LDI Ri. 0x00 ; R16 = OxFF = 0b00000000 OUT DDRC, R16 ; Port C drge chon Kinhip LDL R16,0xFF =; R16 =OxPF = 0b11111111 OUT PORTC, R16 ; cho st dung dign tré‘kéo lén 6 Port C OUT DDRD, R16 ; Port D duge chon ki xudt IN R16, PINC _ ; nhap da liu ti Port C va cét vao thanh ghi R16 OUT PORTD, R16 ; xuéi gid tri ra Port D Chi ¥ 1a trong thanh ghi MCUCR (MCU Control Register) c6 bit PUD (Pull-up Disable) 06 thé cim st dung ign tr kéo len cho ti c& cdc chén port. Khi ghi gia tri 1 vao bit PUD, thi dién tré‘kéo lén bi cm ding cho dit cé DDxn = 0 va PORTxn = 1. Gio Erin Vt Lp nor 2 Bb Men Din Te DEBKEPHCM. 2ex z 8 5 a 3 2 1 ° 149 095) [a0] 00s sous [0 set ice] cue Reaawite RW 7 7 7a 7 a tnuatvaue 0 0 ° a ° ° ° ° Hinh 2.18: Thanh ghi MCUCR 6 bit PUD cho phép/céim dién tré kéo lén Port Bang 2.6 tom tét cdc tin higu diéu khién & chén port. Bang 2.6: Cac cau hinh chan port. DDsn | PORT | PUD TO | digas Chin port (@IcUCR) Pull-up 0 0 x Nhép | Khéng [3 trang thai Tristate (Hi-Z) (input) 0 1 0 ‘Nha Co ‘Pxn sé kéo lén nguéa néu ben (Input) ngoai kéo xuéng thip 0 T T Nhip | Rhong [3 trang thar Tristate (Hi-Z) (input) 1 0 = ‘Xuat Khong Neo ra mic thap (Output Low) (Output) cl 1 x Xuat ‘Khong \ Ng ra meOcao (Output High) (Output) 2.8.4 Cécthanh ghi EEPROM ATmega324P ¢6 IKB EEPROM. CPU ding 3 thaih ghi dé truy xudt ving oho nay os ws ye axe oo ss owe) [— a ova on) [EERIE [Senos] commen cea | fone _[ eens [cram [crane] ccan >~

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° 5 4 3 2 : ° 20 880) eer ReadWite RR tia Value ° ° ° ° ° ° ° ° (b) Thanh ghi EEDR ot a a a ee i oxo) (Teer eee [ene ere [eer] econ a a imavee = «0 KK (©) Thanh ghiEECR Gio Erin Vt Lp nor 2 Bb Men Din Te DEBKEPHCM. FeHinh 2.19: T6 chite cdc thanh ghi truy xuét EEPROM 2.5.4.1 Thanh ghi dja chi EEPROM ~ EEARH_EEARL (EEPROM Address Register) Cap thanh ghi EEARH_EEARL la thanh ghi EEAR 16 bit ding dé chira dia chi ciia ‘ving nhé can truy suit. Do EEPROM eta ATmega324P chi c6 IKB, vi vay chi ding 10 bit dia chi, Trurée khi ghi/doe EEPROM thi can ghi dia chi ctia 6 nhé vao thanh ghi EEAR. 2.5.4.2 Thanh ghi dit ligu EEPROM ~ EEDR (EEPROM Data Register) “Dé ghi EEPROM thi dit ligu duge ghi vao thanh ghi EEDR. Dé doc EEPROM thi doe thanh ghi EEDR. 2.5.4.3 Thanh ghi diéu khién EEPROM — EECR (EEPROM Control Register) © Bit 5,4 EEPM1:EEPMO : Cac bit chon kigu lap trinh (EEPROM Program Mode) ‘Vige lap trinh la 1 hoat dong gom vige x6a va ghi bé nho. Tuy nhién c6 the tach thanh 2 hoat dong riéng Ié. Cac bit EEPM ding dé chon hoat dgfig nhur bing 2.7.x6i Fose-8Mhz. Bang 2.7: Cac bit chon ché 9 lip trinh EEPM[1:0] | Thoi gian lap trinh Hoat dong, @rogramming Time) 00 3.4ms 3a Va BHI trong elmBy Host dong on 1.8ms Chi a 10 1.8ms Chih 1 : Du tir cho tig dung twrong lai Bit 3 — EERIE : Cho pliép fgat EEPROM (EEPROM Ready Interrupt Enable) Ghi 1 vao bit EERIE 8&Chd)phép ngitREPROM hoat dong. Ghi 0 18 cdm sir dung ngit EEPROM (xemchuong V6). « Bit 2— EEMPE 3Cho phép ghithw)EEPROM (EEPROM Master Write Enable) Khi bit EEMPEy4uroe dat len\l, thi vige dat bit EEPE lén 1 trong vong bén chu ky xung nhip tiép theo sé thye hign, vige ghi dot ligu vio EEPROM 6 vi tri da chon. Néu EEMPE 1a 0, thi vige dit BEPR,khging e6 téc dung. Khi ghi 1 vio EEMPE, phan cimg sé x6a bit nay vé 0 sau bon chii\ky xung nhip. * Bit 1 KEP; Gho phép ghi EEPROM (EEPROM Write Enable) Bit EEPE li tin higu digu khién vige ghi EEPROM. Khi dia chi va dit ligu duge thiét Lap ding, bit EEPE ghi thanh 1 dé cho phép ghi gid tri vo EEPROM. Bit EEMPE phai duge ghi 1 true khi EEPE dirge ghi 1; néu khéng, khdng ¢6 qué trinh ghi EEPROM nio digi a. Phan cimg sé xa bit EEPE sau khi khi xong dit ligu vao 6 nho da nh. Khi dat . CPU bj treo 2 chu ky xung nhip trudc khi thue hign lénb ké tiép. Dé ghi EEPROM, can theo cdc burde sau ‘Cho dén khi bit EEPE=0. Ghi dia chi EEPROM vio thanh ghi EEAR. Ghi dir ligu vao thanh ghi EEDR. Dit bit EEMPE= 1. ‘Trong vong 4 chu ky sung n we sau khi dat bit EEMPE=I thi dat bit EEPE =L Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM 2Cho ¥ 18.6 bude 5, phai dt bit EEPE=1 trong vong 4 chu kj xung nhip sau buée 4. Béi vi sm thoi gian do phan cing xa bit HEMPE =0, viée dat bit EEPE =1 cung khong thé ghi duge EEPROM, * Bit 0 — EERE : Cho phép doc EEPROM (EEPROM Read Enable) Bit FFRE latin higu dién khién viée doe EEPROM. Khi dia chi durge thiét lap, viée dat bit EERE =1 trong khi bit EEPE =0 sé bfit du hoat déng doc EEPROM . N6i dung aia @nhé EEPROM sé duge duavao thanh ghi EEDR. Khi EEPROM dugc dgc thi CPU bi treo 4 chu ky sung nhip truéc khi thuc hign lenh tiép theo. Be doc EEPROM, cin theo céic bude sau: 1. Cho dén khi bit FEPM =0. 2. Ghi djachi EEPROM vao thanh ghi EEAR. 3. Dat bit EERE=1. 4. Boe dit lisu FEPROM trong thanh ghi FEDR. 2.5.5 Cac thank ghi I/O da dyng (General Purpose 1/0 Registirs) Cée thanh ghi nay duoc ding dé chia bét ky thétig tin nao, dac\biét hivu ich dé chia ce bién tozn cuc va cde cd trang thai, C6 3 thanhShiL/O da dang: - Thanh ghi /O da dyng 2~ GPEOR2 (General Purpose /O Register 2) - Thanh ghi 1/O da dyng 1sGPIOR1 (General Purpose 1/0 Register 1) - Thanh ghi 1/O dadyng 0— GPTORO (General Purpose I/O Registor 0) oe 7 > es 2 0 oxo) Ce] crore a av ives go No RY 0 0 0 co 0 on Mis MY ss 2 cosioany Cae] TEE] #08 Penne OR EB aves = 0 No 0 = ot rNA_ ss se : A cae ae] EC Renate TB wives = 0 Hinh 2.20; Cac thanh ghi da dung GPOIR2,GPIOR 1,GPIORO 2.5.6 Cae thank ghi h § dinh thai (Timer/Counter Register) ATmega324P 06 3 b6 dinh thoi (Timer/Counter) o6 nhiéu chite ning manh. Bao gém ‘Timer/Counter0 8 bit, Timer/Counter1 16 bit va Timer/Counter2 8 bit. Hot dong cita cdc b6 dinh thoi doc dién khién béi céc thank ghi Timer. Céc thank ghi nay duge tim hiéu ky trong dong 7. ac Tin VA Nie sp cng 2 BB Ain fig Te OHBSCTPHSCNS asBang 2.8: Tom tit cic thanh ghi bd dinh thei BO Timer |__ Dia chi Ten Thanh ghi Chie nang BO nhs | VO Timer [0x44 | 0x22_ [ TCCROA Dieu Khien Timer A Ox45__ [0x25 | TCCROB Digu khien Timer0 B 0x46 [0826 | TCNTO BG dém TimerO 0x47 [0827 [OCROA So sinh ngé ra TimerO A Oxa8__ [0x28 _| OCROB So sinh ngé ra Timer B 0x35__[Ox15_ | TIFRO Carbio ngit Timer0 OK6E TIMSKO Che ngit Timero Timer! [0x80 TCCRIA Dieu khien Timer A Ox81 ‘CCRIB Dicu khien Timer] B Ox82 TCCRIC Dieu khien Timerl C Ox84 TCNTIL BG demic Timer! byte thap Ox85 TCNTIH Bg.dém Timer! byte cao 0x86 ICRIL Bat ngb vio Timefl byte thiap Ox87 ICRI Bifug6 vio Timetl byfe cao 0x88 OCRIAL So'Sinh nga raTimerl A byte thap 0589 OCRIAH So sinhihgé ra Timer! A byte cao Ox8A OCRIBL, So saith rgd. Timer! B byte thap Ox8B OCRIBE Einh igs ra Timer! B byte cao 0336 [0x16 | TIFRT Co bie ngit Timer Ox6F TIMSKI Che ngit Timer! Timer | 0xBO TECR2A Dieu khien Timer2 A OxBI TCCRB Dicu khien Timer2 B OxB2 TCNT? BG dém Timer? OxBe OCR2K So sinh ng6 ra Timer? A OBA, OER So sanh ngé ra Timer? B OxB6 ASSR Trang thai bat dong bo 0337 [ 0x17) TIFR2 Cé bao ngat Timer? OxT0 TIMSK2 Che ngit Timer2 0x43 \[0m3_[GTCCR Digu khign Timer chung 2.5.7 Cac thanh ghi cong néi tiép (Serial Port Registers) A’Timega324P c6 thé truyén ndi tigp véi nhiéu phuong thite SPL, USART, TWI gitip lam vige linh hoat véi ede ngoai vi. Cée thanh ghi digu khign cng néi tigp cing s€ duge trinh bay trong churong &, Bang 2.9: Tom tiit cdc thanh ghi céng ndi tigp Cong Dia chi Tén Thanh ghi Chic nang néitiép [BOnho | VO SPI 0x26 Digu Khign SPI 0x2D ‘Trang thai SPI Ox2E_[SPDRO. Dir ligu SPI Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCMUSARTO [0x0 Trang thai va diéu khién USARTO A’ OxCI ‘ang thai va dieu khien USARTO B OxC2, ‘Trang thai va dieu khien USARTO C OxC4 Toc dé baud USARTO byte thap OxCS, Toe do baud USARTO byte cao OCG Dir ligu xwat/nhip USARTO USARTI | 0xC8 UCSRIA Trang thai va dieu khien USARTIA OxC9) UCSRIB ‘Trang thai va digu khign USARTI B OxCA UCSRIC ‘Trang thai va diou khien USARTI C OxCC UBRRIL Téc d6 baud USARTI byte thap OxCD UBRRIA, Toe dé baud USARTI byte cao OxCE, UDRI Di ligu xuatinhap USARTI TWI OBS TWBR Toe a6 bit TWI OxB9) TWSR Trang thai TWI OxBA TWAR Dia chi (slave) TW OxBB TWDR Dir Ligue WI OxBC TWCR DigukhionTWI OxBD TWAMR Ghe diajchi (slavey DWI 2.5.8 Cac thanh ghi bd ADC va b@ so sinh turoiigsty ATmega324P c6 b6 chuyén doi ADO 10 Bit va bé s¢ sinkyufong tw. Viée digu khién hoat dong ciia ADC va bd so sénh cfing dinyei@thanh gliis®dhro€ xem xét trong chuong 9. Bang 2.10: Tom tit ede thanh ghi ADC va b@’so sinh Dia chi én Thankghi Chie ming Bonhs [70. BOADC | 0x78 ADC Dir ligu ADC byte thap 0x79 ADCHL Dit ligu ADC byte cao ONT ADCSRA, Trang thai va diéu khign ADC A OMB. ADESRB Trang thai va digu khign ADC B Os7 ‘ADMUX ‘Chon kénh ADC O87 DIDRO ‘Clim ng6 vao 86 0 Bo so sinh [0x50 O80 | ACSR Trang thai vA digu Khign b6 so sinh tuong tyr AC | Ox7F DIDR1 ‘Cam ngé vao 86 1 2.5.9 Cac thanh ghi ngit (Interrupt Registers) Ngit la yéu cau tir ngoai vi, vi vay ngit cla ATmega324P 06 ngit tir cdc ngoai vi bén trong nhu bé dinh thi, céng néi tigp, b6 bién déi AL ‘va cae ngat tir cac thiét bj ngoai qua vin /O, Cac thanh ghi diéu khién ngit eiing sé duge trinh bay trong chuong 10. Bang 2.11: Tom tit cac thanh ghi ng? Dia chi Tén Thanh ghi ‘Chie nang BOnhs | VO 0x55, 0x35_| MCUCR Digu khién MCU ‘0x69 EICRA, isu khign ngat ngoai 0x3 | Oxi [EMFR ‘Cd bao ngit ngoai Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM Py0x3D__| 0x1D. ‘Che ngat ngoai Ox68 Dieu khign ngat Pin Change 03B | 0x1B | PCIFR Cb bao ngit Pin Change 0x68 PCMSKO ‘Che ngit Pin Change 0 Ox6C POMS ‘Che ngat Pin Change 1 Ox6D_ POMS ‘Che ngit Pin Change 2 0873 PCMSK3 Che ngit Pin Change 3 2.5.10 Cite thanh ghi hé théng Cae thanh ghi nay 6 lién quan cde phin cimg hg théng nhw bo dao dong, mach reset va cde ché 46 gidm sit ngudn cing nhigu ché a6 nghi. Tat ci sé doc trinh bay riéng trong cac phan tiép theo trong chuong nay. ‘iu hoi dn tap 1. Thanh ghi SREG e6 bao nhigu bit? 2. Thue thi nh ADD R16, R17. Hay cho biét gid tri ca€éc cd trong thank ghi trang thai SREG thay d6ira sao Khi thye hign xong Ignh,v6i n6i’éufig thanh ghi dia R16 va R17 Kin Iuot trong cde truong hop sau: a. OXx9F va 0x61 b. Ox75 vaOXGA, ef OK16 va OxXEA 3. Cho bist gid tri diu cua thanh ghi SP 1& baowhicu Tai sao? 4. Thanh ghi SP 6 bao nhiéu bit? Tai sao? 5. Cau tric LIFO (Last In First Out) ctia figan Sép 1a nhunthé,nao? 6. Voi SP = $0700, khi thuc hién xong lénh PM'SH R20, thisP thay doi ra sao? 7. Cho biét chite ning ciia cde thanh ghi/DDRx, PORTS, PINx (véi x la A, B, C, D) 8. Cho biét ¥ nghia cia doan chuong trinh sau: LDI R16, 08OF OUT BDRB)R16 9. Viét doan chong trinkigauli’gia tri SOF FaPort A. 10. Vit doan chwong thihh nkiip dixJighsiPPort D va cit vao thanh ghi RS 2.6 XUNG NHIP HBDHONG (SYSTEM CLOCK) 2.6.1 Dac diém hé théng.xtng nhip 2.6.1.1 Hé théng xuninhip ‘Xung nhhip (Clock) can thiét cho cac hoat dng co ban ctia 1 hé théng vi chu ky thue hign 18th, dinh thi truy xuat b6 nhé, giao tigp ngoai vi ... Tan s6 xung nhip quyét dinh tée dé thu thi cac 1énh trong chuong trinh. AVR 06 nhiéu loai sung nhip cho CPU va ede thanh phin ngoai vi bén trong. Cac xung nhip nay khong edn thiét hoat dong cing lic. Dé tiét kigm dign nang, xung nhjp thanh phan nao khong ding thi c6 thé treo hay chuyen sang ché d6 ngu. elkcpy xung nhip nay cung cap cho hoat dong cita 161 AVR. elkio xung nhip nay cung cp cho ngoai vi nhwr b6 dinh thi va giao tip ndi tiép. celkriast sung nhip ni ip cho giao tigp b6 nhé Flash, ‘elkasy xung nhip nay cung cap cho b6 dinh thoi bat ding bd. elkape xung nhip nay cung cp cho bé bién dai ADC. cung Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM 28somarenem | | Ganacl 10 aoe lI cPU cow ram Fanand S| amos origi ae Sm 7+ feat Looe | | natcioe Tne EF are dock hon cok Spon Ok Wana nas eta? Tema ca ‘ong Taam Re ‘Oncor steal Coe schator Sate Oeste ‘Osatator Hinie2221: Phirhbs/céesang nhip. 2.6.1.2 Chan néi b§ dao Gog thach anh C62 chin kéynéi NTALI va KTAL2Gi bG dao dhng thgch anh. Ngo ra XTAT2 6 thé ding am ngitéiiycting nhip chOvcé6 thiét bi bén ngodi. C6 thé thay dao dng thach anh bing b6 cong hieng gom. Sty xTAL2 Stat GND ‘Hinh 2.22: Két néi dao déng thach anh Ty dig Cl va C2 o¢ gid ti bing nhau. 2.6.1.3 Ngo ra xung nip (Clock Output) ATmega324P 6 thé xudt xung nihjp hé théng qua chin CLKO (chin PB1). Dé kich hoat ng6 ra xung nip, céu chi CKOUT phai durge 1p trinh (xem muc2.9.1). Ché d6 nay piri hop khi xung nhip duge st dung dé diéu khién cac mach khac trong hé théng. Bat ky nguén xung nhip mio, bao gdm ca b§ dao ding RC bén trong, dén co thé duge chon xual ra chin (Calo Trich VM 29 Checoreg 2 Bb Min Bide Tie DHBETPHOM 2CLKO, Néu sit dung b6 chia ty Ig xung nhip, thi no sé 1a dau ra cua xung nhip hé thong da chia, 2.6.1.4 Trinh ty khi dng xung nhjp (Clock Start-up Sequence) Bat ky nguén xung nhip nao ciing cin c6 Vee vita di dé bat diu dao dong va mét sé chu ky dao dng t6i thigu truse khi:n6 c6 thé duge coi Li 6n din, Dé dam bao Vee vira di, c6 thém khoi dong (reset) ndi voi d6 tré thoi gian cho (trour- time-out delay) sau tit cd ede ngudn khéi déng khie két thiic. D6 tré (trout) durge tinh tir bd tao dao dong gidm sat Watchdog vi mot s6 chu ky tr duge dat béi cde bit cdu chi SUTL. va CKSELO. Dé tim hiéu chi tiét hon vé vin dé nay, cin doe thém data sheet ctia ATimega324P. 2.6.2 Cac ngudn xung nhip ATmega324P cé nhiéu ngudén xung nhip khac nhau, Xung nhjp tir nguén dao thach anh, dao déng RC bén trong hay ngudn dao dong ngoai. Nguon xung nhip dé dura dén hé théng duge lua chon bing cac bit ciu chi CKSEL3..0 dirge trinh bay & muc 2.9.1. Bang 2.12 Tiy chon ngun xung nhip Tay chon xung nhip thiét bj (Device Clocking Option) CKSEIS.0 BG dao dong thgch anh cong suat thap (Low Power Crystal Oscillator) W111 - 1000. BG dao dong thach anh toan tam (Full Swing. Crystal Oscillator), O11 0110. BG dao dong thgch anh tin s6 thap (Low frequeney Crystal_Oscillator) | 0101 - 0100) BG dao dong RC ngi 128kHz (Internal 128kHZRC Osciliter) oon B6 dao dng RC ndi higu chinh duroe (Calibrated Internal RC Oscillator) 0010 Xung nhip ngoai (External Clock) (0000 Dy trit (Reserved) (0001 2.6.2.1 BO dao dong thath Anh, cong suat thap-(Low Power Crystal Oscillator) Dao dong thachyarth.nay 1a bélfa,dao ding edng suat thap, voi gidm thiéu dign dp 6 ng6 ra XTAL2 Jéf'ehO mire tiéu thy dign nang 1a thép nhat. Nhung khéng c6 kha nang tao ngudn sung choigde [JO khée Benfigdit chip khi can sung nhip. 26 tao dao'tng cong suitthip c6 thé hoat ding 6 ba ché d6 khée nhau, méi ché duge tdi uu héa cho mgt daiytin s6 cu thé, Cac ché 46 nay duge chon bai cde edt chi CKSEL3..1 Bang 2.13: Gic ché'@9 dao dng thach anh céng suat thip_ Dai tin sé (MHz) CKSEL3..1__| Gia tr] ty dign dé xudt Ci va C2 (pF) 0.40.9 100 : 0.93.0 101 12-22 3.08.0 110 12-22 8.0 — 16.0 1 12-22 Cha ¥ trang hop dai tin sé 0.4MHz — 0.9Mhz (CKSEL3..1 = 100) khéng ding thach anh ‘ma chi danh cho bé eéng huring gém. 2.6.2.2 BG dao dng thach anh todn tim (Full Swi tal Oscillator) B6 dao dong nay c6 mic dign Ap t6i da 6 ngé ra XTAL2. BO dao dng nay ¢6 ich trong, vige tao nguén xung nhip cho ede /O bén ngoai va khi Lim vige trong m6i trong mhisu. ito Trin ViXiLS Chong 2 26 Men Dign Ti DHBKTPHCM 30Chii ¥ 14 bd dao déng Full Swing hoat déng vi dign ép Vee tir 2.7V dén 5.5V. Bang 2.14 Dao dong thach anh toan tam: Dai tan 5 OTH) CKSEL3.1 | Gia tr] ty dign dé xuat Cl va C2 (pF) 0420.0 on 12-22 2.6.2.3 BG dao dgng thach anh tn sé thap (Low Frequency Crystal Oscillator) é thu hién cae mach cin tidu thu céng suét thép thi xung nhip cin 6 tin 36 thdp. ‘Bé dao déng thach anh tin sé thép choc téi wu héa dé siy dung wéi thach anh déng hé 32,768 ‘KHz. Khi chon thach anh, edn cha ¥ dén dién dung tai va tré khéng nditiép tong dong cia, thach anh (ESR - Equivalent Series Resistance). C& hai gid tri déu duoc chi dinh boi nha cung cap thach anh. 2.6.2.4 BG dao djng RC noi 128 KHz (128K Hz Internal Oscillator) Bé dao déng 128 KHz 6 céng sudt thép va danh cho hé théng khéng cn 46 chink xae cao, Dé chon b6 dao déng nay thi cau chi CKSEL3..0= 0011. 2.6.2.5 BG dao ding RC nGi higu chinh dugc (CalibratedInternakRC Oscillator) Bé dao dong RC ndi direc ding véi tin oS TS Mz khi thiét lip ofa chi CKSEL3..0 = 0010. Thém v6i cdu chi CKDIVS duoc Lap trink\(tem mye.2.91), bd chia § tin 36 droc thye hign, xung nhip bé thong se la I@MHZ. Day la nguén \xufg nbip danh dinh cia ATmeg3324P khi xuat xudng. Lie nay héthdng xung thip hoa dong ma khéng can bat ky thanh phan nao bén ngoai, Do bé dao d6ng RC phulthuge Vao ngudmdién dp, va nhidt 46, tin sé cé thé thay adi tir 7.3 MHz dén 8.1 MHz. Vi'vajeodin-higu chinh dé tin sé chinh xe 8 MHz, ding thanh ghi OSCCAL (Oscillator Clibration Registé?), et 2 1 (ox) A aa Reaawme a AW Init Vat Bute Specie Calaton Value Hinh 2,232Dhanti'ghi OSCCAL higu chinh tin sé dao dong ngi 2.6.2.6 Xung nhip ngoal\(EXternal Clock) Khi CKSEL3,,0 +0000, mot nguén xung ngoai cé tan 26 téi da 20 MHz ¢6 thé ding trong hé ne xtaz EXTERNAL clock ————| _XTALI SIGNAL GND ‘Hinh 2.24; Xung nhip ngoai dua vio MCU Rito Drink Vi Mie Lp Chagone,? BS Adin itn Tie DUBKTPHCME a2.6.3 BG ti 19 xung nhip hg théng (Systom Clock Prescaler) Nhu hinh 2.21, ta thy xung nhip hg théng sau khi lya chon duge dura qua 1 b6 chia tn 96. Tinh nang nay c6 thé duoc ai dung dé giam tan 96 xung nhip hé théng va mic tieu thy dién nang khi hé théng c6 yéu cin vé céng suat xi ly thap, Bé chiatan s6 duoc chon Iva theo nhting ti lé khde nhan, duoc thiét lap quathanh ghi CLEPR(Clock Prescaler Register) et pose os SSE ERS TSO] oxen Reeve iniaVae = See BA Deseipton Hinh 2.25: Thanh ghi CLKPR thiét lap ti 1é chia tan s6 xung nhip. * Bit 7—-CLKPCE: Cho phép thay d6ibé chiaxung nip (Clock Prescaler Change Enable) Bit CLKPCE phai duge ghi gid tri1 dé cho phép. Bit CLKPCE chi dwoc cap nhat khi cée bit cdn lai La 0. Nghia 1a ghi vao thenh ghi CLKPR gid tri 0x80. Bit CLKPCE se duoc x6abéi phan cting sau bén chu ky sau khi ghi. © Bit 3:0 - CLKPSn: Chon ti l@ chia xung nhip (Clock Prescaler Selext) Cac bit nay xac dinh hé sé chia gita nguén xtihg hip va xung nhip hé théng bén trong. Céc hé 86 chia duge chon theo nhu bang drs, day> Bang 2.15: Chon hra hé sé chia CLKPS3 | CLKPS2 | CLKPS1, | CLRPS®, Hé si chia dock (Clock Division Factor) 1 2 4 8 16 32, 64. 128 256 Dy iri, Dy int Dy tri Du tri, Dy tri, Dy i Dy wy Cha y 1a khi ghi hé sé cdm chon vao thanh ghi CLKPR, thi bit CLKPCE phai ghi gia tri 0 (vi du chon b6 chia 8 thi gia tri ghi vao thanh ghi CLKPR a 0x03). Va viée ghi gid tri nay phai diroc thuc hién san khi cho bit CLKPCE gié tri 1 trade dé trong ving 4 chu kj. ‘Néu khdng vige chia xung nhip da lwa chon sé khéng duoc thyc hign. Cito Trish NLP Chansng 2 BO hide Biba Te DEBRTPHCM 2Cau hoi On tip 1. BG dao dong danh inh nao duge chon khi sin xuit? Tai sao? 2. Khi d6 chu ky Ienh cia CPU 1a bao nhiéu? Tai sao? 3. Néu sir dung thach anh bén ngoai li 16MHZ, va str dung b@ ti Ig 18 bao nhigu dé xung nhip hg théng c6 tin s 1a IMHz 4, BS 6 tile chia tan s6 la 64, gid tri ghi vio thanh ghi CLKPR fa bao mhigu? 5. Mudn chan CLKO (chan PB1) lam nguén xung nhip thi phai Lim gi? 2.7 KIEM SOAT NGUON VA CAC CHE DO NGU D6i véi 1 86 hé thong vi diéu khién, viée kiém soat nguén gitp cho cdc yéu cau thiét ké can tiét kigm nang hrong. AVR c6 nhiéu cach dé gidm tiéu hao nang ltrgng nhur li cho sit dung ede ché d9 ngii (Sleep Modes), tit bd phat hign sut sp BOD, 2.7.1 Cac ché 49 ngit (Sleep Modes) Ché d6 ngui cho phép img dung tit cae khdi Khong str dung trong MCU, do do tiét kigm nang long. AVR cung cap cae ché dé ngu khac nhau cho*phép nguéi ding"Gigu chinh mire tigu thu nang hong theo yéu céu cita tmg dung. ATmega324P 06 6 ché dd ngu: nghi (Idle), gidim nhiu ADC (PE Noise Reduction), tit nguén (Power-down), tiét kigm nguon (PowersSaye). cher (Standby), va cho mo rong (Extended Standby). Ché d6 nga sé duge thyethiBaing [enh SEPEP! Khi MCU vao ché 49 ngi, mot ngi(dude kich Heglxayyta lam MCU bj én there (wake-up). MCU thue hin qua trinh ngdt va tiép tue thitehigh,lénh sau SLEEP. Noi dung cia tip thanh ghi va SRAM khéng thay d6i Khi thigt bi.thite gy the ché 46 ng. Néu e6 reset ay ra trong ché d6 ngi, MCU eding's@-danb thite va,thye'thi tir dja chi reset. 2.7.1.1 Ché d@ nghi (Idle Mode), 6 ché d9 nay, CPU ngung hojedgn¥nhung cac ngoai vi (SPI, USART, b@ so sanh tuong tu, ADC ygiae tgp 2 day TWI,\¥6 dinh thoi/bd dém) va hé théng ngit tiép tue hoat déng. Ché d6 ga nay ve co bin wanting clkcru va clksiasn. trong khi cho phép cée xung nhip khae vin cha(sem ede kigtygung nhip hinh 2.21), ‘Ché 46 nghi cho'phép MCU bi danh thite tir cae ngit ngoai cing nhw cae ngit ndi. 2.7.1.2 Ché d6 giant nhiéd ADC (ADC Noise Reduction Mode) G ché dmnayyCPU ngumg hoat dong nhumg edie ngoai vi (SPI, b6 so sinh twong ty, ADC. giao tiép 2 diy TWI, bé dinh thoi/bd dém2. ngit ngoai) va hé théng gidm sat watchdog, tigp tue hoat ding. Ché d ngii nay vé co ban tam ditng elkcro, clkrtasi va elkvo, trong khi cho phép ede xung nhip khée vin chay (xem cdc kiéu xung nhip hinh 2.21). Disu nay cai thign méi tung nhigu cho ADC, cho phép cae phép do c6 d§ phan giai cao hon. Neu ADC durge cho phép, qué trinh chuyén doi s8 ty déng bit dau khi vao ché dé nay, ‘M6t trong cac digu kign dé hé théng thoat khoi ché 46 ngu nay: - Cae ngit: ADC, ngit ngoai, PCINTT:4 (chi ngét mite), Pin change, Timer2, SPM/EEPROM, watchdog, - Giao tiép 2 day TWL ~ Céc reset: ngoai, watchdog va Brown-out. Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM 22.7.1.3 Ché dé tit nguén (Power-down Mode) G ché d9 nay, bé dao dng bén ngoai bj dimg, do do cic xung clk déu dimg. Chi co cae ngit ngoai, giao tiép 2 diy TWI va hé théng gidm sat watchdog tiép tuc hoat dong. Ché 449 nay v8 co ban sé tam dimg tit ea eae thanh phin sung mhip, chi cho phép hoat dng khong dong b6. 1 kign dé he théng thost kh6i ngii niy; - Céc ngit: ngit ngoai, PCINT7:4 (chi ngat mite), Pin change, watchdog. = Giao tigp 2 day TWI. - Cie reset: ngoai, watchdog va Brown-out. 2.7.1.4 Ché dé tiét kigm nguén (Power-save Mode) 6 ngut giéng voi ché d6 tit ngudn, nhung khée 1a khi cho phép Timer2 hoat dong thi né vin chay trong ché 49 ngi. Khi d6 hé théng sé durge danh thite tir ngit Timer2. Néu khong sit dung Timer2, thi nén str dung ché d6 tit ngudn, 2.7.1.5 Ché dé cha (Standby Mode) ngudn, nhun@Khac [%cé str dungnguén xung nhip tirthach anh hay bé edng husng gém ben ngoai. 2.7.1.6 Ché dé cho ma rong (Extended Standby. Mode) Ché d6 ngit gid 1g voi ché do tiét‘KignTngtdn, nbung khat 1a co str dung cdc bé dao dong. Bing 2.16 Tom tit hoat dong cua cée ehé.d6 nga Wangielock Ngudn dank thire ogt dong ldao don; (wake-up) CHE dp ngs a] 5 ls (Sleep Mode), fee] 2 B eile E| fe 3 gee ¥ i Ble ESES|R S|, S ie ase ls fe 2 22 2aEs{82\2 Es Nahi (Idle) x] x] x] x [x] x[x[x[x Giam nhieu ADC, xP xP x], «PETE [Po] x PK (ADCNRM) Tat nguon TK x x (Power-down) kkigm ngudn x xT] x YK " x (Power-safe) ‘Cha (Standby) x xe] x x x ‘Cho me rong, Hx [| HTT YX x x (Extended Standby) Chit thich: (1) nguén xung nhip tir thach anh hay b9 cng hung gém bén ngoai (2) Timer?2 hoat ddng ché d6 bat déng bd. (3) Ngat ngoai INTO 1a ngiit mite. Cio Trinh ViXGLS Chime? ‘BB Mén Difn T#DHBKTPHCM au‘Thanh ghi diéa khién ché d@ ngi SMCR (Sleep Mode Control Register) a poo ss st 1 ° oases) [7] A Peas LT tavae == 0 28 ‘inh 2.26: Thanh ghi SMCR diéu khién ché 46 ng © Bit 3:1 —SMn: chon ché a9 ngii (Sleep Mode n) Ce bit dé chon 1 frog. 6 ché dé ngit theo bing 2.10 Big 2.17: Chon ché 46 ngi SMZ SMI SMO Ché djngi Gleep Mode) 0 0 0 Nghi (idle) 0 0 1 Giam nhiéyADC (ADC Noise Redugtion) 0 1 o Tat nguét(Power-down). 0 1 1 ‘Tiét kigiingudh (Power-sate) 1 0 0 Dyfi. 1 0 1 Dui 1 1 0 ‘hy (Btandbyy 1 1 1 ‘Chi¥m6 rong (Extended Standby) * Bit 0 — SE: cho phép ché.d6 gui (Sleep Enable) Bit SE phdi duge ghi gift] 1dé lam choMM@U chiyén sang ché a nghikhi lénh SLEEP duge thye thi. Vigoghitiyinén thuesbign hgay née khi thye hign 1énh SLEEP va x6a né ngay sm khi MCTdH¢e dénh thite. 2.7.2 B6 phat igri BOD) (Brown-Out Detector) AYR 6 bé phat hiéifsut 4p'ngudn Brown-out (Brown Out Detector - BOD) sé cha dng giam sat dién 4p ngudn trong thoi gian nga. BG BOD duoc cho phép bing cae cau chi BODLEVEL (xem muc 29.3eKhi dign ap Vec thap, dirligu EEPROM 6 thé bi hong do dign 4p cung cip qua thip % CPU va EEPROM hogt dng binh thurgng. Bé BOD c6 nhigm vu phat én sut ép durdi guong tho phép, néu cé thi sé reset CPU. Khi Vcc ting tré Iai trén mite kich hoat, b6 BOD thoafkhoi trang, thai reset. CPU bat dau Lam viéc sau khi chu ky time-out két thi. Dé tiet kim nang hrong, co thé tat BOD bang phan Néw BOD bj cim bing phin mém, chite ning BOD sé bi cam ngay sau khi vao ché Khi bj danh thirc, BOD sé ty dong duge cho phép tré lai. ‘Trong thanh ghi MCUCR cé cae bit diéu khién cam/cho phép bé BOD. ‘Thanh ghi didn khién MCU - MCUCR (MCU Control Register) Geto Trinh VM bp Chong 2 185 Min Bién Tie DBKTPHICEA 35at 2 1 ° « 5 3 oxas cass) [Wt] S008 “soos [FO ET] vcucr Feoarite 7 TP Inia Vaue ° ° a o 09 0 2 Hinh 2.27: Thanh ghi MCUCR cho phépfeém BOD © Bit 6 - BODS: ngii BOD (BOD Sleep) Bit BODS phai duge ghi gid trj 1 dé tit BOD trong ché 49 nga. Viée ghi vao bit BODS duge diéu khién béi mét trinh ty thi gian va bit cho phép BODSE, Dé tit BOD trong cae ché 49 ngii lién quan, ca hai bit BODS va BODSE truce tien phai duoc ghi gid tri 1. Sau d6 dé thiét Lap bit BODS, BODS phai duge ghi gia tri 1 va BODSE phai duge ghi gid tri O trong vong bén chu ky xung nhip. Bit BODS tich eye ba chu ky xung nhip sau khi no duge thiét lap. Lénh SLEEP ph duge thye hign trong khi BODS dang tich eye dé t BOD cho ché a9 ngit thye 18, Bil BODS sé tw dong bi x6asau ba chu ky xung nhip. * Bit 5 — BODSE: cho phép ngii BOD (BOD Sleep Enlble) Bit BODSE cho phép thiét lap bit diéu khién BODS, sihur durge giaf thich trong phan mé tabit BODS. Vige v6 higu hoa BOD dirgekigm Seat boi mGbtrinh tit théi gian. 2.7.8 Thanh ghi giim ning krgng PRR (Power Recduction Register) Thanh ghi gidm nfing long (PRR)-cung cp méfplittodg php ding xung:nhip cho cic ngoai vi riéng lé dé gidm tien thy @ign ning. Trang\théi hign (gi cia ngogi vi bi ding bing va Khong thé doc hoe ghi cic than. ghiWO. Cac tai nguyen cege sir dung béi ngoai vi khi dimg xung nhip sé vin bi chiéméduige Do 46, trong \hthhét cdc trudng hop, ngogi vi phai bj cfm trade khi dimg xung nhijps Vigodanh thie ngoat¥i, ange thuc hign bing cach x6a bit trong tng trong PRR, lam chosio Setrang thal ging hu trude khi t&. Ché 6 tli. ngoai vi c6 thé dude st dung 6 ché 43 nghi va ché 46 hoat déng dé gid dang ké mitc tiéu thysiaing luong ting thé. Trong tat ca céc ché d6 ngii khéc, xung nhip da bi ding Thanh ghi gidm nang lttqng@— PRRO (Power Reduction Register) a 7X ‘ o ' ° os [Pane | Farm] [FRO FRUGARTE | FRADE] Pano Fn 6 intnVowe = «8 ° 0 0 ° Hinh 2.28: Thanh ghi PRRO diéu khién giam nang lugng * Bit 7- PRT WI: gidm ning lvong TWI (Power Reduction TWI) Vige ghi gid tri 1 vao bit nay sé ngung hoat déng giao tiép 2 day TWI bing cach ding xung nhip dén n6. Khi dénh thite TWI mot lan nua, TWI nén duge khéi tao lai dé dam bao hoat dong binh thang. © Bit 6 — PRTIM2: giém nang long Timer2 (Power Reduction Timer /Counter2) Cito Trish NLP Chansng 2 BO hide Biba Te DEBRTPHCM 6Vise ghi gid tr 1 vao bit nay sé ngung hoat dong bd Timer2 6 ché d6 dong b>. Khi bo ‘Timer2 duge cho phép, hoat dong sé tiép tue nhw truée khi ngung. © Bit 5 PRTIMO: gidm ning long B6 Timer0 (Power Reduction Timer /Counter0) Vige ghi gid tri 1 vao bit nay sé ngung hoat dong bé Timer0. Khi bO Timer0 durge cho phép, hoat dong sé tip tue nhur rude khi ngumg. © Bit 4— PRUSARTI: gidm ning long USARTI (Power Reduction USARTI1) Vige ghi gia trj 1 vao bit nay sé ngung hoat déng USART1 bang cach dimg xung nhip én no. Khi dinh thite Iai USARTI, USARTI nén dite kha t90 Iai dé dim bao hoat <9ng binh thing © Bit 3 — PRTIMI: giim nang hrong B6 Timer (Power Reduction Timer /Counter1) Vige ghi gid tri 1 vao bit nay sé ngung hoat déng bé Timerl. Khi bé Timer! dutge cho phép, hoat dong sé tigp tue nhur trade khi ngumg, * Bit 2 — PRSPIO: giém ning lugng SPI Power ReduiGtidn SPI) ‘Vide ghi gid tri vio bit nay s& ngumg hoat ding Biao tsp ngosiyi nditigp SPI bing eich dimg xung nhip dén n6. Khi dinh thite SPP mL fin ntta, SPIphenduge khdi tao lai dé dim bao hoat dong binh thuong. © Bit 1 — PRUSARTO: giim ning hrgfg MSARTO (Power Reduction USARTO) Vige ghi gia tri 1 vao bit nay sé ngung héat dong SARTO bing céch dig xung nhip én n6. Khi dinh thite lai USARTS, USARTO néhaduge khéi tao lai d3 dim bao hoat dng binh thuimg, © Bit 0 PRADC: gidinndn@ liong ADC.(Power Reduction ADC) Vide ghi gid tri | vagibit nay sé ngung hoat déng bé bién d6i ADC. B6 ADC phi ‘tude khi tat, 139 86{sinh tong. khong'the sir dung bo MUX dau vao ADC khi bg ADC jam thiét mite tiéy thu Ming Iwong, ché 49 nga nén duge sir dung cang nhiéu cing 161. Tat ea cae chite ning khongean thiét nén duge tit. Neoai ra, edn ede kha ning khde e6 thé cling giam mite tien thy, thainkhdo them data sheet cla ATmega324P. 2.8 DIEU KHIEN HE THONG VA RESET ‘Trong khi feset, tat ca cac thanh ghi /O duge dit lai gia tri ban dau ctia ching va chuong trinh bat dau thye hign tir dia chi reset (reset vector). Lénh dit tai dia chi nay phai la Ignh nhay tuyét déi (JMP) dén chong trinh xtr ly, Néu chuong trinh khong sir dung ng: cde vector ngit sé khong duge sir dung va chuomg trinh ed thé durge dat tai cae dia chi nay. ‘Truong hop nay ciing xay ra néu dia chi reset nam trong ving img dung (Aplication section) trong khi cdc vector ngit nim trong ving khéi d$ng (Boot section) hode nguge lai, Cac céng I/O etia AVR ngay lap tite vé trang thai ban dau khi nguon reset hoat dong. Digu nay kh6ng yéu cau bat ky nguén xung nhip nio dang chay. ‘Sau khi tat ca cde ngudn reset khong hoat dong, bo dém tao tré sé duge kich khoi, kkéo dai qua trinh reset bén trong. Diéu nay cho phép ngudn dign dat mute én dinh trude khi bat dau hoat déng binh thudmg. Khoang thai gian ché trour (time-out) cita b6 dém tao tré duge xae dinh béi vide thiét lap cdc bit cdu chi SUT va CKSEL. Gio Trinh VIXiLS Chuomg 2 26 Men Dign Ti DHBKTPHCM 3Sau khi reset, néi dung cia dasé céc thanh ghi thuong doc x6a.Vi du nhw tap thanh ghi hay thanh ghi PC = 0x0000. Céc Port déu 1a ngé vio do cc thanh ghi DDRx = 0x00. sta U5 WCU Slate egster(NCUSA) ri Paveron Reset ‘creut Bomod BODLEVEL 1.0] eset Grout Pulp Resistor waendea ‘ener BouvreR Reser i Wena Oxilace Cocks fox} Oey pte, osrertie TIMEOUT cxsEUS. surfia Hinh’2.29: Logie khdi reset 2.8.1 Cac nguén Reset ATmega324P cb Dnghdst reset 2.8.1.1 Reset benguén (Power-on Reset) Xung Power-on Reset (POR) tugc tao ra bai mot mach phat hién trén chip. POR drgc kich hoat bat cit khi*ndo Vee & dudi mite dign 4p nguéng Vrot (Power-on Resset ‘Thershold) (xem bang 211 plifa duéi). Mach POR co thé duge st dung dé kich hoat reset khei dng, cing uhu dephirhign sy cé vé dign ap cung cap. vec vec 10K RESET Hinh 2.30: Chan RESET néi nguén Veo ac Tin VA Nie sp cng 2 BB Ain fig Te OHBSCTPHSCNS 2Mach POR dam bao ring thiét bi diroe reset khi bat ngudn. Khi dat dén dién ap nguéng Voor, sé kich hoat b6 dém tao tré. bé dém nay xac dinh khodng thoi gian thiét bi durye git thém trang thai reset sau khi Voc ting. Khi hét thoi gian nay thi MCU hoat déng binh throng. Khi Vee lai giam xudng ehréi mite phat hign, tin higu reset 14p ture duoc kich hoat tré lai ma khéng c6 thém bat ky thoi gian tré nao, TE Noor Yor ‘ RESET Fy Nrsr Tweout ta —4 INTERNAL PC RESET ‘Hinh 2.31: MCU Khoi déng, chan RESET néi nedén Ae 2.8.1.2 Reset ngoai (External Reset) Mach reset bén ngodi tqo ra tin higitie exe thip tte) dua vito chan RESET cia MCU. Xung reset phi dai hom d6 réngoung t6i thiGu*(xehrbing 2.18) sé wo raresel, ngay iki khong c6 xung nhip. Nhithg xung ngén hohkhong'dim bao dé tgo ra reset. vec, 10K RESET A Fone Hinh 2.32: Mach reset ngoai Khi tin higu reset dn dign dp nguing Vesr tren eanh dirong eta né, 8 kich hoat bd dém tao tr8 tgo thém khoang thi gian reset. Khi hét thai gian niy thi MCU hoat déng binh thurtng, Gide Trinh Hi 1} Chaseng ? 23 Man Digu Te DHBETPHCM 3Veo RESET we-our en INTERNAL RESET Hinh 2.33: Tin higu reset ngoai 2.8.1.3 Reset Brown-out (Brown-out Reset) ATmega324P co mach phat hién sut ap BOD, c6 phiém vy gidm sat dign ap nguén ‘Vee trong lic he thong hoat déng bing cach so sanh voice dign ap nguéng Yeo: (Brown- ‘out Reset Thershold). Vgor thy theo clu chi BODLEVEb (xem bang 2,25 o:mue 2.9.3). Mire ign ap nguéng cé dé tré dé tranh BOD thay d6i,d6t ngdt. Dé tré én BOD co thé higu 1a Voor = Voor + Vivev?2 va Veor- =Vuor- Vavstlt Khi BOD durgt kich hoat va Vee gidmxndng Bid tri,dugimtie Voor. , reset Brown- out ngay lap tite duge kich hoat. Sau déKhi Wee'ting wen{mtic Vecrs, sé kich hoat bé dém tao tré tao thém khoang thoi gian reset. Khihiét thoi gian ‘trou’ thi MCU hoat déng binh thong. Mach BOD sé chi phat hign sy sut giam trong"Veenéu dign ap & dirdi mitc kich hoat, dai hon tao0 (xem bing 2.11) Vee NOD Va MO a Reset) Y a»\ TIME-OUT = trour—f a rs a ‘Hinh 2.34: Tin higu Brown-out Reset 2.8.1.4 Reset hé thong Watchdog (Watchdog System Reset) B6 dinh thoi Watchdog cé chire nang diing dé reset MCU trong trudng hep chirong trinh dang chay bj 13i hay bj lap vong v6 han. Khi b6 dinh thoi Watchdog dirge cho phép, néu hét thai gian do bé dinh thai tao ra, né sé tg0 1 ung reset 4 chidn dai bing 1 chu ky sung nhip. Tai thoi diém canh xuéng cia xung nay sé kich hoat b6 dém tao tré tao them Khong thoi gian reset. Khi hét théi gian trour nay thi MCU hoat déng binh thirong. Bbo Trinh Meg Ohasong 2 BB Moy Digu Te BABKDPUC 40Reser Het exc meio e Reser inet ae-ouT 7 rena RESET Hinh 2.35: Tin higu Watchdog System Reset Hoat dng cia b6 dinh thdi Watchdog sé dirge trinh bay & phan cudi cia chong nay, Bang 2.18 Pac tinh reset Kyhigu_| Thong 58 tae [Wye | Mex [oon : Power-on Rese Tireshou votage mang) oT) 10 | Ae oot | power-on Rest Testo Vatage donna) @ Sus] 09 | Ng Vast _| RESET Pin Trreshota vonage Vier | Qo ‘esr__| Meimum puso wish on RESET By 25 |e hast | rowrrou Dotecor Hysteresis 50 wv ‘eco | Mn Paso With on Brown-outRaset z z rn 2.8.1.5 Reset JTAG (JTAG AWR Reset) MCU duge reset Midna &6 logic trong thanh ghi reset, mt trong cde chudi quét cia hé théng JTAG, Tham Rhao chi tiét trong data sheet ca ATmega324P. 2.8.2 Thanh ghi tratigthai, MCU - MCUSR (MCU Status Register) ‘Thanh ghiMCUSR cung‘eap théng tin vé cac nguén reset MCU. et ‘ e688 | Toro] cus Peace a ina Vane 0 0 Hih 2.36: Thanh ghi MCUSR thng bao cae nguén reset * Bil 4 — JTRF: co Reset JTAG (JTAG Reset Flag) Bit nay duge dat néu mét Reset dang diénra bdi logic 1 trong thanh ghi reset JTAG duge chon béi 1énh JTAG AVR_RESET. Bit nay duge x6a khi c6 Reset bat nguén (Power-on Reset) hoae bing cach ghi logic 0 vao ed. * Bit 3— WDRF: cir Reset hé théng Watchdog (‘Watchdog System Reset Flag) Bit nay duye dat néu xay ra Reset hé thing Watchdog. Bit duye xda bang Reset bat nguon, (Power-on Reset} hode bing cach ghi logie 0 vao cd. + Bit 2— BORF: cit Reset Brown-out (Brown-out Reset Flag) Ciba Trnk Wt 19 Chnsong 2 B3 Mn Din Te DHEKTPHOM a